Merge Official Source
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
commit
39f1f2670f
@ -423,6 +423,8 @@ define Build/netgear-encrypted-factory
|
||||
--output-file $@ \
|
||||
--model $(NETGEAR_ENC_MODEL) \
|
||||
--region $(NETGEAR_ENC_REGION) \
|
||||
$(if $(NETGEAR_ENC_HW_ID_LIST),--hw-id-list "$(NETGEAR_ENC_HW_ID_LIST)") \
|
||||
$(if $(NETGEAR_ENC_MODEL_LIST),--model-list "$(NETGEAR_ENC_MODEL_LIST)") \
|
||||
--version V1.0.0.0.$(shell cat $(VERSION_DIST)| sed -e 's/[[:space:]]/-/g').$(firstword $(subst -, ,$(REVISION))) \
|
||||
--encryption-block-size 0x20000 \
|
||||
--openssl-bin "$(STAGING_DIR_HOST)/bin/openssl" \
|
||||
|
||||
@ -12,7 +12,8 @@ touch /etc/config/ubootenv
|
||||
board=$(board_name)
|
||||
|
||||
case "$board" in
|
||||
iptime,a6004mx)
|
||||
iptime,a6004mx|\
|
||||
netgear,ex6250-v2)
|
||||
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x1000"
|
||||
;;
|
||||
esac
|
||||
|
||||
@ -70,7 +70,7 @@
|
||||
{
|
||||
--- a/boot/image-fit.c
|
||||
+++ b/boot/image-fit.c
|
||||
@@ -2051,6 +2051,50 @@ static const char *fit_get_image_type_pr
|
||||
@@ -2051,6 +2051,49 @@ static const char *fit_get_image_type_pr
|
||||
return "unknown";
|
||||
}
|
||||
|
||||
@ -89,9 +89,8 @@
|
||||
+
|
||||
+ hdrsize = fdt_totalsize(fit);
|
||||
+
|
||||
+ /* simple FIT with internal images */
|
||||
+ if (hdrsize > 0x1000)
|
||||
+ return hdrsize;
|
||||
+ /* take care of simple FIT with internal images */
|
||||
+ max_size = hdrsize;
|
||||
+
|
||||
+ images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
|
||||
+ if (images_noffset < 0) {
|
||||
|
||||
@ -88,11 +88,6 @@ if [ -n "${COMPATIBLE}" ]; then
|
||||
COMPATIBLE_PROP="compatible = \"${COMPATIBLE}\";"
|
||||
fi
|
||||
|
||||
[ "$DTOVERLAY" ] && {
|
||||
dtbsize=$(wc -c "$DTB" | awk '{print $1}')
|
||||
DTADDR=$(printf "0x%08x" $(($LOAD_ADDR - $dtbsize)) )
|
||||
}
|
||||
|
||||
[ "$FDTADDR" ] && {
|
||||
DTADDR="$FDTADDR"
|
||||
}
|
||||
@ -170,7 +165,6 @@ OVCONFIGS=""
|
||||
ovnode="fdt-$ovname"
|
||||
ovsize=$(wc -c "$overlay_blob" | awk '{print $1}')
|
||||
echo "$ovname ($overlay_blob) : $ovsize" >&2
|
||||
DTADDR=$(printf "0x%08x" $(($DTADDR - $ovsize)))
|
||||
FDTOVERLAY_NODE="$FDTOVERLAY_NODE
|
||||
|
||||
$ovnode {
|
||||
@ -179,7 +173,6 @@ OVCONFIGS=""
|
||||
data = /incbin/(\"${overlay_blob}\");
|
||||
type = \"flat_dt\";
|
||||
arch = \"${ARCH}\";
|
||||
load = <${DTADDR}>;
|
||||
compression = \"none\";
|
||||
hash@1 {
|
||||
algo = \"crc32\";
|
||||
|
||||
@ -14,6 +14,8 @@ def main():
|
||||
parser.add_argument('--model', type=str, required=True)
|
||||
parser.add_argument('--region', type=str, required=True)
|
||||
parser.add_argument('--version', type=str, required=True)
|
||||
parser.add_argument('--hw-id-list', type=str)
|
||||
parser.add_argument('--model-list', type=str)
|
||||
parser.add_argument('--encryption-block-size', type=str, required=True)
|
||||
parser.add_argument('--openssl-bin', type=str, required=True)
|
||||
parser.add_argument('--key', type=str, required=True)
|
||||
@ -26,6 +28,10 @@ def main():
|
||||
assert (encryption_block_size > 0 and encryption_block_size % 16 ==
|
||||
0), 'Encryption block size must be a multiple of the AES block size (16)'
|
||||
|
||||
hw_id_list = args.hw_id_list.split(';') if args.hw_id_list else []
|
||||
model_list = args.model_list.split(';') if args.model_list else []
|
||||
hw_info = ';'.join(hw_id_list + model_list)
|
||||
|
||||
image = open(args.input_file, 'rb').read()
|
||||
image_enc = []
|
||||
for i in range(0, len(image), encryption_block_size):
|
||||
@ -45,13 +51,18 @@ def main():
|
||||
image_enc = b''.join(image_enc)
|
||||
|
||||
image_with_header = struct.pack(
|
||||
'>32s32s64s64s64s256s12sII',
|
||||
'>32s32s64s64sIBBB13s200s100s12sII',
|
||||
args.model.encode('ascii'),
|
||||
args.region.encode('ascii'),
|
||||
args.version.encode('ascii'),
|
||||
b'Thu Jan 1 00:00:00 1970', # static date for reproducibility
|
||||
0, # product hw model
|
||||
0, # model index
|
||||
len(hw_id_list),
|
||||
len(model_list),
|
||||
b'', # reserved
|
||||
hw_info.encode('ascii'),
|
||||
b'', # reserved
|
||||
b'', # RSA signature - omitted for now
|
||||
b'encrpted_img',
|
||||
len(image_enc),
|
||||
encryption_block_size,
|
||||
|
||||
@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "ar9344_mikrotik_routerboard-951x-2hnd.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "mikrotik,routerboard-951g-2hnd", "qca,ar9344";
|
||||
model = "Mikrotik RouterBOARD 951G-2HnD";
|
||||
|
||||
/delete-node/ aliases;
|
||||
/delete-node/ leds;
|
||||
|
||||
gpio-export {
|
||||
compatible = "gpio-export";
|
||||
|
||||
gpio_usb_power {
|
||||
gpio-export,name = "rb951g-2hnd:power:usb";
|
||||
gpio-export,output = <1>;
|
||||
gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
buzzer {
|
||||
gpio-export,name = "buzzer";
|
||||
gpio-export,output = <1>;
|
||||
gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&ref {
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
|
||||
qca,ar8327-initvals = <
|
||||
0x04 0x07600000 /* PAD0_MODE */
|
||||
0x7c 0x0000007e /* PORT0_STATUS */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
status = "okay";
|
||||
|
||||
pll-data = <0x6f000000 0x00000101 0x00001616>;
|
||||
|
||||
phy-mode = "rgmii";
|
||||
phy-handle = <&phy0>;
|
||||
|
||||
gmac-config {
|
||||
device = <&gmac>;
|
||||
rgmii-gmac0 = <1>;
|
||||
rxd-delay = <1>;
|
||||
switch-only-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ð1 {
|
||||
status = "disabled";
|
||||
};
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "ar9344_mikrotik_routerboard.dtsi"
|
||||
#include "ar9344_mikrotik_routerboard-951x-2hnd.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "mikrotik,routerboard-951ui-2hnd", "qca,ar9344";
|
||||
@ -59,77 +59,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
nand_power {
|
||||
gpio-hog;
|
||||
gpios = <14 GPIO_ACTIVE_LOW>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
nand-ecc-mode = "soft";
|
||||
qca,nand-swap-dma;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "booter";
|
||||
reg = <0x0000000 0x0040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "kernel";
|
||||
reg = <0x0040000 0x03c0000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "ubi";
|
||||
reg = <0x0400000 0x7c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <25000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "mikrotik,routerboot-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "routerboot";
|
||||
reg = <0x0 0x0>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
hard_config: hard_config {
|
||||
read-only;
|
||||
};
|
||||
|
||||
bios {
|
||||
size = <0x1000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
soft_config {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ð0 {
|
||||
phy-handle = <&swphy4>;
|
||||
|
||||
@ -143,11 +72,3 @@
|
||||
&wmac {
|
||||
qca,led-pin = /bits/ 8 <11>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -0,0 +1,82 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
#include "ar9344_mikrotik_routerboard.dtsi"
|
||||
|
||||
&gpio {
|
||||
nand_power {
|
||||
gpio-hog;
|
||||
gpios = <14 GPIO_ACTIVE_LOW>;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
|
||||
nand-ecc-mode = "soft";
|
||||
qca,nand-swap-dma;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "booter";
|
||||
reg = <0x0000000 0x0040000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@40000 {
|
||||
label = "kernel";
|
||||
reg = <0x0040000 0x03c0000>;
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
label = "ubi";
|
||||
reg = <0x0400000 0x7c00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&spi {
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <25000000>;
|
||||
|
||||
partitions {
|
||||
compatible = "mikrotik,routerboot-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "routerboot";
|
||||
reg = <0x0 0x0>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
hard_config: hard_config {
|
||||
read-only;
|
||||
};
|
||||
|
||||
bios {
|
||||
size = <0x1000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
soft_config {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
||||
@ -48,6 +48,15 @@ define Device/mikrotik_routerboard-922uags-5hpacd
|
||||
endef
|
||||
TARGET_DEVICES += mikrotik_routerboard-922uags-5hpacd
|
||||
|
||||
define Device/mikrotik_routerboard-951g-2hnd
|
||||
$(Device/mikrotik_nand)
|
||||
SOC := ar9344
|
||||
DEVICE_MODEL := RouterBOARD 951G-2HnD
|
||||
DEVICE_PACKAGES += kmod-usb-ohci kmod-usb2
|
||||
SUPPORTED_DEVICES += rb-951g-2hnd
|
||||
endef
|
||||
TARGET_DEVICES += mikrotik_routerboard-951g-2hnd
|
||||
|
||||
define Device/mikrotik_routerboard-951ui-2hnd
|
||||
$(Device/mikrotik_nand)
|
||||
SOC := ar9344
|
||||
|
||||
@ -35,6 +35,7 @@ ath79_setup_interfaces()
|
||||
mikrotik,routerboard-map-2nd)
|
||||
ucidef_set_interface_lan "eth0 eth1"
|
||||
;;
|
||||
mikrotik,routerboard-951g-2hnd|\
|
||||
mikrotik,routerboard-962uigs-5hact2hnt)
|
||||
ucidef_add_switch "switch0" \
|
||||
"0@eth0" "2:lan" "3:lan" "4:lan" "5:lan" "1:wan"
|
||||
|
||||
@ -46,6 +46,7 @@ case "$FIRMWARE" in
|
||||
mikrotik,routerboard-962uigs-5hact2hnt)
|
||||
caldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add "$mac_base" 7)
|
||||
;;
|
||||
mikrotik,routerboard-951g-2hnd|\
|
||||
mikrotik,routerboard-951ui-2hnd)
|
||||
caldata_mikrotik_ath9k 0x1000 0x440 $(macaddr_add "$mac_base" +11)
|
||||
;;
|
||||
|
||||
@ -33,6 +33,7 @@ platform_do_upgrade() {
|
||||
mikrotik,routerboard-912uag-2hpnd|\
|
||||
mikrotik,routerboard-921gs-5hpacd-15s|\
|
||||
mikrotik,routerboard-922uags-5hpacd|\
|
||||
mikrotik,routerboard-951g-2hnd|\
|
||||
mikrotik,routerboard-951ui-2hnd|\
|
||||
mikrotik,routerboard-sxt-5nd-r2)
|
||||
platform_do_upgrade_mikrotik_nand "$1"
|
||||
|
||||
@ -57,7 +57,7 @@ bcm53xx_setup_macs()
|
||||
etXmacaddr=$(nvram get et2macaddr)
|
||||
offset=1
|
||||
;;
|
||||
luxul,xwr-3100v1 | \
|
||||
luxul,xwr-3100-v1 | \
|
||||
luxul,xwr-3150-v1)
|
||||
etXmacaddr=$(nvram get et0macaddr)
|
||||
offset=5
|
||||
|
||||
@ -39,18 +39,18 @@ platform_expected_image() {
|
||||
"dlink,dir-885l") echo "seamaseal wrgac42_dlink.2015_dir885l"; return;;
|
||||
"luxul,abr-4500-v1") echo "lxl ABR-4500"; return;;
|
||||
"luxul,xap-810-v1") echo "lxl XAP-810"; return;;
|
||||
"luxul,xap-1410v1") echo "lxl XAP-1410"; return;;
|
||||
"luxul,xap-1410-v1") echo "lxl XAP-1410"; return;;
|
||||
"luxul,xap-1440-v1") echo "lxl XAP-1440"; return;;
|
||||
"luxul,xap-1510v1") echo "lxl XAP-1510"; return;;
|
||||
"luxul,xap-1510-v1") echo "lxl XAP-1510"; return;;
|
||||
"luxul,xap-1610-v1") echo "lxl XAP-1610"; return;;
|
||||
"luxul,xbr-4500-v1") echo "lxl XBR-4500"; return;;
|
||||
"luxul,xwc-1000") echo "lxl XWC-1000"; return;;
|
||||
"luxul,xwc-2000-v1") echo "lxl XWC-2000"; return;;
|
||||
"luxul,xwr-1200v1") echo "lxl XWR-1200"; return;;
|
||||
"luxul,xwr-3100v1") echo "lxl XWR-3100"; return;;
|
||||
"luxul,xwr-1200-v1") echo "lxl XWR-1200"; return;;
|
||||
"luxul,xwr-3100-v1") echo "lxl XWR-3100"; return;;
|
||||
"luxul,xwr-3150-v1") echo "lxl XWR-3150"; return;;
|
||||
"netgear,r6250v1") echo "chk U12H245T00_NETGEAR"; return;;
|
||||
"netgear,r6300v2") echo "chk U12H240T00_NETGEAR"; return;;
|
||||
"netgear,r6250-v1") echo "chk U12H245T00_NETGEAR"; return;;
|
||||
"netgear,r6300-v2") echo "chk U12H240T00_NETGEAR"; return;;
|
||||
"netgear,r7000") echo "chk U12H270T00_NETGEAR"; return;;
|
||||
"netgear,r7900") echo "chk U12H315T30_NETGEAR"; return;;
|
||||
"netgear,r8000") echo "chk U12H315T00_NETGEAR"; return;;
|
||||
|
||||
@ -21,7 +21,7 @@ Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
|
||||
@@ -131,6 +131,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
|
||||
bcm47094-netgear-r8500.dtb \
|
||||
bcm47094-phicomm-k3.dtb \
|
||||
bcm53015-meraki-mr26.dtb \
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,487 @@
|
||||
From 915fac07f053418d0ab9075af64da2872ca8a7f8 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Wed, 3 May 2023 14:16:10 +0200
|
||||
Subject: [PATCH] =?UTF-8?q?ARM:=20dts:=20BCM5301X:=20Relicense=20Rafa?=
|
||||
=?UTF-8?q?=C5=82's=20code=20to=20the=20GPL=202.0+=20/=20MIT?=
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
All BCM5301X device DTS files use dual licensing. Try the same for SoC.
|
||||
Introduce a new .dtsi file with a proper SPDX tag.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Link: https://lore.kernel.org/r/20230503121611.1629-1-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
MAINTAINERS | 1 +
|
||||
arch/arm/boot/dts/bcm-ns.dtsi | 202 ++++++++++++++++++++++++++++++++
|
||||
arch/arm/boot/dts/bcm5301x.dtsi | 192 +-----------------------------
|
||||
3 files changed, 205 insertions(+), 190 deletions(-)
|
||||
create mode 100644 arch/arm/boot/dts/bcm-ns.dtsi
|
||||
|
||||
--- a/MAINTAINERS
|
||||
+++ b/MAINTAINERS
|
||||
@@ -3579,6 +3579,7 @@ M: Rafał Miłecki <zajec5@gmail.com>
|
||||
M: bcm-kernel-feedback-list@broadcom.com
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
+F: arch/arm/boot/dts/bcm-ns.dtsi
|
||||
F: arch/arm/boot/dts/bcm470*
|
||||
F: arch/arm/boot/dts/bcm5301*
|
||||
F: arch/arm/boot/dts/bcm953012*
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
@@ -0,0 +1,202 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+
|
||||
+#include <dt-bindings/clock/bcm-nsp.h>
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/interrupt-controller/irq.h>
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+
|
||||
+/ {
|
||||
+ axi@18000000 {
|
||||
+ compatible = "brcm,bus-axi";
|
||||
+ reg = <0x18000000 0x1000>;
|
||||
+ ranges = <0x00000000 0x18000000 0x00100000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ chipcommon: chipcommon@0 {
|
||||
+ reg = <0x00000000 0x1000>;
|
||||
+
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ };
|
||||
+
|
||||
+ pcie0: pcie@12000 {
|
||||
+ reg = <0x00012000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ pcie1: pcie@13000 {
|
||||
+ reg = <0x00013000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ usb2: usb2@21000 {
|
||||
+ reg = <0x00021000 0x1000>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ ehci: usb@21000 {
|
||||
+ #usb-cells = <0>;
|
||||
+
|
||||
+ compatible = "generic-ehci";
|
||||
+ reg = <0x00021000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&usb2_phy>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ ehci_port1: port@1 {
|
||||
+ reg = <1>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ehci_port2: port@2 {
|
||||
+ reg = <2>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ ohci: usb@22000 {
|
||||
+ #usb-cells = <0>;
|
||||
+
|
||||
+ compatible = "generic-ohci";
|
||||
+ reg = <0x00022000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ ohci_port1: port@1 {
|
||||
+ reg = <1>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ ohci_port2: port@2 {
|
||||
+ reg = <2>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb3: usb3@23000 {
|
||||
+ reg = <0x00023000 0x1000>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+
|
||||
+ interrupt-parent = <&gic>;
|
||||
+
|
||||
+ xhci: usb@23000 {
|
||||
+ #usb-cells = <0>;
|
||||
+
|
||||
+ compatible = "generic-xhci";
|
||||
+ reg = <0x00023000 0x1000>;
|
||||
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ phys = <&usb3_phy>;
|
||||
+ phy-names = "usb";
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ xhci_port1: port@1 {
|
||||
+ reg = <1>;
|
||||
+ #trigger-source-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ mdio: mdio@18003000 {
|
||||
+ compatible = "brcm,iproc-mdio";
|
||||
+ reg = <0x18003000 0x8>;
|
||||
+ #size-cells = <0>;
|
||||
+ #address-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ dmu-bus@1800c000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ ranges = <0 0x1800c000 0x1000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ cru-bus@100 {
|
||||
+ compatible = "brcm,ns-cru", "simple-mfd";
|
||||
+ reg = <0x100 0x1a4>;
|
||||
+ ranges;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ usb2_phy: phy@164 {
|
||||
+ compatible = "brcm,ns-usb2-phy";
|
||||
+ reg = <0x164 0x4>;
|
||||
+ brcm,syscon-clkset = <&cru_clkset>;
|
||||
+ clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
|
||||
+ clock-names = "phy-ref-clk";
|
||||
+ #phy-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ cru_clkset: syscon@180 {
|
||||
+ compatible = "brcm,cru-clkset", "syscon";
|
||||
+ reg = <0x180 0x4>;
|
||||
+ };
|
||||
+
|
||||
+ pinctrl: pinctrl@1c0 {
|
||||
+ compatible = "brcm,bcm4708-pinmux";
|
||||
+ reg = <0x1c0 0x24>;
|
||||
+ reg-names = "cru_gpio_control";
|
||||
+
|
||||
+ spi-pins {
|
||||
+ groups = "spi_grp";
|
||||
+ function = "spi";
|
||||
+ };
|
||||
+
|
||||
+ pinmux_i2c: i2c-pins {
|
||||
+ groups = "i2c_grp";
|
||||
+ function = "i2c";
|
||||
+ };
|
||||
+
|
||||
+ pinmux_pwm: pwm-pins {
|
||||
+ groups = "pwm0_grp", "pwm1_grp",
|
||||
+ "pwm2_grp", "pwm3_grp";
|
||||
+ function = "pwm";
|
||||
+ };
|
||||
+
|
||||
+ pinmux_uart1: uart1-pins {
|
||||
+ groups = "uart1_grp";
|
||||
+ function = "uart1";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ thermal: thermal@2c0 {
|
||||
+ compatible = "brcm,ns-thermal";
|
||||
+ reg = <0x2c0 0x10>;
|
||||
+ #thermal-sensor-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ thermal-zones {
|
||||
+ cpu_thermal: cpu-thermal {
|
||||
+ polling-delay-passive = <0>;
|
||||
+ polling-delay = <1000>;
|
||||
+ coefficients = <(-556) 418000>;
|
||||
+ thermal-sensors = <&thermal>;
|
||||
+
|
||||
+ trips {
|
||||
+ cpu-crit {
|
||||
+ temperature = <125000>;
|
||||
+ hysteresis = <0>;
|
||||
+ type = "critical";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cooling-maps {
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--- a/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
@@ -8,11 +8,7 @@
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
-#include <dt-bindings/clock/bcm-nsp.h>
|
||||
-#include <dt-bindings/gpio/gpio.h>
|
||||
-#include <dt-bindings/input/input.h>
|
||||
-#include <dt-bindings/interrupt-controller/irq.h>
|
||||
-#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+#include "bcm-ns.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
@@ -149,12 +145,6 @@
|
||||
};
|
||||
|
||||
axi@18000000 {
|
||||
- compatible = "brcm,bus-axi";
|
||||
- reg = <0x18000000 0x1000>;
|
||||
- ranges = <0x00000000 0x18000000 0x00100000>;
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
-
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0x000fffff 0xffff>;
|
||||
interrupt-map =
|
||||
@@ -228,108 +218,15 @@
|
||||
<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
- chipcommon: chipcommon@0 {
|
||||
- reg = <0x00000000 0x1000>;
|
||||
-
|
||||
- gpio-controller;
|
||||
- #gpio-cells = <2>;
|
||||
+ chipcommon@0 {
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
- pcie0: pcie@12000 {
|
||||
- reg = <0x00012000 0x1000>;
|
||||
- };
|
||||
-
|
||||
- pcie1: pcie@13000 {
|
||||
- reg = <0x00013000 0x1000>;
|
||||
- };
|
||||
-
|
||||
pcie2: pcie@14000 {
|
||||
reg = <0x00014000 0x1000>;
|
||||
};
|
||||
|
||||
- usb2: usb2@21000 {
|
||||
- reg = <0x00021000 0x1000>;
|
||||
-
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
- ranges;
|
||||
-
|
||||
- interrupt-parent = <&gic>;
|
||||
-
|
||||
- ehci: usb@21000 {
|
||||
- #usb-cells = <0>;
|
||||
-
|
||||
- compatible = "generic-ehci";
|
||||
- reg = <0x00021000 0x1000>;
|
||||
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- phys = <&usb2_phy>;
|
||||
-
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
-
|
||||
- ehci_port1: port@1 {
|
||||
- reg = <1>;
|
||||
- #trigger-source-cells = <0>;
|
||||
- };
|
||||
-
|
||||
- ehci_port2: port@2 {
|
||||
- reg = <2>;
|
||||
- #trigger-source-cells = <0>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- ohci: usb@22000 {
|
||||
- #usb-cells = <0>;
|
||||
-
|
||||
- compatible = "generic-ohci";
|
||||
- reg = <0x00022000 0x1000>;
|
||||
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
-
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
-
|
||||
- ohci_port1: port@1 {
|
||||
- reg = <1>;
|
||||
- #trigger-source-cells = <0>;
|
||||
- };
|
||||
-
|
||||
- ohci_port2: port@2 {
|
||||
- reg = <2>;
|
||||
- #trigger-source-cells = <0>;
|
||||
- };
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- usb3: usb3@23000 {
|
||||
- reg = <0x00023000 0x1000>;
|
||||
-
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
- ranges;
|
||||
-
|
||||
- interrupt-parent = <&gic>;
|
||||
-
|
||||
- xhci: usb@23000 {
|
||||
- #usb-cells = <0>;
|
||||
-
|
||||
- compatible = "generic-xhci";
|
||||
- reg = <0x00023000 0x1000>;
|
||||
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- phys = <&usb3_phy>;
|
||||
- phy-names = "usb";
|
||||
-
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
-
|
||||
- xhci_port1: port@1 {
|
||||
- reg = <1>;
|
||||
- #trigger-source-cells = <0>;
|
||||
- };
|
||||
- };
|
||||
- };
|
||||
-
|
||||
gmac0: ethernet@24000 {
|
||||
reg = <0x24000 0x800>;
|
||||
};
|
||||
@@ -355,13 +252,6 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
- mdio: mdio@18003000 {
|
||||
- compatible = "brcm,iproc-mdio";
|
||||
- reg = <0x18003000 0x8>;
|
||||
- #size-cells = <0>;
|
||||
- #address-cells = <1>;
|
||||
- };
|
||||
-
|
||||
mdio-mux@18003000 {
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio>;
|
||||
@@ -409,18 +299,7 @@
|
||||
};
|
||||
|
||||
dmu-bus@1800c000 {
|
||||
- compatible = "simple-bus";
|
||||
- ranges = <0 0x1800c000 0x1000>;
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
-
|
||||
cru-bus@100 {
|
||||
- compatible = "brcm,ns-cru", "simple-mfd";
|
||||
- reg = <0x100 0x1a4>;
|
||||
- ranges;
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
-
|
||||
lcpll0: clock-controller@100 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "brcm,nsp-lcpll0";
|
||||
@@ -440,53 +319,6 @@
|
||||
"usbclk", "iprocfast",
|
||||
"sata1", "sata2";
|
||||
};
|
||||
-
|
||||
- usb2_phy: phy@164 {
|
||||
- compatible = "brcm,ns-usb2-phy";
|
||||
- reg = <0x164 0x4>;
|
||||
- brcm,syscon-clkset = <&cru_clkset>;
|
||||
- clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
|
||||
- clock-names = "phy-ref-clk";
|
||||
- #phy-cells = <0>;
|
||||
- };
|
||||
-
|
||||
- cru_clkset: syscon@180 {
|
||||
- compatible = "brcm,cru-clkset", "syscon";
|
||||
- reg = <0x180 0x4>;
|
||||
- };
|
||||
-
|
||||
- pinctrl: pinctrl@1c0 {
|
||||
- compatible = "brcm,bcm4708-pinmux";
|
||||
- reg = <0x1c0 0x24>;
|
||||
- reg-names = "cru_gpio_control";
|
||||
-
|
||||
- spi-pins {
|
||||
- groups = "spi_grp";
|
||||
- function = "spi";
|
||||
- };
|
||||
-
|
||||
- pinmux_i2c: i2c-pins {
|
||||
- groups = "i2c_grp";
|
||||
- function = "i2c";
|
||||
- };
|
||||
-
|
||||
- pinmux_pwm: pwm-pins {
|
||||
- groups = "pwm0_grp", "pwm1_grp",
|
||||
- "pwm2_grp", "pwm3_grp";
|
||||
- function = "pwm";
|
||||
- };
|
||||
-
|
||||
- pinmux_uart1: uart1-pins {
|
||||
- groups = "uart1_grp";
|
||||
- function = "uart1";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- thermal: thermal@2c0 {
|
||||
- compatible = "brcm,ns-thermal";
|
||||
- reg = <0x2c0 0x10>;
|
||||
- #thermal-sensor-cells = <0>;
|
||||
- };
|
||||
};
|
||||
};
|
||||
|
||||
@@ -558,24 +390,4 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
-
|
||||
- thermal-zones {
|
||||
- cpu_thermal: cpu-thermal {
|
||||
- polling-delay-passive = <0>;
|
||||
- polling-delay = <1000>;
|
||||
- coefficients = <(-556) 418000>;
|
||||
- thermal-sensors = <&thermal>;
|
||||
-
|
||||
- trips {
|
||||
- cpu-crit {
|
||||
- temperature = <125000>;
|
||||
- hysteresis = <0>;
|
||||
- type = "critical";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- cooling-maps {
|
||||
- };
|
||||
- };
|
||||
- };
|
||||
};
|
||||
@ -0,0 +1,136 @@
|
||||
From 916553449561c4f0b61c71b751b7bb583f5dddd4 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Wed, 3 May 2023 14:16:11 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Relicense Florian's code to the GPL 2.0+
|
||||
/ MIT
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
All BCM5301X device DTS files use dual licensing. Try the same for SoC.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Link: https://lore.kernel.org/r/20230503121611.1629-2-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm-ns.dtsi | 36 ++++++++++++++++++++++++++++++
|
||||
arch/arm/boot/dts/bcm5301x.dtsi | 39 ---------------------------------
|
||||
2 files changed, 36 insertions(+), 39 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
@@ -19,6 +19,8 @@
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcie0: pcie@12000 {
|
||||
@@ -109,6 +111,22 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
+
|
||||
+ gmac0: ethernet@24000 {
|
||||
+ reg = <0x24000 0x800>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1: ethernet@25000 {
|
||||
+ reg = <0x25000 0x800>;
|
||||
+ };
|
||||
+
|
||||
+ gmac2: ethernet@26000 {
|
||||
+ reg = <0x26000 0x800>;
|
||||
+ };
|
||||
+
|
||||
+ gmac3: ethernet@27000 {
|
||||
+ reg = <0x27000 0x800>;
|
||||
+ };
|
||||
};
|
||||
|
||||
mdio: mdio@18003000 {
|
||||
@@ -118,6 +136,24 @@
|
||||
#address-cells = <1>;
|
||||
};
|
||||
|
||||
+ rng: rng@18004000 {
|
||||
+ compatible = "brcm,bcm5301x-rng";
|
||||
+ reg = <0x18004000 0x14>;
|
||||
+ };
|
||||
+
|
||||
+ srab: ethernet-switch@18007000 {
|
||||
+ compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
|
||||
+ reg = <0x18007000 0x1000>;
|
||||
+
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ /* ports are defined in board DTS */
|
||||
+ ports {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
dmu-bus@1800c000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x1800c000 0x1000>;
|
||||
--- a/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
@@ -218,30 +218,9 @@
|
||||
<0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
- chipcommon@0 {
|
||||
- interrupt-controller;
|
||||
- #interrupt-cells = <2>;
|
||||
- };
|
||||
-
|
||||
pcie2: pcie@14000 {
|
||||
reg = <0x00014000 0x1000>;
|
||||
};
|
||||
-
|
||||
- gmac0: ethernet@24000 {
|
||||
- reg = <0x24000 0x800>;
|
||||
- };
|
||||
-
|
||||
- gmac1: ethernet@25000 {
|
||||
- reg = <0x25000 0x800>;
|
||||
- };
|
||||
-
|
||||
- gmac2: ethernet@26000 {
|
||||
- reg = <0x26000 0x800>;
|
||||
- };
|
||||
-
|
||||
- gmac3: ethernet@27000 {
|
||||
- reg = <0x27000 0x800>;
|
||||
- };
|
||||
};
|
||||
|
||||
pwm: pwm@18002000 {
|
||||
@@ -322,24 +301,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
- srab: ethernet-switch@18007000 {
|
||||
- compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
|
||||
- reg = <0x18007000 0x1000>;
|
||||
-
|
||||
- status = "disabled";
|
||||
-
|
||||
- /* ports are defined in board DTS */
|
||||
- ports {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- rng: rng@18004000 {
|
||||
- compatible = "brcm,bcm5301x-rng";
|
||||
- reg = <0x18004000 0x14>;
|
||||
- };
|
||||
-
|
||||
nand_controller: nand-controller@18028000 {
|
||||
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
|
||||
reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
|
||||
@ -0,0 +1,32 @@
|
||||
From d3c8e2c5757153bbfad70019ec1decbca86f3def Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Wed, 3 May 2023 14:28:30 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Drop "clock-names" from the SPI node
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
There is no such property in the SPI controller binding documentation.
|
||||
Also Linux driver doesn't look for it.
|
||||
|
||||
This fixes:
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: spi@18029200: Unevaluated properties are not allowed ('clock-names' was unexpected)
|
||||
From schema: Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Link: https://lore.kernel.org/r/20230503122830.3200-1-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm5301x.dtsi | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
@@ -335,7 +335,6 @@
|
||||
"spi_lr_session_done",
|
||||
"spi_lr_overread";
|
||||
clocks = <&iprocmed>;
|
||||
- clock-names = "iprocmed";
|
||||
num-cs = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -0,0 +1,249 @@
|
||||
From b3b3cd885ed39cb4b38319a1c4fa4e41db6fee72 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Mon, 15 May 2023 17:19:20 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ /
|
||||
MIT
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing.
|
||||
That syncs more Northstar code to be based on the same licensing schema.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Cc: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Link: https://lore.kernel.org/r/20230515151921.25021-1-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm-ns.dtsi | 90 +++++++++++++++++++++++++++++++++
|
||||
arch/arm/boot/dts/bcm5301x.dtsi | 85 -------------------------------
|
||||
2 files changed, 90 insertions(+), 85 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
@@ -1,4 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
+ */
|
||||
|
||||
#include <dt-bindings/clock/bcm-nsp.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
@@ -7,6 +10,81 @@
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
+ interrupt-parent = <&gic>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ chipcommon-a-bus@18000000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ ranges = <0x00000000 0x18000000 0x00001000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ uart0: serial@300 {
|
||||
+ compatible = "ns16550";
|
||||
+ reg = <0x0300 0x100>;
|
||||
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&iprocslow>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ uart1: serial@400 {
|
||||
+ compatible = "ns16550";
|
||||
+ reg = <0x0400 0x100>;
|
||||
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&iprocslow>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pinmux_uart1>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ mpcore-bus@19000000 {
|
||||
+ compatible = "simple-bus";
|
||||
+ ranges = <0x00000000 0x19000000 0x00023000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ scu@20000 {
|
||||
+ compatible = "arm,cortex-a9-scu";
|
||||
+ reg = <0x20000 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ timer@20200 {
|
||||
+ compatible = "arm,cortex-a9-global-timer";
|
||||
+ reg = <0x20200 0x100>;
|
||||
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ };
|
||||
+
|
||||
+ timer@20600 {
|
||||
+ compatible = "arm,cortex-a9-twd-timer";
|
||||
+ reg = <0x20600 0x20>;
|
||||
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
+ IRQ_TYPE_EDGE_RISING)>;
|
||||
+ clocks = <&periph_clk>;
|
||||
+ };
|
||||
+
|
||||
+ gic: interrupt-controller@21000 {
|
||||
+ compatible = "arm,cortex-a9-gic";
|
||||
+ #interrupt-cells = <3>;
|
||||
+ #address-cells = <0>;
|
||||
+ interrupt-controller;
|
||||
+ reg = <0x21000 0x1000>,
|
||||
+ <0x20100 0x100>;
|
||||
+ };
|
||||
+
|
||||
+ L2: cache-controller@22000 {
|
||||
+ compatible = "arm,pl310-cache";
|
||||
+ reg = <0x22000 0x1000>;
|
||||
+ cache-unified;
|
||||
+ arm,shared-override;
|
||||
+ prefetch-data = <1>;
|
||||
+ prefetch-instr = <1>;
|
||||
+ cache-level = <2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
axi@18000000 {
|
||||
compatible = "brcm,bus-axi";
|
||||
reg = <0x18000000 0x1000>;
|
||||
@@ -216,6 +294,18 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ nand_controller: nand-controller@18028000 {
|
||||
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
|
||||
+ reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
|
||||
+ reg-names = "nand", "iproc-idm", "iproc-ext";
|
||||
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ brcm,nand-has-wp;
|
||||
+ };
|
||||
+
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <0>;
|
||||
--- a/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
@@ -11,41 +11,7 @@
|
||||
#include "bcm-ns.dtsi"
|
||||
|
||||
/ {
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
- interrupt-parent = <&gic>;
|
||||
-
|
||||
- chipcommon-a-bus@18000000 {
|
||||
- compatible = "simple-bus";
|
||||
- ranges = <0x00000000 0x18000000 0x00001000>;
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
-
|
||||
- uart0: serial@300 {
|
||||
- compatible = "ns16550";
|
||||
- reg = <0x0300 0x100>;
|
||||
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&iprocslow>;
|
||||
- status = "disabled";
|
||||
- };
|
||||
-
|
||||
- uart1: serial@400 {
|
||||
- compatible = "ns16550";
|
||||
- reg = <0x0400 0x100>;
|
||||
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- clocks = <&iprocslow>;
|
||||
- pinctrl-names = "default";
|
||||
- pinctrl-0 = <&pinmux_uart1>;
|
||||
- status = "disabled";
|
||||
- };
|
||||
- };
|
||||
-
|
||||
mpcore-bus@19000000 {
|
||||
- compatible = "simple-bus";
|
||||
- ranges = <0x00000000 0x19000000 0x00023000>;
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <1>;
|
||||
-
|
||||
a9pll: arm_clk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "brcm,nsp-armpll";
|
||||
@@ -53,26 +19,6 @@
|
||||
reg = <0x00000 0x1000>;
|
||||
};
|
||||
|
||||
- scu@20000 {
|
||||
- compatible = "arm,cortex-a9-scu";
|
||||
- reg = <0x20000 0x100>;
|
||||
- };
|
||||
-
|
||||
- timer@20200 {
|
||||
- compatible = "arm,cortex-a9-global-timer";
|
||||
- reg = <0x20200 0x100>;
|
||||
- interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
|
||||
- clocks = <&periph_clk>;
|
||||
- };
|
||||
-
|
||||
- timer@20600 {
|
||||
- compatible = "arm,cortex-a9-twd-timer";
|
||||
- reg = <0x20600 0x20>;
|
||||
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
- IRQ_TYPE_EDGE_RISING)>;
|
||||
- clocks = <&periph_clk>;
|
||||
- };
|
||||
-
|
||||
watchdog@20620 {
|
||||
compatible = "arm,cortex-a9-twd-wdt";
|
||||
reg = <0x20620 0x20>;
|
||||
@@ -80,25 +26,6 @@
|
||||
IRQ_TYPE_EDGE_RISING)>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
-
|
||||
- gic: interrupt-controller@21000 {
|
||||
- compatible = "arm,cortex-a9-gic";
|
||||
- #interrupt-cells = <3>;
|
||||
- #address-cells = <0>;
|
||||
- interrupt-controller;
|
||||
- reg = <0x21000 0x1000>,
|
||||
- <0x20100 0x100>;
|
||||
- };
|
||||
-
|
||||
- L2: cache-controller@22000 {
|
||||
- compatible = "arm,pl310-cache";
|
||||
- reg = <0x22000 0x1000>;
|
||||
- cache-unified;
|
||||
- arm,shared-override;
|
||||
- prefetch-data = <1>;
|
||||
- prefetch-instr = <1>;
|
||||
- cache-level = <2>;
|
||||
- };
|
||||
};
|
||||
|
||||
pmu {
|
||||
@@ -301,18 +228,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
- nand_controller: nand-controller@18028000 {
|
||||
- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
|
||||
- reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
|
||||
- reg-names = "nand", "iproc-idm", "iproc-ext";
|
||||
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
-
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
-
|
||||
- brcm,nand-has-wp;
|
||||
- };
|
||||
-
|
||||
spi@18029200 {
|
||||
compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
|
||||
reg = <0x18029200 0x184>,
|
||||
@ -0,0 +1,203 @@
|
||||
From 3b3e35b279bee5e51580c648399e20323467f58c Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Mon, 15 May 2023 17:19:21 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Relicense AXI interrupts code to the GPL
|
||||
2.0+ / MIT
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Those entries were added by:
|
||||
1. Hauke in commits dec378827c4a ("ARM: BCM5301X: Add IRQs to Broadcom's
|
||||
bus-axi in DTS file") and 1f80de6863ca ("ARM: BCM5301X: add IRQ
|
||||
numbers for PCIe controller")
|
||||
2. Florian in the commit 2cd0c0202f13 ("ARM: dts: BCM5301X: Add SRAB
|
||||
interrupts")
|
||||
|
||||
Move them to the bcm-ns.dtsi which uses dual licensing. That syncs more
|
||||
Northstar code to be based on the same licensing schema.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Cc: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Cc: Florian Fainelli <f.fainelli@gmail.com>
|
||||
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
|
||||
Link: https://lore.kernel.org/r/20230515151921.25021-2-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm-ns.dtsi | 73 ++++++++++++++++++++++++++++++++
|
||||
arch/arm/boot/dts/bcm5301x.dtsi | 75 ---------------------------------
|
||||
2 files changed, 73 insertions(+), 75 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
@@ -92,6 +92,79 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
+ #interrupt-cells = <1>;
|
||||
+ interrupt-map-mask = <0x000fffff 0xffff>;
|
||||
+ interrupt-map =
|
||||
+ /* ChipCommon */
|
||||
+ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Switch Register Access Block */
|
||||
+ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* PCIe Controller 0 */
|
||||
+ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* PCIe Controller 1 */
|
||||
+ <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* PCIe Controller 2 */
|
||||
+ <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* USB 2.0 Controller */
|
||||
+ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* USB 3.0 Controller */
|
||||
+ <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Ethernet Controller 0 */
|
||||
+ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Ethernet Controller 1 */
|
||||
+ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Ethernet Controller 2 */
|
||||
+ <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* Ethernet Controller 3 */
|
||||
+ <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+
|
||||
+ /* NAND Controller */
|
||||
+ <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+
|
||||
chipcommon: chipcommon@0 {
|
||||
reg = <0x00000000 0x1000>;
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
@@ -3,8 +3,6 @@
|
||||
* Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
|
||||
* BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
|
||||
*
|
||||
- * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
- *
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
@@ -72,79 +70,6 @@
|
||||
};
|
||||
|
||||
axi@18000000 {
|
||||
- #interrupt-cells = <1>;
|
||||
- interrupt-map-mask = <0x000fffff 0xffff>;
|
||||
- interrupt-map =
|
||||
- /* ChipCommon */
|
||||
- <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* Switch Register Access Block */
|
||||
- <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* PCIe Controller 0 */
|
||||
- <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* PCIe Controller 1 */
|
||||
- <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* PCIe Controller 2 */
|
||||
- <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* USB 2.0 Controller */
|
||||
- <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* USB 3.0 Controller */
|
||||
- <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* Ethernet Controller 0 */
|
||||
- <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* Ethernet Controller 1 */
|
||||
- <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* Ethernet Controller 2 */
|
||||
- <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* Ethernet Controller 3 */
|
||||
- <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
|
||||
-
|
||||
- /* NAND Controller */
|
||||
- <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
- <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
-
|
||||
pcie2: pcie@14000 {
|
||||
reg = <0x00014000 0x1000>;
|
||||
};
|
||||
@ -0,0 +1,336 @@
|
||||
From dfa6570eb5ce2f24059caadbe2ed70034b5337bc Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Mon, 15 May 2023 10:33:08 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Specify MAC addresses on Luxul devices
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Use NRAM (NVMEM device) and its "et0macaddr" variable (NVMEM cell) to
|
||||
point Ethernet devices to their MAC addresses.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Link: https://lore.kernel.org/r/20230515083308.7612-1-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 13 +++++++++++++
|
||||
arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 13 +++++++++++++
|
||||
arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 13 +++++++++++++
|
||||
arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 11 +++++++++++
|
||||
arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 11 +++++++++++
|
||||
arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 13 +++++++++++++
|
||||
arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 11 +++++++++++
|
||||
arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 13 +++++++++++++
|
||||
arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 11 +++++++++++
|
||||
arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 5 ++++-
|
||||
10 files changed, 113 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
|
||||
@@ -20,6 +20,14 @@
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
+ nvram@1eff0000 {
|
||||
+ compatible = "brcm,nvram";
|
||||
+ reg = <0x1eff0000 0x10000>;
|
||||
+
|
||||
+ et0macaddr: et0macaddr {
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
@@ -53,6 +61,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&gmac0 {
|
||||
+ nvmem-cells = <&et0macaddr>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
|
||||
@@ -24,6 +24,14 @@
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
+ nvram@1eff0000 {
|
||||
+ compatible = "brcm,nvram";
|
||||
+ reg = <0x1eff0000 0x10000>;
|
||||
+
|
||||
+ et0macaddr: et0macaddr {
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
nand_controller: nand-controller@18028000 {
|
||||
nand@0 {
|
||||
partitions {
|
||||
@@ -60,6 +68,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&gmac0 {
|
||||
+ nvmem-cells = <&et0macaddr>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
|
||||
@@ -20,6 +20,14 @@
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
+ nvram@1eff0000 {
|
||||
+ compatible = "brcm,nvram";
|
||||
+ reg = <0x1eff0000 0x10000>;
|
||||
+
|
||||
+ et0macaddr: et0macaddr {
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
@@ -53,6 +61,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&gmac0 {
|
||||
+ nvmem-cells = <&et0macaddr>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
|
||||
@@ -24,6 +24,10 @@
|
||||
nvram@1eff0000 {
|
||||
compatible = "brcm,nvram";
|
||||
reg = <0x1eff0000 0x10000>;
|
||||
+
|
||||
+ et0macaddr: et0macaddr {
|
||||
+ #nvmem-cell-cells = <1>;
|
||||
+ };
|
||||
};
|
||||
|
||||
leds {
|
||||
@@ -106,6 +110,11 @@
|
||||
vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
+&gmac0 {
|
||||
+ nvmem-cells = <&et0macaddr 0>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -137,6 +146,8 @@
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "wan";
|
||||
+ nvmem-cells = <&et0macaddr 5>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
|
||||
@@ -25,6 +25,10 @@
|
||||
nvram@1eff0000 {
|
||||
compatible = "brcm,nvram";
|
||||
reg = <0x1eff0000 0x10000>;
|
||||
+
|
||||
+ et0macaddr: et0macaddr {
|
||||
+ #nvmem-cell-cells = <1>;
|
||||
+ };
|
||||
};
|
||||
|
||||
leds {
|
||||
@@ -61,6 +65,11 @@
|
||||
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
+&gmac0 {
|
||||
+ nvmem-cells = <&et0macaddr 0>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -76,6 +85,8 @@
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "wan";
|
||||
+ nvmem-cells = <&et0macaddr 1>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
|
||||
@@ -20,6 +20,14 @@
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
+ nvram@1eff0000 {
|
||||
+ compatible = "brcm,nvram";
|
||||
+ reg = <0x1eff0000 0x10000>;
|
||||
+
|
||||
+ et0macaddr: et0macaddr {
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
@@ -51,6 +59,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&gmac0 {
|
||||
+ nvmem-cells = <&et0macaddr>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
|
||||
@@ -25,6 +25,10 @@
|
||||
nvram@1eff0000 {
|
||||
compatible = "brcm,nvram";
|
||||
reg = <0x1eff0000 0x10000>;
|
||||
+
|
||||
+ et0macaddr: et0macaddr {
|
||||
+ #nvmem-cell-cells = <1>;
|
||||
+ };
|
||||
};
|
||||
|
||||
leds {
|
||||
@@ -61,6 +65,11 @@
|
||||
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
+&gmac0 {
|
||||
+ nvmem-cells = <&et0macaddr 0>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -76,6 +85,8 @@
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "wan";
|
||||
+ nvmem-cells = <&et0macaddr 1>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
|
||||
@@ -22,6 +22,14 @@
|
||||
<0x88000000 0x18000000>;
|
||||
};
|
||||
|
||||
+ nvram@1eff0000 {
|
||||
+ compatible = "brcm,nvram";
|
||||
+ reg = <0x1eff0000 0x10000>;
|
||||
+
|
||||
+ et0macaddr: et0macaddr {
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
@@ -47,6 +55,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&gmac0 {
|
||||
+ nvmem-cells = <&et0macaddr>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
|
||||
@@ -25,6 +25,10 @@
|
||||
nvram@1eff0000 {
|
||||
compatible = "brcm,nvram";
|
||||
reg = <0x1eff0000 0x10000>;
|
||||
+
|
||||
+ et0macaddr: et0macaddr {
|
||||
+ #nvmem-cell-cells = <1>;
|
||||
+ };
|
||||
};
|
||||
|
||||
leds {
|
||||
@@ -101,6 +105,11 @@
|
||||
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
+&gmac0 {
|
||||
+ nvmem-cells = <&et0macaddr 0>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
+};
|
||||
+
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -136,6 +145,8 @@
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "wan";
|
||||
+ nvmem-cells = <&et0macaddr 5>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
|
||||
@@ -27,6 +27,7 @@
|
||||
reg = <0x1eff0000 0x10000>;
|
||||
|
||||
et0macaddr: et0macaddr {
|
||||
+ #nvmem-cell-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -76,7 +77,7 @@
|
||||
};
|
||||
|
||||
&gmac0 {
|
||||
- nvmem-cells = <&et0macaddr>;
|
||||
+ nvmem-cells = <&et0macaddr 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
@@ -119,6 +120,8 @@
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "wan";
|
||||
+ nvmem-cells = <&et0macaddr 5>;
|
||||
+ nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
@ -0,0 +1,90 @@
|
||||
From 9d7121f1d2faa0b50bf5b462adcd2dd91970c45e Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Sat, 20 May 2023 13:26:01 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Use updated device "compatible" strings
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Northstar binding was updated to use minus/hyphen char between model and
|
||||
version for all devices.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230520112601.11821-2-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 2 +-
|
||||
arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 2 +-
|
||||
arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts | 2 +-
|
||||
arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 2 +-
|
||||
arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 2 +-
|
||||
arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 2 +-
|
||||
6 files changed, 6 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
|
||||
@@ -8,7 +8,7 @@
|
||||
#include "bcm4708.dtsi"
|
||||
|
||||
/ {
|
||||
- compatible = "luxul,xap-1510v1", "brcm,bcm4708";
|
||||
+ compatible = "luxul,xap-1510-v1", "brcm,bcm4708";
|
||||
model = "Luxul XAP-1510 V1";
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
|
||||
@@ -13,7 +13,7 @@
|
||||
#include "bcm5301x-nand-cs0-bch8.dtsi"
|
||||
|
||||
/ {
|
||||
- compatible = "netgear,r6250v1", "brcm,bcm4708";
|
||||
+ compatible = "netgear,r6250-v1", "brcm,bcm4708";
|
||||
model = "Netgear R6250 V1 (BCM4708)";
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
|
||||
@@ -12,7 +12,7 @@
|
||||
#include "bcm5301x-nand-cs0-bch8.dtsi"
|
||||
|
||||
/ {
|
||||
- compatible = "netgear,r6300v2", "brcm,bcm4708";
|
||||
+ compatible = "netgear,r6300-v2", "brcm,bcm4708";
|
||||
model = "Netgear R6300 V2 (BCM4708)";
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
|
||||
@@ -8,7 +8,7 @@
|
||||
#include "bcm47081.dtsi"
|
||||
|
||||
/ {
|
||||
- compatible = "luxul,xap-1410v1", "brcm,bcm47081", "brcm,bcm4708";
|
||||
+ compatible = "luxul,xap-1410-v1", "brcm,bcm47081", "brcm,bcm4708";
|
||||
model = "Luxul XAP-1410 V1";
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
|
||||
@@ -9,7 +9,7 @@
|
||||
#include "bcm5301x-nand-cs0-bch4.dtsi"
|
||||
|
||||
/ {
|
||||
- compatible = "luxul,xwr-1200v1", "brcm,bcm47081", "brcm,bcm4708";
|
||||
+ compatible = "luxul,xwr-1200-v1", "brcm,bcm47081", "brcm,bcm4708";
|
||||
model = "Luxul XWR-1200 V1";
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
|
||||
@@ -9,7 +9,7 @@
|
||||
#include "bcm5301x-nand-cs0-bch4.dtsi"
|
||||
|
||||
/ {
|
||||
- compatible = "luxul,xwr-3100v1", "brcm,bcm47094", "brcm,bcm4708";
|
||||
+ compatible = "luxul,xwr-3100-v1", "brcm,bcm47094", "brcm,bcm4708";
|
||||
model = "Luxul XWR-3100 V1";
|
||||
|
||||
chosen {
|
||||
@ -0,0 +1,82 @@
|
||||
From 04afb51c1dce90051487d3c7b70a1b1b246ce29a Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Fri, 2 Jun 2023 17:10:23 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Use updated "spi-gpio" binding properties
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Switch away from deprecated properties.
|
||||
|
||||
This fixes:
|
||||
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: gpio-sck: False schema does not allow [[6, 7, 0]]
|
||||
From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml
|
||||
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: gpio-mosi: False schema does not allow [[6, 4, 0]]
|
||||
From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml
|
||||
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: 'sck-gpios' is a required property
|
||||
From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml
|
||||
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dtb: spi: Unevaluated properties are not allowed ('gpio-mosi', 'gpio-sck' were unexpected)
|
||||
From schema: Documentation/devicetree/bindings/spi/spi-gpio.yaml
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Link: https://lore.kernel.org/r/20230602151023.8607-1-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi | 4 ++--
|
||||
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 4 ++--
|
||||
arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 4 ++--
|
||||
arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 4 ++--
|
||||
4 files changed, 8 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
|
||||
@@ -16,8 +16,8 @@
|
||||
spi {
|
||||
compatible = "spi-gpio";
|
||||
num-chipselects = <1>;
|
||||
- gpio-sck = <&chipcommon 7 0>;
|
||||
- gpio-mosi = <&chipcommon 4 0>;
|
||||
+ sck-gpios = <&chipcommon 7 0>;
|
||||
+ mosi-gpios = <&chipcommon 4 0>;
|
||||
cs-gpios = <&chipcommon 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
|
||||
@@ -28,8 +28,8 @@
|
||||
spi {
|
||||
compatible = "spi-gpio";
|
||||
num-chipselects = <1>;
|
||||
- gpio-sck = <&chipcommon 7 0>;
|
||||
- gpio-mosi = <&chipcommon 4 0>;
|
||||
+ sck-gpios = <&chipcommon 7 0>;
|
||||
+ mosi-gpios = <&chipcommon 4 0>;
|
||||
cs-gpios = <&chipcommon 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
|
||||
@@ -28,8 +28,8 @@
|
||||
spi {
|
||||
compatible = "spi-gpio";
|
||||
num-chipselects = <1>;
|
||||
- gpio-sck = <&chipcommon 7 0>;
|
||||
- gpio-mosi = <&chipcommon 4 0>;
|
||||
+ sck-gpios = <&chipcommon 7 0>;
|
||||
+ mosi-gpios = <&chipcommon 4 0>;
|
||||
cs-gpios = <&chipcommon 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
|
||||
@@ -28,8 +28,8 @@
|
||||
spi {
|
||||
compatible = "spi-gpio";
|
||||
num-chipselects = <1>;
|
||||
- gpio-sck = <&chipcommon 7 0>;
|
||||
- gpio-mosi = <&chipcommon 4 0>;
|
||||
+ sck-gpios = <&chipcommon 7 0>;
|
||||
+ mosi-gpios = <&chipcommon 4 0>;
|
||||
cs-gpios = <&chipcommon 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
@ -0,0 +1,54 @@
|
||||
From c3acdd4901192bc69dc577012663d5abae21661e Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Fri, 2 Jun 2023 15:34:54 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Drop invalid #usb-cells
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Such property simply doesn't exist (is not documented or used anywhere).
|
||||
|
||||
This fixes:
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: usb@21000: Unevaluated properties are not allowed ('#usb-cells' was unexpected)
|
||||
From schema: Documentation/devicetree/bindings/usb/generic-ehci.yaml
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: usb@22000: Unevaluated properties are not allowed ('#usb-cells' was unexpected)
|
||||
From schema: Documentation/devicetree/bindings/usb/generic-ohci.yaml
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: usb@23000: Unevaluated properties are not allowed ('#usb-cells' was unexpected)
|
||||
From schema: Documentation/devicetree/bindings/usb/generic-xhci.yaml
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Link: https://lore.kernel.org/r/20230602133455.7441-1-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm-ns.dtsi | 6 ------
|
||||
1 file changed, 6 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
@@ -192,8 +192,6 @@
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
ehci: usb@21000 {
|
||||
- #usb-cells = <0>;
|
||||
-
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x00021000 0x1000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@@ -214,8 +212,6 @@
|
||||
};
|
||||
|
||||
ohci: usb@22000 {
|
||||
- #usb-cells = <0>;
|
||||
-
|
||||
compatible = "generic-ohci";
|
||||
reg = <0x00022000 0x1000>;
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@@ -245,8 +241,6 @@
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
xhci: usb@23000 {
|
||||
- #usb-cells = <0>;
|
||||
-
|
||||
compatible = "generic-xhci";
|
||||
reg = <0x00023000 0x1000>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
@ -0,0 +1,31 @@
|
||||
From 676bf7d062c14191c3fc12f1e36e1f3809041483 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Fri, 2 Jun 2023 15:34:55 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Drop invalid properties from Meraki MR32
|
||||
keys
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This fixes:
|
||||
arch/arm/boot/dts/bcm53015-meraki-mr26.dtb: keys: '#address-cells', '#size-cells' do not match any of the regexes: '^(button|event|key|switch|(button|event|key|switch)-[a-z0-9-]+|[a-z0-9-]+-(button|event|key|switch))$', 'pinctrl-[0-9]+'
|
||||
From schema: Documentation/devicetree/bindings/input/gpio-keys.yaml
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Link: https://lore.kernel.org/r/20230602133455.7441-2-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 --
|
||||
1 file changed, 2 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
|
||||
+++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
|
||||
@@ -39,8 +39,6 @@
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
- #address-cells = <1>;
|
||||
- #size-cells = <0>;
|
||||
|
||||
key-restart {
|
||||
label = "Reset";
|
||||
@ -0,0 +1,106 @@
|
||||
From 1d5682ccc7d6088179b6cfd50a3e3bb6d2b0527e Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Mon, 5 Jun 2023 08:10:49 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Relicense Christian's code to the GPL
|
||||
2.0+ / MIT
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Move code added by Christian to the bcm-ns.dtsi which uses dual
|
||||
licensing. That syncs more Northstar code to be based on the same
|
||||
licensing schema.
|
||||
|
||||
Cc: Christian Lamparter <chunkeey@gmail.com>
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Acked-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230605061049.16136-1-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm-ns.dtsi | 21 +++++++++++++++++++++
|
||||
arch/arm/boot/dts/bcm5301x.dtsi | 23 -----------------------
|
||||
2 files changed, 21 insertions(+), 23 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
@@ -182,6 +182,10 @@
|
||||
reg = <0x00013000 0x1000>;
|
||||
};
|
||||
|
||||
+ pcie2: pcie@14000 {
|
||||
+ reg = <0x00014000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
usb2: usb2@21000 {
|
||||
reg = <0x00021000 0x1000>;
|
||||
|
||||
@@ -274,6 +278,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ pwm: pwm@18002000 {
|
||||
+ compatible = "brcm,iproc-pwm";
|
||||
+ reg = <0x18002000 0x28>;
|
||||
+ clocks = <&osc>;
|
||||
+ #pwm-cells = <3>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
mdio: mdio@18003000 {
|
||||
compatible = "brcm,iproc-mdio";
|
||||
reg = <0x18003000 0x8>;
|
||||
@@ -299,6 +311,15 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ uart2: serial@18008000 {
|
||||
+ compatible = "ns16550a";
|
||||
+ reg = <0x18008000 0x20>;
|
||||
+ clocks = <&iprocslow>;
|
||||
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg-shift = <2>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
dmu-bus@1800c000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0 0x1800c000 0x1000>;
|
||||
--- a/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
|
||||
@@ -69,20 +69,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
- axi@18000000 {
|
||||
- pcie2: pcie@14000 {
|
||||
- reg = <0x00014000 0x1000>;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- pwm: pwm@18002000 {
|
||||
- compatible = "brcm,iproc-pwm";
|
||||
- reg = <0x18002000 0x28>;
|
||||
- clocks = <&osc>;
|
||||
- #pwm-cells = <3>;
|
||||
- status = "disabled";
|
||||
- };
|
||||
-
|
||||
mdio-mux@18003000 {
|
||||
compatible = "mdio-mux-mmioreg", "mdio-mux";
|
||||
mdio-parent-bus = <&mdio>;
|
||||
@@ -110,15 +96,6 @@
|
||||
reg = <0x18105000 0x1000>;
|
||||
};
|
||||
|
||||
- uart2: serial@18008000 {
|
||||
- compatible = "ns16550a";
|
||||
- reg = <0x18008000 0x20>;
|
||||
- clocks = <&iprocslow>;
|
||||
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
||||
- reg-shift = <2>;
|
||||
- status = "disabled";
|
||||
- };
|
||||
-
|
||||
i2c0: i2c@18009000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x18009000 0x50>;
|
||||
@ -0,0 +1,838 @@
|
||||
From ba4aebce23b2affb810b8a60eae853674d2cded2 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Mon, 5 Jun 2023 15:21:09 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Describe switch ports in the main DTS
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
All Northstar SoCs have BCM5301x switches (BCM53011, BCM53012) with 8
|
||||
ports (0-8 without 6). By design 3 switch ports (5, 7 and 8) are
|
||||
hardwired to 3 on-SoC Ethernet interfaces. Switch port 8 requires
|
||||
forcing link state.
|
||||
|
||||
It seems that global Northstar .dtsi file is the best place to describe
|
||||
those hw details. Only device specific bits (like labels) should go to
|
||||
device .dts files.
|
||||
|
||||
This seems to fit well with a tiny exception of Asus RT-AC88U which
|
||||
somehow was designed to have switch 5 connected to an extra switch. This
|
||||
case was simply handled with a /delete-property/.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Reviewed-by: Christian Lamparter <chunkeey@gmail.com> (MR32+MR26)
|
||||
Link: https://lore.kernel.org/r/20230605132109.7933-1-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm-ns.dtsi | 41 ++++++++++++++++++-
|
||||
.../bcm4708-buffalo-wzr-1166dhp-common.dtsi | 7 ----
|
||||
arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts | 4 --
|
||||
arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts | 3 --
|
||||
arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 7 ----
|
||||
arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts | 7 ----
|
||||
.../boot/dts/bcm47081-buffalo-wzr-600dhp2.dts | 7 ----
|
||||
arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts | 3 --
|
||||
arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts | 7 ----
|
||||
arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 12 ------
|
||||
arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts | 17 +-------
|
||||
arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts | 12 ------
|
||||
arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts | 12 ------
|
||||
.../boot/dts/bcm47094-linksys-panamera.dts | 34 ++++-----------
|
||||
arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts | 7 ----
|
||||
arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts | 4 --
|
||||
arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts | 7 ----
|
||||
arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts | 3 --
|
||||
arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts | 7 ----
|
||||
.../boot/dts/bcm47094-luxul-xwr-3150-v1.dts | 7 ----
|
||||
arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 3 --
|
||||
arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 3 --
|
||||
22 files changed, 51 insertions(+), 163 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
@@ -304,10 +304,49 @@
|
||||
|
||||
status = "disabled";
|
||||
|
||||
- /* ports are defined in board DTS */
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
+
|
||||
+ port@0 {
|
||||
+ reg = <0>;
|
||||
+ };
|
||||
+
|
||||
+ port@1 {
|
||||
+ reg = <1>;
|
||||
+ };
|
||||
+
|
||||
+ port@2 {
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+
|
||||
+ port@3 {
|
||||
+ reg = <3>;
|
||||
+ };
|
||||
+
|
||||
+ port@4 {
|
||||
+ reg = <4>;
|
||||
+ };
|
||||
+
|
||||
+ port@5 {
|
||||
+ reg = <5>;
|
||||
+ ethernet = <&gmac0>;
|
||||
+ };
|
||||
+
|
||||
+ port@7 {
|
||||
+ reg = <7>;
|
||||
+ ethernet = <&gmac1>;
|
||||
+ };
|
||||
+
|
||||
+ port@8 {
|
||||
+ reg = <8>;
|
||||
+ ethernet = <&gmac2>;
|
||||
+
|
||||
+ fixed-link {
|
||||
+ speed = <1000>;
|
||||
+ full-duplex;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1166dhp-common.dtsi
|
||||
@@ -159,34 +159,27 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-luxul-xap-1510.dts
|
||||
@@ -75,19 +75,15 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "poe";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "lan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts
|
||||
@@ -82,14 +82,11 @@
|
||||
|
||||
ports {
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "lan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
|
||||
@@ -100,34 +100,27 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
|
||||
@@ -123,34 +123,27 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts
|
||||
@@ -123,34 +123,27 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47081-luxul-xap-1410.dts
|
||||
@@ -75,14 +75,11 @@
|
||||
|
||||
ports {
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "poe";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47081-luxul-xwr-1200.dts
|
||||
@@ -124,36 +124,29 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
nvmem-cells = <&et0macaddr 5>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
|
||||
@@ -191,39 +191,27 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@8 {
|
||||
- reg = <8>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac2>;
|
||||
-
|
||||
- fixed-link {
|
||||
- speed = <1000>;
|
||||
- full-duplex;
|
||||
- };
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-asus-rt-ac88u.dts
|
||||
@@ -181,32 +181,28 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
sw0_p5: port@5 {
|
||||
- reg = <5>;
|
||||
+ /delete-property/ethernet;
|
||||
+
|
||||
label = "extsw";
|
||||
phy-mode = "rgmii";
|
||||
|
||||
@@ -218,8 +214,6 @@
|
||||
};
|
||||
|
||||
port@7 {
|
||||
- reg = <7>;
|
||||
- ethernet = <&gmac1>;
|
||||
label = "cpu";
|
||||
|
||||
fixed-link {
|
||||
@@ -229,14 +223,7 @@
|
||||
};
|
||||
|
||||
port@8 {
|
||||
- reg = <8>;
|
||||
- ethernet = <&gmac2>;
|
||||
label = "cpu";
|
||||
-
|
||||
- fixed-link {
|
||||
- speed = <1000>;
|
||||
- full-duplex;
|
||||
- };
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
|
||||
@@ -124,39 +124,27 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@8 {
|
||||
- reg = <8>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac2>;
|
||||
-
|
||||
- fixed-link {
|
||||
- speed = <1000>;
|
||||
- full-duplex;
|
||||
- };
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-890l.dts
|
||||
@@ -172,40 +172,28 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@8 {
|
||||
- reg = <8>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac2>;
|
||||
phy-mode = "rgmii";
|
||||
-
|
||||
- fixed-link {
|
||||
- speed = <1000>;
|
||||
- full-duplex;
|
||||
- };
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-linksys-panamera.dts
|
||||
@@ -207,29 +207,32 @@
|
||||
dsa,member = <0 0>;
|
||||
|
||||
ports {
|
||||
+ sw0_p0: port@0 {
|
||||
+ label = "extsw";
|
||||
+
|
||||
+ fixed-link {
|
||||
+ speed = <1000>;
|
||||
+ full-duplex;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan7";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan8";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
- ethernet = <&gmac0>;
|
||||
label = "cpu";
|
||||
status = "disabled";
|
||||
|
||||
@@ -240,8 +243,6 @@
|
||||
};
|
||||
|
||||
port@7 {
|
||||
- reg = <7>;
|
||||
- ethernet = <&gmac1>;
|
||||
label = "cpu";
|
||||
status = "disabled";
|
||||
|
||||
@@ -252,24 +253,7 @@
|
||||
};
|
||||
|
||||
port@8 {
|
||||
- reg = <8>;
|
||||
- ethernet = <&gmac2>;
|
||||
label = "cpu";
|
||||
-
|
||||
- fixed-link {
|
||||
- speed = <1000>;
|
||||
- full-duplex;
|
||||
- };
|
||||
- };
|
||||
-
|
||||
- sw0_p0: port@0 {
|
||||
- reg = <0>;
|
||||
- label = "extsw";
|
||||
-
|
||||
- fixed-link {
|
||||
- speed = <1000>;
|
||||
- full-duplex;
|
||||
- };
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-abr-4500.dts
|
||||
@@ -83,36 +83,29 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "wan";
|
||||
nvmem-cells = <&et0macaddr 1>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xap-1610.dts
|
||||
@@ -73,19 +73,15 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "poe";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xbr-4500.dts
|
||||
@@ -83,36 +83,29 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "wan";
|
||||
nvmem-cells = <&et0macaddr 1>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
|
||||
@@ -69,14 +69,11 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3100.dts
|
||||
@@ -123,36 +123,29 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
nvmem-cells = <&et0macaddr 5>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
|
||||
+++ b/arch/arm/boot/dts/bcm47094-luxul-xwr-3150-v1.dts
|
||||
@@ -98,36 +98,29 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
- reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
- reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
- reg = <3>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
- reg = <4>;
|
||||
label = "wan";
|
||||
nvmem-cells = <&et0macaddr 5>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
|
||||
+++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
|
||||
@@ -115,14 +115,11 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "poe";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
|
||||
+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
|
||||
@@ -176,14 +176,11 @@
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
- reg = <0>;
|
||||
label = "poe";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
- reg = <5>;
|
||||
label = "cpu";
|
||||
- ethernet = <&gmac0>;
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
@ -0,0 +1,63 @@
|
||||
From a6a1a156f5debaebf9f61850d111b966e9be9ee9 Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Thu, 8 Jun 2023 17:36:27 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: MR26: MR32: remove bogus nand-ecc-algo
|
||||
property
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
| bcm53015-meraki-mr26.dtb: nand-controller@18028000:
|
||||
| nand@0:nand-ecc-algo:0: 'hw' is not one of ['hamming', 'bch', 'rs']
|
||||
| From schema: Documentation/[...]/nand-controller.yaml
|
||||
| bcm53016-meraki-mr32.dtb: nand-controller@18028000:
|
||||
| nand@0:nand-ecc-algo:0: 'hw' is not one of ['hamming', 'bch', 'rs']
|
||||
| From schema: Documentation/[...]/nand-controller.yaml
|
||||
|
||||
original ECC values for these old Merakis are sadly not
|
||||
provided by the vendor. It looks like Meraki just stuck
|
||||
with what Broadcom's SDK was doing... which left this
|
||||
up to the proprietary nand driver.
|
||||
|
||||
Note: The invalid setting was and is handled by brcmnand. It
|
||||
falls back to "bch" in brcmnand_setup_dev() when ecc.algo is
|
||||
set to NAND_ECC_ALGO_UNKNOWN (since "hw" is not in the list
|
||||
above).
|
||||
|
||||
A correct nand-ecc-algo = "bch"; is already specified in the
|
||||
included "bcm5301x-nand-cs0-bch8.dtsi". So this line can be
|
||||
dropped.
|
||||
|
||||
Reported-by: Rafał Miłecki <zajec5@gmail.com> (per Mail)
|
||||
Fixes: 935327a73553 ("ARM: dts: BCM5301X: Add DT for Meraki MR26")
|
||||
Fixes: ec88a9c344d9 ("ARM: BCM5301X: Add DT for Meraki MR32")
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Link: https://lore.kernel.org/r/2c4d00dd40124c2ddc0b139cbce7531b108f9052.1686238550.git.chunkeey@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 --
|
||||
arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 --
|
||||
2 files changed, 4 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
|
||||
+++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
|
||||
@@ -72,8 +72,6 @@
|
||||
};
|
||||
|
||||
&nandcs {
|
||||
- nand-ecc-algo = "hw";
|
||||
-
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <0x1>;
|
||||
--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
|
||||
+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
|
||||
@@ -125,8 +125,6 @@
|
||||
};
|
||||
|
||||
&nandcs {
|
||||
- nand-ecc-algo = "hw";
|
||||
-
|
||||
partitions {
|
||||
/*
|
||||
* The partition autodetection does not work for this device.
|
||||
@ -0,0 +1,54 @@
|
||||
From d68b2f7d7d06872450d4f39d84d5926d7e7ae88c Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Thu, 8 Jun 2023 17:36:28 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: MR32: remove partition index numbers
|
||||
|
||||
removes the partition indexes in the node names under.
|
||||
This brings the device tree source in line with others.
|
||||
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Link: https://lore.kernel.org/r/627f57d568030a56499361790524b4d4f3381619.1686238550.git.chunkeey@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
|
||||
+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
|
||||
@@ -138,31 +138,31 @@
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x1>;
|
||||
|
||||
- partition0@0 {
|
||||
+ partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
- partition1@100000 {
|
||||
+ partition@100000 {
|
||||
label = "bootkernel1";
|
||||
reg = <0x100000 0x300000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
- partition2@400000 {
|
||||
+ partition@400000 {
|
||||
label = "nvram";
|
||||
reg = <0x400000 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
- partition3@500000 {
|
||||
+ partition@500000 {
|
||||
label = "bootkernel2";
|
||||
reg = <0x500000 0x300000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
- partition4@800000 {
|
||||
+ partition@800000 {
|
||||
label = "ubi";
|
||||
reg = <0x800000 0x7780000>;
|
||||
};
|
||||
@ -0,0 +1,44 @@
|
||||
From fd274b733bfdde3ca72f0fa2a37f032f3a8c402c Mon Sep 17 00:00:00 2001
|
||||
From: Christian Lamparter <chunkeey@gmail.com>
|
||||
Date: Thu, 8 Jun 2023 17:36:29 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: fix duplex-full => full-duplex
|
||||
|
||||
this typo was found by the dtbs_check
|
||||
| ports:port@5:fixed-link: 'oneOf' conditional failed,
|
||||
| {'speed': [[1000]], 'duplex-full': True} is not of type 'array'
|
||||
| 'duplex-full' does not match any of the regexes: 'pinctrl-[0-]..."
|
||||
|
||||
this should have been full-duplex;
|
||||
|
||||
Fixes: 935327a73553 ("ARM: dts: BCM5301X: Add DT for Meraki MR26")
|
||||
Fixes: ec88a9c344d9 ("ARM: BCM5301X: Add DT for Meraki MR32")
|
||||
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
|
||||
Link: https://lore.kernel.org/r/50522f45566951a9eabd22820647924cc6b4a264.1686238550.git.chunkeey@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm53015-meraki-mr26.dts | 2 +-
|
||||
arch/arm/boot/dts/bcm53016-meraki-mr32.dts | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
|
||||
+++ b/arch/arm/boot/dts/bcm53015-meraki-mr26.dts
|
||||
@@ -121,7 +121,7 @@
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
- duplex-full;
|
||||
+ full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
|
||||
+++ b/arch/arm/boot/dts/bcm53016-meraki-mr32.dts
|
||||
@@ -182,7 +182,7 @@
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
- duplex-full;
|
||||
+ full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,61 @@
|
||||
From 752a63b8dbe6cc6900efd1035bea427a778a4b55 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Fri, 2 Jun 2023 15:59:25 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Add Netgear R8000 WiFi regulator mappings
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This allows setting FullMAC firmware regulatory domain.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Link: https://lore.kernel.org/r/20230602135925.14143-3-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm4709-netgear-r8000.dts | 17 +++++++++++++++++
|
||||
1 file changed, 17 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts
|
||||
@@ -137,8 +137,10 @@
|
||||
#size-cells = <2>;
|
||||
|
||||
wifi@0,1,0 {
|
||||
+ compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
ieee80211-freq-limit = <5735000 5835000>;
|
||||
+ brcm,ccode-map = "JP-JP-78", "US-Q2-86";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -159,6 +161,19 @@
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
+ bridge@1,0 {
|
||||
+ reg = <0x800 0 0 0 0>;
|
||||
+
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
+
|
||||
+ wifi@0,0 {
|
||||
+ compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
|
||||
+ reg = <0x0000 0 0 0 0>;
|
||||
+ brcm,ccode-map = "JP-JP-78", "US-Q2-86";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
bridge@1,2,2 {
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
|
||||
@@ -166,8 +181,10 @@
|
||||
#size-cells = <2>;
|
||||
|
||||
wifi@1,4,0 {
|
||||
+ compatible = "brcm,bcm4366-fmac", "brcm,bcm4329-fmac";
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
ieee80211-freq-limit = <5170000 5730000>;
|
||||
+ brcm,ccode-map = "JP-JP-78", "US-Q2-86";
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,59 @@
|
||||
From b67cad33176e472df6d16a24ee7624299bdcd5d5 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Fri, 16 Jun 2023 12:58:27 +0200
|
||||
Subject: [PATCH] ARM: dts: BCM5301X: Add cells sizes to PCIe nodes
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This fixes:
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#address-cells' is a required property
|
||||
From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@12000: '#size-cells' is a required property
|
||||
From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#address-cells' is a required property
|
||||
From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@13000: '#size-cells' is a required property
|
||||
From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#address-cells' is a required property
|
||||
From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
|
||||
arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dtb: pcie@14000: '#size-cells' is a required property
|
||||
From schema: /lib/python3.10/site-packages/dtschema/schemas/pci/pci-bus.yaml
|
||||
|
||||
Two properties that need to be added later are "device_type" and
|
||||
"ranges". Adding "device_type" on its own causes a new warning and the
|
||||
value of "ranges" needs to be determined yet.
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Link: https://lore.kernel.org/r/20230616105827.21656-1-zajec5@gmail.com
|
||||
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
|
||||
---
|
||||
arch/arm/boot/dts/bcm-ns.dtsi | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
+++ b/arch/arm/boot/dts/bcm-ns.dtsi
|
||||
@@ -176,14 +176,23 @@
|
||||
|
||||
pcie0: pcie@12000 {
|
||||
reg = <0x00012000 0x1000>;
|
||||
+
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
};
|
||||
|
||||
pcie1: pcie@13000 {
|
||||
reg = <0x00013000 0x1000>;
|
||||
+
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
};
|
||||
|
||||
pcie2: pcie@14000 {
|
||||
reg = <0x00014000 0x1000>;
|
||||
+
|
||||
+ #address-cells = <3>;
|
||||
+ #size-cells = <2>;
|
||||
};
|
||||
|
||||
usb2: usb2@21000 {
|
||||
@ -10,7 +10,7 @@ Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
|
||||
--- a/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
|
||||
+++ b/arch/arm/boot/dts/bcm4708-asus-rt-ac56u.dts
|
||||
@@ -93,3 +93,40 @@
|
||||
@@ -92,3 +92,40 @@
|
||||
&usb3_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -0,0 +1,45 @@
|
||||
From e7731194fdf085f46d58b1adccfddbd0dfee4873 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Fri, 7 Jul 2023 08:53:25 +0200
|
||||
Subject: [PATCH] net: bgmac: postpone turning IRQs off to avoid SoC hangs
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Turning IRQs off is done by accessing Ethernet controller registers.
|
||||
That can't be done until device's clock is enabled. It results in a SoC
|
||||
hang otherwise.
|
||||
|
||||
This bug remained unnoticed for years as most bootloaders keep all
|
||||
Ethernet interfaces turned on. It seems to only affect a niche SoC
|
||||
family BCM47189. It has two Ethernet controllers but CFE bootloader uses
|
||||
only the first one.
|
||||
|
||||
Fixes: 34322615cbaa ("net: bgmac: Mask interrupts during probe")
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
|
||||
Signed-off-by: David S. Miller <davem@davemloft.net>
|
||||
---
|
||||
drivers/net/ethernet/broadcom/bgmac.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/net/ethernet/broadcom/bgmac.c
|
||||
+++ b/drivers/net/ethernet/broadcom/bgmac.c
|
||||
@@ -1492,8 +1492,6 @@ int bgmac_enet_probe(struct bgmac *bgmac
|
||||
|
||||
bgmac->in_init = true;
|
||||
|
||||
- bgmac_chip_intrs_off(bgmac);
|
||||
-
|
||||
net_dev->irq = bgmac->irq;
|
||||
SET_NETDEV_DEV(net_dev, bgmac->dev);
|
||||
dev_set_drvdata(bgmac->dev, bgmac);
|
||||
@@ -1511,6 +1509,8 @@ int bgmac_enet_probe(struct bgmac *bgmac
|
||||
*/
|
||||
bgmac_clk_enable(bgmac, 0);
|
||||
|
||||
+ bgmac_chip_intrs_off(bgmac);
|
||||
+
|
||||
/* This seems to be fixing IRQ by assigning OOB #6 to the core */
|
||||
if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
|
||||
if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
|
||||
@ -0,0 +1,31 @@
|
||||
From eebc6573ad940b62a87776db3917e912b4f52d78 Mon Sep 17 00:00:00 2001
|
||||
From: Tom Rix <trix@redhat.com>
|
||||
Date: Sun, 11 Jun 2023 15:03:05 +0100
|
||||
Subject: [PATCH] nvmem: imx-ocotp: set varaiable imx_ocotp_layout
|
||||
storage-class-specifier to static
|
||||
|
||||
smatch reports
|
||||
drivers/nvmem/imx-ocotp.c:599:21: warning: symbol
|
||||
'imx_ocotp_layout' was not declared. Should it be static?
|
||||
|
||||
This variable is only used in one file so should be static.
|
||||
|
||||
Signed-off-by: Tom Rix <trix@redhat.com>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-2-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/imx-ocotp.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/nvmem/imx-ocotp.c
|
||||
+++ b/drivers/nvmem/imx-ocotp.c
|
||||
@@ -596,7 +596,7 @@ static void imx_ocotp_fixup_cell_info(st
|
||||
cell->read_post_process = imx_ocotp_cell_pp;
|
||||
}
|
||||
|
||||
-struct nvmem_layout imx_ocotp_layout = {
|
||||
+static struct nvmem_layout imx_ocotp_layout = {
|
||||
.fixup_cell_info = imx_ocotp_fixup_cell_info,
|
||||
};
|
||||
|
||||
@ -0,0 +1,71 @@
|
||||
From 8a00fc606312c68b98add8fe8e6f7a013ce29e78 Mon Sep 17 00:00:00 2001
|
||||
From: Alexander Stein <alexander.stein@ew.tq-group.com>
|
||||
Date: Sun, 11 Jun 2023 15:03:06 +0100
|
||||
Subject: [PATCH] nvmem: imx-ocotp: Reverse MAC addresses on all i.MX derivates
|
||||
|
||||
Not just i.MX8M, but all i.MX6/7 (and subtypes) need to reverse the
|
||||
MAC address read from fuses. Exceptions are i.MX6SLL and i.MX7ULP which
|
||||
do not support ethernet at all.
|
||||
|
||||
Fixes: d0221a780cbc ("nvmem: imx-ocotp: add support for post processing")
|
||||
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
|
||||
Tested-by: Richard Leitner <richard.leitner@skidata.com> # imx6q
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-3-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/imx-ocotp.c | 8 +-------
|
||||
1 file changed, 1 insertion(+), 7 deletions(-)
|
||||
|
||||
--- a/drivers/nvmem/imx-ocotp.c
|
||||
+++ b/drivers/nvmem/imx-ocotp.c
|
||||
@@ -97,7 +97,6 @@ struct ocotp_params {
|
||||
unsigned int bank_address_words;
|
||||
void (*set_timing)(struct ocotp_priv *priv);
|
||||
struct ocotp_ctrl_reg ctrl;
|
||||
- bool reverse_mac_address;
|
||||
};
|
||||
|
||||
static int imx_ocotp_wait_for_busy(struct ocotp_priv *priv, u32 flags)
|
||||
@@ -545,7 +544,6 @@ static const struct ocotp_params imx8mq_
|
||||
.bank_address_words = 0,
|
||||
.set_timing = imx_ocotp_set_imx6_timing,
|
||||
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
||||
- .reverse_mac_address = true,
|
||||
};
|
||||
|
||||
static const struct ocotp_params imx8mm_params = {
|
||||
@@ -553,7 +551,6 @@ static const struct ocotp_params imx8mm_
|
||||
.bank_address_words = 0,
|
||||
.set_timing = imx_ocotp_set_imx6_timing,
|
||||
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
||||
- .reverse_mac_address = true,
|
||||
};
|
||||
|
||||
static const struct ocotp_params imx8mn_params = {
|
||||
@@ -561,7 +558,6 @@ static const struct ocotp_params imx8mn_
|
||||
.bank_address_words = 0,
|
||||
.set_timing = imx_ocotp_set_imx6_timing,
|
||||
.ctrl = IMX_OCOTP_BM_CTRL_DEFAULT,
|
||||
- .reverse_mac_address = true,
|
||||
};
|
||||
|
||||
static const struct ocotp_params imx8mp_params = {
|
||||
@@ -569,7 +565,6 @@ static const struct ocotp_params imx8mp_
|
||||
.bank_address_words = 0,
|
||||
.set_timing = imx_ocotp_set_imx6_timing,
|
||||
.ctrl = IMX_OCOTP_BM_CTRL_8MP,
|
||||
- .reverse_mac_address = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id imx_ocotp_dt_ids[] = {
|
||||
@@ -624,8 +619,7 @@ static int imx_ocotp_probe(struct platfo
|
||||
imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
|
||||
imx_ocotp_nvmem_config.dev = dev;
|
||||
imx_ocotp_nvmem_config.priv = priv;
|
||||
- if (priv->params->reverse_mac_address)
|
||||
- imx_ocotp_nvmem_config.layout = &imx_ocotp_layout;
|
||||
+ imx_ocotp_nvmem_config.layout = &imx_ocotp_layout;
|
||||
|
||||
priv->config = &imx_ocotp_nvmem_config;
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
From 73bcd133c910bff3b6d3b3834d0d14be9444e90a Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Thu, 6 Apr 2023 12:46:16 +0200
|
||||
Date: Sun, 11 Jun 2023 15:03:08 +0100
|
||||
Subject: [PATCH] nvmem: brcm_nvram: add .read_post_process() for MACs
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
@ -9,6 +10,9 @@ Content-Transfer-Encoding: 8bit
|
||||
2. Calculate relative addresses based on index argument
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-5-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/Kconfig | 1 +
|
||||
drivers/nvmem/brcm_nvram.c | 28 ++++++++++++++++++++++++++++
|
||||
@ -0,0 +1,166 @@
|
||||
From 8dc61364164e79e44c07fa2ac0a7b6939f00d5db Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Sun, 11 Jun 2023 15:03:13 +0100
|
||||
Subject: [PATCH] nvmem: rockchip-otp: Add clks and reg_read to rockchip_data
|
||||
|
||||
In preparation to support new Rockchip OTP memory devices with different
|
||||
clock configurations and register layout, extend rockchip_data struct
|
||||
with the related members: clks, num_clks, reg_read.
|
||||
|
||||
Additionally, to avoid managing redundant driver data, drop num_clks
|
||||
member from rockchip_otp struct and update all references to point to
|
||||
the equivalent member in rockchip_data.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-10-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/rockchip-otp.c | 79 ++++++++++++++++++++++--------------
|
||||
1 file changed, 49 insertions(+), 30 deletions(-)
|
||||
|
||||
--- a/drivers/nvmem/rockchip-otp.c
|
||||
+++ b/drivers/nvmem/rockchip-otp.c
|
||||
@@ -54,21 +54,19 @@
|
||||
|
||||
#define OTPC_TIMEOUT 10000
|
||||
|
||||
+struct rockchip_data {
|
||||
+ int size;
|
||||
+ const char * const *clks;
|
||||
+ int num_clks;
|
||||
+ nvmem_reg_read_t reg_read;
|
||||
+};
|
||||
+
|
||||
struct rockchip_otp {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
- struct clk_bulk_data *clks;
|
||||
- int num_clks;
|
||||
+ struct clk_bulk_data *clks;
|
||||
struct reset_control *rst;
|
||||
-};
|
||||
-
|
||||
-/* list of required clocks */
|
||||
-static const char * const rockchip_otp_clocks[] = {
|
||||
- "otp", "apb_pclk", "phy",
|
||||
-};
|
||||
-
|
||||
-struct rockchip_data {
|
||||
- int size;
|
||||
+ const struct rockchip_data *data;
|
||||
};
|
||||
|
||||
static int rockchip_otp_reset(struct rockchip_otp *otp)
|
||||
@@ -132,29 +130,23 @@ static int rockchip_otp_ecc_enable(struc
|
||||
return ret;
|
||||
}
|
||||
|
||||
-static int rockchip_otp_read(void *context, unsigned int offset,
|
||||
- void *val, size_t bytes)
|
||||
+static int px30_otp_read(void *context, unsigned int offset,
|
||||
+ void *val, size_t bytes)
|
||||
{
|
||||
struct rockchip_otp *otp = context;
|
||||
u8 *buf = val;
|
||||
- int ret = 0;
|
||||
-
|
||||
- ret = clk_bulk_prepare_enable(otp->num_clks, otp->clks);
|
||||
- if (ret < 0) {
|
||||
- dev_err(otp->dev, "failed to prepare/enable clks\n");
|
||||
- return ret;
|
||||
- }
|
||||
+ int ret;
|
||||
|
||||
ret = rockchip_otp_reset(otp);
|
||||
if (ret) {
|
||||
dev_err(otp->dev, "failed to reset otp phy\n");
|
||||
- goto disable_clks;
|
||||
+ return ret;
|
||||
}
|
||||
|
||||
ret = rockchip_otp_ecc_enable(otp, false);
|
||||
if (ret < 0) {
|
||||
dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
|
||||
- goto disable_clks;
|
||||
+ return ret;
|
||||
}
|
||||
|
||||
writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
|
||||
@@ -174,8 +166,28 @@ static int rockchip_otp_read(void *conte
|
||||
|
||||
read_end:
|
||||
writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
|
||||
-disable_clks:
|
||||
- clk_bulk_disable_unprepare(otp->num_clks, otp->clks);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_otp_read(void *context, unsigned int offset,
|
||||
+ void *val, size_t bytes)
|
||||
+{
|
||||
+ struct rockchip_otp *otp = context;
|
||||
+ int ret;
|
||||
+
|
||||
+ if (!otp->data || !otp->data->reg_read)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ ret = clk_bulk_prepare_enable(otp->data->num_clks, otp->clks);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(otp->dev, "failed to prepare/enable clks\n");
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
+ ret = otp->data->reg_read(context, offset, val, bytes);
|
||||
+
|
||||
+ clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -189,8 +201,15 @@ static struct nvmem_config otp_config =
|
||||
.reg_read = rockchip_otp_read,
|
||||
};
|
||||
|
||||
+static const char * const px30_otp_clocks[] = {
|
||||
+ "otp", "apb_pclk", "phy",
|
||||
+};
|
||||
+
|
||||
static const struct rockchip_data px30_data = {
|
||||
.size = 0x40,
|
||||
+ .clks = px30_otp_clocks,
|
||||
+ .num_clks = ARRAY_SIZE(px30_otp_clocks),
|
||||
+ .reg_read = px30_otp_read,
|
||||
};
|
||||
|
||||
static const struct of_device_id rockchip_otp_match[] = {
|
||||
@@ -225,21 +244,21 @@ static int rockchip_otp_probe(struct pla
|
||||
if (!otp)
|
||||
return -ENOMEM;
|
||||
|
||||
+ otp->data = data;
|
||||
otp->dev = dev;
|
||||
otp->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(otp->base))
|
||||
return PTR_ERR(otp->base);
|
||||
|
||||
- otp->num_clks = ARRAY_SIZE(rockchip_otp_clocks);
|
||||
- otp->clks = devm_kcalloc(dev, otp->num_clks,
|
||||
- sizeof(*otp->clks), GFP_KERNEL);
|
||||
+ otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks),
|
||||
+ GFP_KERNEL);
|
||||
if (!otp->clks)
|
||||
return -ENOMEM;
|
||||
|
||||
- for (i = 0; i < otp->num_clks; ++i)
|
||||
- otp->clks[i].id = rockchip_otp_clocks[i];
|
||||
+ for (i = 0; i < data->num_clks; ++i)
|
||||
+ otp->clks[i].id = data->clks[i];
|
||||
|
||||
- ret = devm_clk_bulk_get(dev, otp->num_clks, otp->clks);
|
||||
+ ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -0,0 +1,62 @@
|
||||
From 30fd21cfb1e64ef20035559a8246f5fbf682c40e Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Sun, 11 Jun 2023 15:03:14 +0100
|
||||
Subject: [PATCH] nvmem: rockchip-otp: Generalize rockchip_otp_wait_status()
|
||||
|
||||
In preparation to support additional Rockchip OTP memory devices with
|
||||
different register layout, generalize rockchip_otp_wait_status() to
|
||||
accept a new parameter for specifying the offset of the status register.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-11-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/rockchip-otp.c | 11 ++++++-----
|
||||
1 file changed, 6 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/nvmem/rockchip-otp.c
|
||||
+++ b/drivers/nvmem/rockchip-otp.c
|
||||
@@ -90,18 +90,19 @@ static int rockchip_otp_reset(struct roc
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int rockchip_otp_wait_status(struct rockchip_otp *otp, u32 flag)
|
||||
+static int rockchip_otp_wait_status(struct rockchip_otp *otp,
|
||||
+ unsigned int reg, u32 flag)
|
||||
{
|
||||
u32 status = 0;
|
||||
int ret;
|
||||
|
||||
- ret = readl_poll_timeout_atomic(otp->base + OTPC_INT_STATUS, status,
|
||||
+ ret = readl_poll_timeout_atomic(otp->base + reg, status,
|
||||
(status & flag), 1, OTPC_TIMEOUT);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* clean int status */
|
||||
- writel(flag, otp->base + OTPC_INT_STATUS);
|
||||
+ writel(flag, otp->base + reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -123,7 +124,7 @@ static int rockchip_otp_ecc_enable(struc
|
||||
|
||||
writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
|
||||
|
||||
- ret = rockchip_otp_wait_status(otp, OTPC_SBPI_DONE);
|
||||
+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_SBPI_DONE);
|
||||
if (ret < 0)
|
||||
dev_err(otp->dev, "timeout during ecc_enable\n");
|
||||
|
||||
@@ -156,7 +157,7 @@ static int px30_otp_read(void *context,
|
||||
otp->base + OTPC_USER_ADDR);
|
||||
writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
|
||||
otp->base + OTPC_USER_ENABLE);
|
||||
- ret = rockchip_otp_wait_status(otp, OTPC_USER_DONE);
|
||||
+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE);
|
||||
if (ret < 0) {
|
||||
dev_err(otp->dev, "timeout during read setup\n");
|
||||
goto read_end;
|
||||
@ -0,0 +1,31 @@
|
||||
From d325c9dd2b6e94040ca722ddcadcd6af358dd2be Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Sun, 11 Jun 2023 15:03:15 +0100
|
||||
Subject: [PATCH] nvmem: rockchip-otp: Use
|
||||
devm_reset_control_array_get_exclusive()
|
||||
|
||||
In preparation to support new Rockchip OTP memory devices having
|
||||
specific reset configurations, switch devm_reset_control_get() to
|
||||
devm_reset_control_array_get_exclusive().
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-12-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/rockchip-otp.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/nvmem/rockchip-otp.c
|
||||
+++ b/drivers/nvmem/rockchip-otp.c
|
||||
@@ -263,7 +263,7 @@ static int rockchip_otp_probe(struct pla
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
- otp->rst = devm_reset_control_get(dev, "phy");
|
||||
+ otp->rst = devm_reset_control_array_get_exclusive(dev);
|
||||
if (IS_ERR(otp->rst))
|
||||
return PTR_ERR(otp->rst);
|
||||
|
||||
@ -0,0 +1,71 @@
|
||||
From 912517345b867a69542dc9f5c2cc3e9d8beaccf5 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Sun, 11 Jun 2023 15:03:16 +0100
|
||||
Subject: [PATCH] nvmem: rockchip-otp: Improve probe error handling
|
||||
|
||||
Enhance error handling in the probe function by making use of
|
||||
dev_err_probe(), which ensures the error code is always printed, in
|
||||
addition to the specified error message.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-13-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/rockchip-otp.c | 21 ++++++++++++---------
|
||||
1 file changed, 12 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/drivers/nvmem/rockchip-otp.c
|
||||
+++ b/drivers/nvmem/rockchip-otp.c
|
||||
@@ -235,10 +235,8 @@ static int rockchip_otp_probe(struct pla
|
||||
int ret, i;
|
||||
|
||||
data = of_device_get_match_data(dev);
|
||||
- if (!data) {
|
||||
- dev_err(dev, "failed to get match data\n");
|
||||
- return -EINVAL;
|
||||
- }
|
||||
+ if (!data)
|
||||
+ return dev_err_probe(dev, -EINVAL, "failed to get match data\n");
|
||||
|
||||
otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp),
|
||||
GFP_KERNEL);
|
||||
@@ -249,7 +247,8 @@ static int rockchip_otp_probe(struct pla
|
||||
otp->dev = dev;
|
||||
otp->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(otp->base))
|
||||
- return PTR_ERR(otp->base);
|
||||
+ return dev_err_probe(dev, PTR_ERR(otp->base),
|
||||
+ "failed to ioremap resource\n");
|
||||
|
||||
otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks),
|
||||
GFP_KERNEL);
|
||||
@@ -261,18 +260,22 @@ static int rockchip_otp_probe(struct pla
|
||||
|
||||
ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks);
|
||||
if (ret)
|
||||
- return ret;
|
||||
+ return dev_err_probe(dev, ret, "failed to get clocks\n");
|
||||
|
||||
otp->rst = devm_reset_control_array_get_exclusive(dev);
|
||||
if (IS_ERR(otp->rst))
|
||||
- return PTR_ERR(otp->rst);
|
||||
+ return dev_err_probe(dev, PTR_ERR(otp->rst),
|
||||
+ "failed to get resets\n");
|
||||
|
||||
otp_config.size = data->size;
|
||||
otp_config.priv = otp;
|
||||
otp_config.dev = dev;
|
||||
- nvmem = devm_nvmem_register(dev, &otp_config);
|
||||
|
||||
- return PTR_ERR_OR_ZERO(nvmem);
|
||||
+ nvmem = devm_nvmem_register(dev, &otp_config);
|
||||
+ if (IS_ERR(nvmem))
|
||||
+ return dev_err_probe(dev, PTR_ERR(nvmem),
|
||||
+ "failed to register nvmem device\n");
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver rockchip_otp_driver = {
|
||||
@ -0,0 +1,129 @@
|
||||
From 8ab099fafbbc8c9607c399d21a774784a6cb8b45 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Sun, 11 Jun 2023 15:03:17 +0100
|
||||
Subject: [PATCH] nvmem: rockchip-otp: Add support for RK3588
|
||||
|
||||
Add support for the OTP memory device found on the Rockchip RK3588 SoC.
|
||||
|
||||
While here, remove the unnecessary 'void *' casts in the OF device ID
|
||||
table.
|
||||
|
||||
Co-developed-by: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-14-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/rockchip-otp.c | 78 +++++++++++++++++++++++++++++++++++-
|
||||
1 file changed, 76 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/nvmem/rockchip-otp.c
|
||||
+++ b/drivers/nvmem/rockchip-otp.c
|
||||
@@ -54,6 +54,19 @@
|
||||
|
||||
#define OTPC_TIMEOUT 10000
|
||||
|
||||
+/* RK3588 Register */
|
||||
+#define RK3588_OTPC_AUTO_CTRL 0x04
|
||||
+#define RK3588_OTPC_AUTO_EN 0x08
|
||||
+#define RK3588_OTPC_INT_ST 0x84
|
||||
+#define RK3588_OTPC_DOUT0 0x20
|
||||
+#define RK3588_NO_SECURE_OFFSET 0x300
|
||||
+#define RK3588_NBYTES 4
|
||||
+#define RK3588_BURST_NUM 1
|
||||
+#define RK3588_BURST_SHIFT 8
|
||||
+#define RK3588_ADDR_SHIFT 16
|
||||
+#define RK3588_AUTO_EN BIT(0)
|
||||
+#define RK3588_RD_DONE BIT(1)
|
||||
+
|
||||
struct rockchip_data {
|
||||
int size;
|
||||
const char * const *clks;
|
||||
@@ -171,6 +184,52 @@ read_end:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static int rk3588_otp_read(void *context, unsigned int offset,
|
||||
+ void *val, size_t bytes)
|
||||
+{
|
||||
+ struct rockchip_otp *otp = context;
|
||||
+ unsigned int addr_start, addr_end, addr_len;
|
||||
+ int ret, i = 0;
|
||||
+ u32 data;
|
||||
+ u8 *buf;
|
||||
+
|
||||
+ addr_start = round_down(offset, RK3588_NBYTES) / RK3588_NBYTES;
|
||||
+ addr_end = round_up(offset + bytes, RK3588_NBYTES) / RK3588_NBYTES;
|
||||
+ addr_len = addr_end - addr_start;
|
||||
+ addr_start += RK3588_NO_SECURE_OFFSET;
|
||||
+
|
||||
+ buf = kzalloc(array_size(addr_len, RK3588_NBYTES), GFP_KERNEL);
|
||||
+ if (!buf)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ while (addr_len--) {
|
||||
+ writel((addr_start << RK3588_ADDR_SHIFT) |
|
||||
+ (RK3588_BURST_NUM << RK3588_BURST_SHIFT),
|
||||
+ otp->base + RK3588_OTPC_AUTO_CTRL);
|
||||
+ writel(RK3588_AUTO_EN, otp->base + RK3588_OTPC_AUTO_EN);
|
||||
+
|
||||
+ ret = rockchip_otp_wait_status(otp, RK3588_OTPC_INT_ST,
|
||||
+ RK3588_RD_DONE);
|
||||
+ if (ret < 0) {
|
||||
+ dev_err(otp->dev, "timeout during read setup\n");
|
||||
+ goto read_end;
|
||||
+ }
|
||||
+
|
||||
+ data = readl(otp->base + RK3588_OTPC_DOUT0);
|
||||
+ memcpy(&buf[i], &data, RK3588_NBYTES);
|
||||
+
|
||||
+ i += RK3588_NBYTES;
|
||||
+ addr_start++;
|
||||
+ }
|
||||
+
|
||||
+ memcpy(val, buf + offset % RK3588_NBYTES, bytes);
|
||||
+
|
||||
+read_end:
|
||||
+ kfree(buf);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
static int rockchip_otp_read(void *context, unsigned int offset,
|
||||
void *val, size_t bytes)
|
||||
{
|
||||
@@ -213,14 +272,29 @@ static const struct rockchip_data px30_d
|
||||
.reg_read = px30_otp_read,
|
||||
};
|
||||
|
||||
+static const char * const rk3588_otp_clocks[] = {
|
||||
+ "otp", "apb_pclk", "phy", "arb",
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_data rk3588_data = {
|
||||
+ .size = 0x400,
|
||||
+ .clks = rk3588_otp_clocks,
|
||||
+ .num_clks = ARRAY_SIZE(rk3588_otp_clocks),
|
||||
+ .reg_read = rk3588_otp_read,
|
||||
+};
|
||||
+
|
||||
static const struct of_device_id rockchip_otp_match[] = {
|
||||
{
|
||||
.compatible = "rockchip,px30-otp",
|
||||
- .data = (void *)&px30_data,
|
||||
+ .data = &px30_data,
|
||||
},
|
||||
{
|
||||
.compatible = "rockchip,rk3308-otp",
|
||||
- .data = (void *)&px30_data,
|
||||
+ .data = &px30_data,
|
||||
+ },
|
||||
+ {
|
||||
+ .compatible = "rockchip,rk3588-otp",
|
||||
+ .data = &rk3588_data,
|
||||
},
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
@ -0,0 +1,26 @@
|
||||
From 9734408969e978a1c0d5d752be63dd638288e374 Mon Sep 17 00:00:00 2001
|
||||
From: Michal Simek <michal.simek@amd.com>
|
||||
Date: Sun, 11 Jun 2023 15:03:23 +0100
|
||||
Subject: [PATCH] nvmem: zynqmp: Switch @xilinx.com emails to @amd.com
|
||||
|
||||
@xilinx.com is still working but better to switch to new amd.com after
|
||||
AMD/Xilinx acquisition.
|
||||
|
||||
Signed-off-by: Michal Simek <michal.simek@amd.com>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-20-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/zynqmp_nvmem.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/nvmem/zynqmp_nvmem.c
|
||||
+++ b/drivers/nvmem/zynqmp_nvmem.c
|
||||
@@ -76,6 +76,6 @@ static struct platform_driver zynqmp_nvm
|
||||
|
||||
module_platform_driver(zynqmp_nvmem_driver);
|
||||
|
||||
-MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>, Nava kishore Manne <navam@xilinx.com>");
|
||||
+MODULE_AUTHOR("Michal Simek <michal.simek@amd.com>, Nava kishore Manne <nava.kishore.manne@amd.com>");
|
||||
MODULE_DESCRIPTION("ZynqMP NVMEM driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -0,0 +1,230 @@
|
||||
From 22e9e6fcfb5042cb6d6c7874c459b034800092f1 Mon Sep 17 00:00:00 2001
|
||||
From: Peng Fan <peng.fan@nxp.com>
|
||||
Date: Sun, 11 Jun 2023 15:03:25 +0100
|
||||
Subject: [PATCH] nvmem: imx: support i.MX93 OCOTP
|
||||
|
||||
Add i.MX93 OCOTP support. i.MX93 OCOTP has two parts: Fuse shadow
|
||||
block(fsb) and fuse managed by ELE. The FSB part could be directly
|
||||
accessed with MMIO, the ELE could only be accessed with ELE API.
|
||||
|
||||
Currently the ELE API is not ready, so NULL function callback is used,
|
||||
but it was tested with downstream ELE API.
|
||||
|
||||
Signed-off-by: Peng Fan <peng.fan@nxp.com>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-22-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/Kconfig | 9 ++
|
||||
drivers/nvmem/Makefile | 2 +
|
||||
drivers/nvmem/imx-ocotp-ele.c | 175 ++++++++++++++++++++++++++++++++++
|
||||
3 files changed, 186 insertions(+)
|
||||
create mode 100644 drivers/nvmem/imx-ocotp-ele.c
|
||||
|
||||
--- a/drivers/nvmem/Kconfig
|
||||
+++ b/drivers/nvmem/Kconfig
|
||||
@@ -83,6 +83,15 @@ config NVMEM_IMX_OCOTP
|
||||
This driver can also be built as a module. If so, the module
|
||||
will be called nvmem-imx-ocotp.
|
||||
|
||||
+config NVMEM_IMX_OCOTP_ELE
|
||||
+ tristate "i.MX On-Chip OTP Controller support"
|
||||
+ depends on ARCH_MXC || COMPILE_TEST
|
||||
+ depends on HAS_IOMEM
|
||||
+ depends on OF
|
||||
+ help
|
||||
+ This is a driver for the On-Chip OTP Controller (OCOTP)
|
||||
+ available on i.MX SoCs which has ELE.
|
||||
+
|
||||
config NVMEM_IMX_OCOTP_SCU
|
||||
tristate "i.MX8 SCU On-Chip OTP Controller support"
|
||||
depends on IMX_SCU
|
||||
--- a/drivers/nvmem/Makefile
|
||||
+++ b/drivers/nvmem/Makefile
|
||||
@@ -18,6 +18,8 @@ obj-$(CONFIG_NVMEM_IMX_IIM) += nvmem-im
|
||||
nvmem-imx-iim-y := imx-iim.o
|
||||
obj-$(CONFIG_NVMEM_IMX_OCOTP) += nvmem-imx-ocotp.o
|
||||
nvmem-imx-ocotp-y := imx-ocotp.o
|
||||
+obj-$(CONFIG_NVMEM_IMX_OCOTP_ELE) += nvmem-imx-ocotp-ele.o
|
||||
+nvmem-imx-ocotp-ele-y := imx-ocotp-ele.o
|
||||
obj-$(CONFIG_NVMEM_IMX_OCOTP_SCU) += nvmem-imx-ocotp-scu.o
|
||||
nvmem-imx-ocotp-scu-y := imx-ocotp-scu.o
|
||||
obj-$(CONFIG_NVMEM_JZ4780_EFUSE) += nvmem_jz4780_efuse.o
|
||||
--- /dev/null
|
||||
+++ b/drivers/nvmem/imx-ocotp-ele.c
|
||||
@@ -0,0 +1,175 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-only
|
||||
+/*
|
||||
+ * i.MX9 OCOTP fusebox driver
|
||||
+ *
|
||||
+ * Copyright 2023 NXP
|
||||
+ */
|
||||
+
|
||||
+#include <linux/device.h>
|
||||
+#include <linux/io.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/nvmem-provider.h>
|
||||
+#include <linux/of_device.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/slab.h>
|
||||
+
|
||||
+enum fuse_type {
|
||||
+ FUSE_FSB = 1,
|
||||
+ FUSE_ELE = 2,
|
||||
+ FUSE_INVALID = -1
|
||||
+};
|
||||
+
|
||||
+struct ocotp_map_entry {
|
||||
+ u32 start; /* start word */
|
||||
+ u32 num; /* num words */
|
||||
+ enum fuse_type type;
|
||||
+};
|
||||
+
|
||||
+struct ocotp_devtype_data {
|
||||
+ u32 reg_off;
|
||||
+ char *name;
|
||||
+ u32 size;
|
||||
+ u32 num_entry;
|
||||
+ u32 flag;
|
||||
+ nvmem_reg_read_t reg_read;
|
||||
+ struct ocotp_map_entry entry[];
|
||||
+};
|
||||
+
|
||||
+struct imx_ocotp_priv {
|
||||
+ struct device *dev;
|
||||
+ void __iomem *base;
|
||||
+ struct nvmem_config config;
|
||||
+ struct mutex lock;
|
||||
+ const struct ocotp_devtype_data *data;
|
||||
+};
|
||||
+
|
||||
+static enum fuse_type imx_ocotp_fuse_type(void *context, u32 index)
|
||||
+{
|
||||
+ struct imx_ocotp_priv *priv = context;
|
||||
+ const struct ocotp_devtype_data *data = priv->data;
|
||||
+ u32 start, end;
|
||||
+ int i;
|
||||
+
|
||||
+ for (i = 0; i < data->num_entry; i++) {
|
||||
+ start = data->entry[i].start;
|
||||
+ end = data->entry[i].start + data->entry[i].num;
|
||||
+
|
||||
+ if (index >= start && index < end)
|
||||
+ return data->entry[i].type;
|
||||
+ }
|
||||
+
|
||||
+ return FUSE_INVALID;
|
||||
+}
|
||||
+
|
||||
+static int imx_ocotp_reg_read(void *context, unsigned int offset, void *val, size_t bytes)
|
||||
+{
|
||||
+ struct imx_ocotp_priv *priv = context;
|
||||
+ void __iomem *reg = priv->base + priv->data->reg_off;
|
||||
+ u32 count, index, num_bytes;
|
||||
+ enum fuse_type type;
|
||||
+ u32 *buf;
|
||||
+ void *p;
|
||||
+ int i;
|
||||
+
|
||||
+ index = offset;
|
||||
+ num_bytes = round_up(bytes, 4);
|
||||
+ count = num_bytes >> 2;
|
||||
+
|
||||
+ if (count > ((priv->data->size >> 2) - index))
|
||||
+ count = (priv->data->size >> 2) - index;
|
||||
+
|
||||
+ p = kzalloc(num_bytes, GFP_KERNEL);
|
||||
+ if (!p)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ mutex_lock(&priv->lock);
|
||||
+
|
||||
+ buf = p;
|
||||
+
|
||||
+ for (i = index; i < (index + count); i++) {
|
||||
+ type = imx_ocotp_fuse_type(context, i);
|
||||
+ if (type == FUSE_INVALID || type == FUSE_ELE) {
|
||||
+ *buf++ = 0;
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ *buf++ = readl_relaxed(reg + (i << 2));
|
||||
+ }
|
||||
+
|
||||
+ memcpy(val, (u8 *)p, bytes);
|
||||
+
|
||||
+ mutex_unlock(&priv->lock);
|
||||
+
|
||||
+ kfree(p);
|
||||
+
|
||||
+ return 0;
|
||||
+};
|
||||
+
|
||||
+static int imx_ele_ocotp_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ struct device *dev = &pdev->dev;
|
||||
+ struct imx_ocotp_priv *priv;
|
||||
+ struct nvmem_device *nvmem;
|
||||
+
|
||||
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
+ if (!priv)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
+ priv->data = of_device_get_match_data(dev);
|
||||
+
|
||||
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
+ if (IS_ERR(priv->base))
|
||||
+ return PTR_ERR(priv->base);
|
||||
+
|
||||
+ priv->config.dev = dev;
|
||||
+ priv->config.name = "ELE-OCOTP";
|
||||
+ priv->config.id = NVMEM_DEVID_AUTO;
|
||||
+ priv->config.owner = THIS_MODULE;
|
||||
+ priv->config.size = priv->data->size;
|
||||
+ priv->config.reg_read = priv->data->reg_read;
|
||||
+ priv->config.word_size = 4;
|
||||
+ priv->config.stride = 1;
|
||||
+ priv->config.priv = priv;
|
||||
+ priv->config.read_only = true;
|
||||
+ mutex_init(&priv->lock);
|
||||
+
|
||||
+ nvmem = devm_nvmem_register(dev, &priv->config);
|
||||
+ if (IS_ERR(nvmem))
|
||||
+ return PTR_ERR(nvmem);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct ocotp_devtype_data imx93_ocotp_data = {
|
||||
+ .reg_off = 0x8000,
|
||||
+ .reg_read = imx_ocotp_reg_read,
|
||||
+ .size = 2048,
|
||||
+ .num_entry = 6,
|
||||
+ .entry = {
|
||||
+ { 0, 52, FUSE_FSB },
|
||||
+ { 63, 1, FUSE_ELE},
|
||||
+ { 128, 16, FUSE_ELE },
|
||||
+ { 182, 1, FUSE_ELE },
|
||||
+ { 188, 1, FUSE_ELE },
|
||||
+ { 312, 200, FUSE_FSB }
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
+static const struct of_device_id imx_ele_ocotp_dt_ids[] = {
|
||||
+ { .compatible = "fsl,imx93-ocotp", .data = &imx93_ocotp_data, },
|
||||
+ {},
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, imx_ele_ocotp_dt_ids);
|
||||
+
|
||||
+static struct platform_driver imx_ele_ocotp_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "imx_ele_ocotp",
|
||||
+ .of_match_table = imx_ele_ocotp_dt_ids,
|
||||
+ },
|
||||
+ .probe = imx_ele_ocotp_probe,
|
||||
+};
|
||||
+module_platform_driver(imx_ele_ocotp_driver);
|
||||
+
|
||||
+MODULE_DESCRIPTION("i.MX OCOTP/ELE driver");
|
||||
+MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
|
||||
+MODULE_LICENSE("GPL");
|
||||
@ -0,0 +1,96 @@
|
||||
From 27f699e578b1a72df89dfa3bc42e093a01dc8d10 Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
|
||||
Date: Sun, 11 Jun 2023 15:03:29 +0100
|
||||
Subject: [PATCH] nvmem: core: add support for fixed cells *layout*
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
This adds support for the "fixed-layout" NVMEM layout binding. It allows
|
||||
defining NVMEM cells in a layout DT node named "nvmem-layout".
|
||||
|
||||
While NVMEM subsystem supports layout drivers it has been discussed that
|
||||
"fixed-layout" may actually be supperted internally. It's because:
|
||||
1. It's a very basic layout
|
||||
2. It allows sharing code with legacy syntax parsing
|
||||
3. It's safer for soc_device_match() due to -EPROBE_DEFER
|
||||
4. This will make the syntax transition easier
|
||||
|
||||
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
|
||||
Reviewed-by: Michael Walle <michael@walle.cc>
|
||||
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
Message-ID: <20230611140330.154222-26-srinivas.kandagatla@linaro.org>
|
||||
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
||||
---
|
||||
drivers/nvmem/core.c | 32 +++++++++++++++++++++++++++++---
|
||||
1 file changed, 29 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/nvmem/core.c
|
||||
+++ b/drivers/nvmem/core.c
|
||||
@@ -696,7 +696,7 @@ static int nvmem_validate_keepouts(struc
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static int nvmem_add_cells_from_of(struct nvmem_device *nvmem)
|
||||
+static int nvmem_add_cells_from_dt(struct nvmem_device *nvmem, struct device_node *np)
|
||||
{
|
||||
struct nvmem_layout *layout = nvmem->layout;
|
||||
struct device *dev = &nvmem->dev;
|
||||
@@ -704,7 +704,7 @@ static int nvmem_add_cells_from_of(struc
|
||||
const __be32 *addr;
|
||||
int len, ret;
|
||||
|
||||
- for_each_child_of_node(dev->of_node, child) {
|
||||
+ for_each_child_of_node(np, child) {
|
||||
struct nvmem_cell_info info = {0};
|
||||
|
||||
addr = of_get_property(child, "reg", &len);
|
||||
@@ -742,6 +742,28 @@ static int nvmem_add_cells_from_of(struc
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int nvmem_add_cells_from_legacy_of(struct nvmem_device *nvmem)
|
||||
+{
|
||||
+ return nvmem_add_cells_from_dt(nvmem, nvmem->dev.of_node);
|
||||
+}
|
||||
+
|
||||
+static int nvmem_add_cells_from_fixed_layout(struct nvmem_device *nvmem)
|
||||
+{
|
||||
+ struct device_node *layout_np;
|
||||
+ int err = 0;
|
||||
+
|
||||
+ layout_np = of_nvmem_layout_get_container(nvmem);
|
||||
+ if (!layout_np)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (of_device_is_compatible(layout_np, "fixed-layout"))
|
||||
+ err = nvmem_add_cells_from_dt(nvmem, layout_np);
|
||||
+
|
||||
+ of_node_put(layout_np);
|
||||
+
|
||||
+ return err;
|
||||
+}
|
||||
+
|
||||
int __nvmem_layout_register(struct nvmem_layout *layout, struct module *owner)
|
||||
{
|
||||
layout->owner = owner;
|
||||
@@ -972,7 +994,7 @@ struct nvmem_device *nvmem_register(cons
|
||||
if (rval)
|
||||
goto err_remove_cells;
|
||||
|
||||
- rval = nvmem_add_cells_from_of(nvmem);
|
||||
+ rval = nvmem_add_cells_from_legacy_of(nvmem);
|
||||
if (rval)
|
||||
goto err_remove_cells;
|
||||
|
||||
@@ -982,6 +1004,10 @@ struct nvmem_device *nvmem_register(cons
|
||||
if (rval)
|
||||
goto err_remove_cells;
|
||||
|
||||
+ rval = nvmem_add_cells_from_fixed_layout(nvmem);
|
||||
+ if (rval)
|
||||
+ goto err_remove_cells;
|
||||
+
|
||||
rval = nvmem_add_cells_from_layout(nvmem);
|
||||
if (rval)
|
||||
goto err_remove_cells;
|
||||
@ -295,6 +295,7 @@ CONFIG_NR_CPUS=4
|
||||
CONFIG_NVMEM=y
|
||||
# CONFIG_NVMEM_IMX_IIM is not set
|
||||
CONFIG_NVMEM_IMX_OCOTP=y
|
||||
# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
|
||||
# CONFIG_NVMEM_SNVS_LPGPR is not set
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
CONFIG_OF=y
|
||||
|
||||
@ -413,6 +413,7 @@ CONFIG_NR_CPUS=16
|
||||
CONFIG_NTFS_FS=y
|
||||
CONFIG_NVMEM=y
|
||||
# CONFIG_NVMEM_IMX_IIM is not set
|
||||
# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
|
||||
# CONFIG_NVMEM_SNVS_LPGPR is not set
|
||||
# CONFIG_NVMEM_SPMI_SDAM is not set
|
||||
CONFIG_NVMEM_SYSFS=y
|
||||
|
||||
238
target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts
Normal file
238
target/linux/mediatek/dts/mt7629-netgear-ex6250-v2.dts
Normal file
@ -0,0 +1,238 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "mt7629.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Netgear EX6250 v2";
|
||||
compatible = "netgear,ex6250-v2", "mediatek,mt7629";
|
||||
|
||||
aliases {
|
||||
led-boot = &led_power_green;
|
||||
led-failsafe = &led_power_red;
|
||||
led-running = &led_power_green;
|
||||
led-upgrade = &led_power_red;
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs-override = "console=ttyS0,115200n8";
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
gpios = <&pio 60 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
wps {
|
||||
label = "wps";
|
||||
gpios = <&pio 58 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
|
||||
ap_mode {
|
||||
label = "ap_mode";
|
||||
gpios = <&pio 54 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <BTN_0>;
|
||||
};
|
||||
|
||||
extender_mode {
|
||||
label = "extender_mode";
|
||||
gpios = <&pio 53 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <BTN_1>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_power_green: power_green {
|
||||
label = "green:power";
|
||||
gpios = <&pio 21 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led_power_red: power_red {
|
||||
label = "red:power";
|
||||
gpios = <&pio 61 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
client_green {
|
||||
label = "green:client";
|
||||
gpios = <&pio 59 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
client_red {
|
||||
label = "red:client";
|
||||
gpios = <&pio 24 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
router_green {
|
||||
label = "green:router";
|
||||
gpios = <&pio 55 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
router_red {
|
||||
label = "red:router";
|
||||
gpios = <&pio 56 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wps_green {
|
||||
label = "green:wps";
|
||||
gpios = <&pio 57 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
eth_green {
|
||||
label = "green:eth";
|
||||
gpios = <&pio 16 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
eth_yellow {
|
||||
label = "yellow:eth";
|
||||
gpios = <&pio 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ð_pins>;
|
||||
pinctrl-1 = <&ephy_leds_pins>;
|
||||
status = "okay";
|
||||
|
||||
mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
phy-mode = "gmii";
|
||||
phy-handle = <&phy0>;
|
||||
};
|
||||
|
||||
mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "Bootloader";
|
||||
reg = <0x0 0x60000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@60000 {
|
||||
label = "Config";
|
||||
reg = <0x60000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@70000 {
|
||||
label = "Factory";
|
||||
reg = <0x70000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@80000 {
|
||||
label = "firmware";
|
||||
reg = <0x80000 0xcd0000>;
|
||||
compatible = "denx,fit";
|
||||
};
|
||||
|
||||
partition@d50000 {
|
||||
label = "CFG";
|
||||
reg = <0xd50000 0x80000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@dd0000 {
|
||||
label = "RAE";
|
||||
reg = <0xdd0000 0x200000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@fd0000 {
|
||||
label = "POT";
|
||||
reg = <0xfd0000 0x10000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@fe0000 {
|
||||
label = "LOG";
|
||||
reg = <0xfe0000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pio {
|
||||
eth_pins: eth-pins {
|
||||
mux {
|
||||
function = "eth";
|
||||
groups = "mdc_mdio";
|
||||
};
|
||||
};
|
||||
|
||||
ephy_leds_pins: ephy-leds-pins {
|
||||
mux {
|
||||
function = "led";
|
||||
groups = "ephy_leds";
|
||||
};
|
||||
};
|
||||
|
||||
qspi_pins: qspi-pins {
|
||||
mux {
|
||||
function = "flash";
|
||||
groups = "spi_nor";
|
||||
};
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
mux {
|
||||
function = "uart";
|
||||
groups = "uart0_txd_rxd" ;
|
||||
};
|
||||
};
|
||||
|
||||
watchdog_pins: watchdog-pins {
|
||||
mux {
|
||||
function = "watchdog";
|
||||
groups = "watchdog";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&watchdog_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -156,6 +156,7 @@
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mediatek,pio = <&pio>;
|
||||
|
||||
gsw_phy0: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id03a2.9481";
|
||||
|
||||
@ -215,7 +215,7 @@
|
||||
};
|
||||
|
||||
pio: pinctrl@1001f000 {
|
||||
compatible = "mediatek,mt7988-pinctrl";
|
||||
compatible = "mediatek,mt7988-pinctrl", "syscon";
|
||||
reg = <0 0x1001f000 0 0x1000>,
|
||||
<0 0x11c10000 0 0x1000>,
|
||||
<0 0x11d00000 0 0x1000>,
|
||||
@ -303,11 +303,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
boottrap: boottrap@1001f6f0 {
|
||||
compatible = "mediatek,boottrap";
|
||||
reg = <0 0x1001f6f0 0 0x4>;
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@10060000 {
|
||||
compatible = "mediatek,mt7988-sgmiisys",
|
||||
"mediatek,mt7988-sgmiisys_0",
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -6,6 +6,8 @@
|
||||
include $(TOPDIR)/rules.mk
|
||||
include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
DEVICE_VARS += NETGEAR_ENC_MODEL NETGEAR_ENC_REGION NETGEAR_ENC_HW_ID_LIST NETGEAR_ENC_MODEL_LIST
|
||||
|
||||
loadaddr-$(CONFIG_TARGET_mediatek_mt7622) := 0x44000000
|
||||
loadaddr-$(CONFIG_TARGET_mediatek_mt7623) := 0x80008000
|
||||
loadaddr-$(CONFIG_TARGET_mediatek_mt7629) := 0x40008000
|
||||
@ -22,6 +24,10 @@ define Device/Default
|
||||
KERNEL_LOADADDR = $(loadaddr-y)
|
||||
FILESYSTEMS := squashfs
|
||||
DEVICE_DTS_DIR := $(DTS_DIR)
|
||||
NETGEAR_ENC_MODEL :=
|
||||
NETGEAR_ENC_REGION :=
|
||||
NETGEAR_ENC_HW_ID_LIST :=
|
||||
NETGEAR_ENC_MODEL_LIST :=
|
||||
IMAGES := sysupgrade.bin
|
||||
IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | \
|
||||
pad-rootfs | append-metadata
|
||||
|
||||
@ -22,3 +22,29 @@ define Device/iptime_a6004mx
|
||||
IMAGE/recovery.bin := append-kernel | pad-to 128k | append-ubi | append-metadata
|
||||
endef
|
||||
TARGET_DEVICES += iptime_a6004mx
|
||||
|
||||
define Device/netgear_ex6250-v2
|
||||
DEVICE_VENDOR := NETGEAR
|
||||
DEVICE_MODEL := EX6250
|
||||
DEVICE_VARIANT := v2
|
||||
DEVICE_ALT0_VENDOR := NETGEAR
|
||||
DEVICE_ALT0_MODEL := EX6400
|
||||
DEVICE_ALT0_VARIANT := v3
|
||||
DEVICE_ALT1_VENDOR := NETGEAR
|
||||
DEVICE_ALT1_MODEL := EX6410
|
||||
DEVICE_ALT1_VARIANT := v2
|
||||
DEVICE_ALT2_VENDOR := NETGEAR
|
||||
DEVICE_ALT2_MODEL := EX6470
|
||||
DEVICE_DTS := mt7629-netgear-ex6250-v2
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_PACKAGES := uboot-envtools
|
||||
NETGEAR_ENC_MODEL := EX6250v2
|
||||
NETGEAR_ENC_REGION := US
|
||||
NETGEAR_ENC_HW_ID_LIST := 1010000003630000_NETGEAR;1010000003540000_NETGEAR
|
||||
NETGEAR_ENC_MODEL_LIST := EX6250v2;EX6400v3;EX6470;EX6410v2
|
||||
IMAGE_SIZE := 13120k
|
||||
IMAGES += factory.img
|
||||
IMAGE/factory.img := append-kernel | pad-to 128k | append-rootfs | \
|
||||
pad-rootfs | check-size | netgear-encrypted-factory
|
||||
endef
|
||||
TARGET_DEVICES += netgear_ex6250-v2
|
||||
|
||||
@ -9,6 +9,10 @@ case $board in
|
||||
iptime,a6004mx)
|
||||
ucidef_set_led_netdev "wan" "WAN" "orange:wan" "eth1"
|
||||
;;
|
||||
netgear,ex6250-v2)
|
||||
ucidef_set_led_netdev "eth_act" "LAN act" "yellow:eth" "eth0" "tx rx"
|
||||
ucidef_set_led_netdev "eth_link" "LAN link" "green:eth" "eth0" "link"
|
||||
;;
|
||||
esac
|
||||
|
||||
board_config_flush
|
||||
|
||||
@ -16,6 +16,9 @@ mediatek_setup_interfaces()
|
||||
ucidef_add_switch "switch0" \
|
||||
"0:lan" "1:lan" "2:lan" "3:lan" "6@eth0"
|
||||
;;
|
||||
netgear,ex6250-v2)
|
||||
ucidef_set_interface_lan "eth0"
|
||||
;;
|
||||
esac
|
||||
}
|
||||
|
||||
@ -24,7 +27,15 @@ mediatek_setup_macs()
|
||||
local board="$1"
|
||||
|
||||
case $board in
|
||||
netgear,ex6250-v2)
|
||||
lan_mac=$(mtd_get_mac_ascii Config mac)
|
||||
label_mac=$lan_mac
|
||||
;;
|
||||
esac
|
||||
|
||||
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
|
||||
[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
|
||||
[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
|
||||
}
|
||||
|
||||
board_config_update
|
||||
|
||||
@ -1,82 +0,0 @@
|
||||
From 60ed9eb9605656c19ca402b7bd3f47552e901601 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Mon, 13 Feb 2023 02:33:14 +0000
|
||||
Subject: [PATCH] net: phy: add driver for MediaTek SoC built-in GE PHYs
|
||||
|
||||
Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet
|
||||
PHYs which require calibration data from the SoC's efuse.
|
||||
Despite the similar design the driver doesn't share any code with the
|
||||
existing mediatek-ge.c, so add support for these PHYs by introducing a
|
||||
new driver for only MediaTek's ARM64 SoCs.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
MAINTAINERS | 9 +
|
||||
drivers/net/phy/Kconfig | 12 +
|
||||
drivers/net/phy/Makefile | 1 +
|
||||
drivers/net/phy/mediatek-ge-soc.c | 1263 +++++++++++++++++++++++++++++
|
||||
drivers/net/phy/mediatek-ge.c | 3 +-
|
||||
5 files changed, 1287 insertions(+), 1 deletion(-)
|
||||
create mode 100644 drivers/net/phy/mediatek-ge-soc.c
|
||||
|
||||
--- a/MAINTAINERS
|
||||
+++ b/MAINTAINERS
|
||||
@@ -11790,6 +11790,15 @@ S: Maintained
|
||||
F: drivers/net/pcs/pcs-mtk-lynxi.c
|
||||
F: include/linux/pcs/pcs-mtk-lynxi.h
|
||||
|
||||
+MEDIATEK ETHERNET PHY DRIVERS
|
||||
+M: Daniel Golle <daniel@makrotopia.org>
|
||||
+M: Qingfang Deng <dqfext@gmail.com>
|
||||
+M: SkyLake Huang <SkyLake.Huang@mediatek.com>
|
||||
+L: netdev@vger.kernel.org
|
||||
+S: Maintained
|
||||
+F: drivers/net/phy/mediatek-ge-soc.c
|
||||
+F: drivers/net/phy/mediatek-ge.c
|
||||
+
|
||||
MEDIATEK I2C CONTROLLER DRIVER
|
||||
M: Qii Wang <qii.wang@mediatek.com>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
--- a/drivers/net/phy/Kconfig
|
||||
+++ b/drivers/net/phy/Kconfig
|
||||
@@ -292,6 +292,18 @@ config MEDIATEK_GE_PHY
|
||||
help
|
||||
Supports the MediaTek Gigabit Ethernet PHYs.
|
||||
|
||||
+config MEDIATEK_GE_SOC_PHY
|
||||
+ tristate "MediaTek SoC Ethernet PHYs"
|
||||
+ depends on (ARM64 && ARCH_MEDIATEK) || COMPILE_TEST
|
||||
+ select NVMEM_MTK_EFUSE
|
||||
+ help
|
||||
+ Supports MediaTek SoC built-in Gigabit Ethernet PHYs.
|
||||
+
|
||||
+ Include support for built-in Ethernet PHYs which are present in
|
||||
+ the MT7981 and MT7988 SoCs. These PHYs need calibration data
|
||||
+ present in the SoCs efuse and will dynamically calibrate VCM
|
||||
+ (common-mode voltage) during startup.
|
||||
+
|
||||
config MICREL_PHY
|
||||
tristate "Micrel PHYs"
|
||||
help
|
||||
--- a/drivers/net/phy/Makefile
|
||||
+++ b/drivers/net/phy/Makefile
|
||||
@@ -81,6 +81,7 @@ obj-$(CONFIG_MARVELL_PHY) += marvell.o
|
||||
obj-$(CONFIG_MARVELL_88X2222_PHY) += marvell-88x2222.o
|
||||
obj-$(CONFIG_MAXLINEAR_GPHY) += mxl-gpy.o
|
||||
obj-$(CONFIG_MEDIATEK_GE_PHY) += mediatek-ge.o
|
||||
+obj-$(CONFIG_MEDIATEK_GE_SOC_PHY) += mediatek-ge-soc.o
|
||||
obj-$(CONFIG_MESON_GXL_PHY) += meson-gxl.o
|
||||
obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
|
||||
obj-$(CONFIG_MICREL_PHY) += micrel.o
|
||||
--- a/drivers/net/phy/mediatek-ge.c
|
||||
+++ b/drivers/net/phy/mediatek-ge.c
|
||||
@@ -136,7 +136,8 @@ static struct phy_driver mtk_gephy_drive
|
||||
module_phy_driver(mtk_gephy_driver);
|
||||
|
||||
static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
|
||||
- { PHY_ID_MATCH_VENDOR(0x03a29400) },
|
||||
+ { PHY_ID_MATCH_EXACT(0x03a29441) },
|
||||
+ { PHY_ID_MATCH_EXACT(0x03a29412) },
|
||||
{ }
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,166 +0,0 @@
|
||||
--- a/drivers/net/phy/mxl-gpy.c
|
||||
+++ b/drivers/net/phy/mxl-gpy.c
|
||||
@@ -126,6 +126,12 @@ static int gpy_config_init(struct phy_de
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
+ /* Disable SGMII auto-negotiation */
|
||||
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
+ VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+
|
||||
return gpy_led_write(phydev);
|
||||
}
|
||||
|
||||
@@ -151,65 +157,6 @@ static int gpy_probe(struct phy_device *
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static bool gpy_sgmii_need_reaneg(struct phy_device *phydev)
|
||||
-{
|
||||
- int fw_ver, fw_type, fw_minor;
|
||||
- size_t i;
|
||||
-
|
||||
- fw_ver = phy_read(phydev, PHY_FWV);
|
||||
- if (fw_ver < 0)
|
||||
- return true;
|
||||
-
|
||||
- fw_type = FIELD_GET(PHY_FWV_TYPE_MASK, fw_ver);
|
||||
- fw_minor = FIELD_GET(PHY_FWV_MINOR_MASK, fw_ver);
|
||||
-
|
||||
- for (i = 0; i < ARRAY_SIZE(ver_need_sgmii_reaneg); i++) {
|
||||
- if (fw_type != ver_need_sgmii_reaneg[i].type)
|
||||
- continue;
|
||||
- if (fw_minor < ver_need_sgmii_reaneg[i].minor)
|
||||
- return true;
|
||||
- break;
|
||||
- }
|
||||
-
|
||||
- return false;
|
||||
-}
|
||||
-
|
||||
-static bool gpy_2500basex_chk(struct phy_device *phydev)
|
||||
-{
|
||||
- int ret;
|
||||
-
|
||||
- ret = phy_read(phydev, PHY_MIISTAT);
|
||||
- if (ret < 0) {
|
||||
- phydev_err(phydev, "Error: MDIO register access failed: %d\n",
|
||||
- ret);
|
||||
- return false;
|
||||
- }
|
||||
-
|
||||
- if (!(ret & PHY_MIISTAT_LS) ||
|
||||
- FIELD_GET(PHY_MIISTAT_SPD_MASK, ret) != PHY_MIISTAT_SPD_2500)
|
||||
- return false;
|
||||
-
|
||||
- phydev->speed = SPEED_2500;
|
||||
- phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
||||
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
- VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
- return true;
|
||||
-}
|
||||
-
|
||||
-static bool gpy_sgmii_aneg_en(struct phy_device *phydev)
|
||||
-{
|
||||
- int ret;
|
||||
-
|
||||
- ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL);
|
||||
- if (ret < 0) {
|
||||
- phydev_err(phydev, "Error: MMD register access failed: %d\n",
|
||||
- ret);
|
||||
- return true;
|
||||
- }
|
||||
-
|
||||
- return (ret & VSPEC1_SGMII_CTRL_ANEN) ? true : false;
|
||||
-}
|
||||
-
|
||||
static int gpy_config_aneg(struct phy_device *phydev)
|
||||
{
|
||||
bool changed = false;
|
||||
@@ -248,53 +195,11 @@ static int gpy_config_aneg(struct phy_de
|
||||
phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
|
||||
return 0;
|
||||
|
||||
- /* No need to trigger re-ANEG if link speed is 2.5G or SGMII ANEG is
|
||||
- * disabled.
|
||||
- */
|
||||
- if (!gpy_sgmii_need_reaneg(phydev) || gpy_2500basex_chk(phydev) ||
|
||||
- !gpy_sgmii_aneg_en(phydev))
|
||||
- return 0;
|
||||
-
|
||||
- /* There is a design constraint in GPY2xx device where SGMII AN is
|
||||
- * only triggered when there is change of speed. If, PHY link
|
||||
- * partner`s speed is still same even after PHY TPI is down and up
|
||||
- * again, SGMII AN is not triggered and hence no new in-band message
|
||||
- * from GPY to MAC side SGMII.
|
||||
- * This could cause an issue during power up, when PHY is up prior to
|
||||
- * MAC. At this condition, once MAC side SGMII is up, MAC side SGMII
|
||||
- * wouldn`t receive new in-band message from GPY with correct link
|
||||
- * status, speed and duplex info.
|
||||
- *
|
||||
- * 1) If PHY is already up and TPI link status is still down (such as
|
||||
- * hard reboot), TPI link status is polled for 4 seconds before
|
||||
- * retriggerring SGMII AN.
|
||||
- * 2) If PHY is already up and TPI link status is also up (such as soft
|
||||
- * reboot), polling of TPI link status is not needed and SGMII AN is
|
||||
- * immediately retriggered.
|
||||
- * 3) Other conditions such as PHY is down, speed change etc, skip
|
||||
- * retriggering SGMII AN. Note: in case of speed change, GPY FW will
|
||||
- * initiate SGMII AN.
|
||||
- */
|
||||
-
|
||||
- if (phydev->state != PHY_UP)
|
||||
- return 0;
|
||||
-
|
||||
- ret = phy_read_poll_timeout(phydev, MII_BMSR, ret, ret & BMSR_LSTATUS,
|
||||
- 20000, 4000000, false);
|
||||
- if (ret == -ETIMEDOUT)
|
||||
- return 0;
|
||||
- else if (ret < 0)
|
||||
- return ret;
|
||||
-
|
||||
- /* Trigger SGMII AN. */
|
||||
- return phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
- VSPEC1_SGMII_CTRL_ANRS, VSPEC1_SGMII_CTRL_ANRS);
|
||||
+ return 0;
|
||||
}
|
||||
|
||||
static void gpy_update_interface(struct phy_device *phydev)
|
||||
{
|
||||
- int ret;
|
||||
-
|
||||
/* Interface mode is fixed for USXGMII and integrated PHY */
|
||||
if (phydev->interface == PHY_INTERFACE_MODE_USXGMII ||
|
||||
phydev->interface == PHY_INTERFACE_MODE_INTERNAL)
|
||||
@@ -306,29 +211,11 @@ static void gpy_update_interface(struct
|
||||
switch (phydev->speed) {
|
||||
case SPEED_2500:
|
||||
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
||||
- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
- VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
- if (ret < 0)
|
||||
- phydev_err(phydev,
|
||||
- "Error: Disable of SGMII ANEG failed: %d\n",
|
||||
- ret);
|
||||
break;
|
||||
case SPEED_1000:
|
||||
case SPEED_100:
|
||||
case SPEED_10:
|
||||
phydev->interface = PHY_INTERFACE_MODE_SGMII;
|
||||
- if (gpy_sgmii_aneg_en(phydev))
|
||||
- break;
|
||||
- /* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
|
||||
- * if ANEG is disabled (in 2500-BaseX mode).
|
||||
- */
|
||||
- ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
- VSPEC1_SGMII_ANEN_ANRS,
|
||||
- VSPEC1_SGMII_ANEN_ANRS);
|
||||
- if (ret < 0)
|
||||
- phydev_err(phydev,
|
||||
- "Error: Enable of SGMII ANEG failed: %d\n",
|
||||
- ret);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -0,0 +1,213 @@
|
||||
From 5d2d78860f98eb5c03bc404eb024606878901ac8 Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Tue, 13 Jun 2023 03:27:14 +0100
|
||||
Subject: [PATCH] net: phy: mediatek-ge-soc: initialize MT7988 PHY LEDs default
|
||||
state
|
||||
|
||||
Initialize LEDs and set sane default values.
|
||||
Read boottrap register and apply LED polarities accordingly to get
|
||||
uniform behavior from all LEDs on MT7988.
|
||||
Requires syscon phandle 'mediatek,pio' present in parenting MDIO bus
|
||||
which should point to the syscon holding the boottrap register.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/net/phy/mediatek-ge-soc.c | 144 ++++++++++++++++++++++++++++--
|
||||
1 file changed, 136 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/net/phy/mediatek-ge-soc.c
|
||||
+++ b/drivers/net/phy/mediatek-ge-soc.c
|
||||
@@ -1,11 +1,13 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
#include <linux/bitfield.h>
|
||||
+#include <linux/mfd/syscon.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/nvmem-consumer.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/phy.h>
|
||||
+#include <linux/regmap.h>
|
||||
|
||||
#define MTK_GPHY_ID_MT7981 0x03a29461
|
||||
#define MTK_GPHY_ID_MT7988 0x03a29481
|
||||
@@ -208,9 +210,40 @@
|
||||
#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f
|
||||
#define MTK_PHY_DA_TX_R50_PAIR_D 0x540
|
||||
|
||||
+/* Registers on MDIO_MMD_VEND2 */
|
||||
+#define MTK_PHY_LED0_ON_CTRL 0x24
|
||||
+#define MTK_PHY_LED1_ON_CTRL 0x26
|
||||
+#define MTK_PHY_LED_ON_MASK GENMASK(6, 0)
|
||||
+#define MTK_PHY_LED_ON_LINK1000 BIT(0)
|
||||
+#define MTK_PHY_LED_ON_LINK100 BIT(1)
|
||||
+#define MTK_PHY_LED_ON_LINK10 BIT(2)
|
||||
+#define MTK_PHY_LED_ON_LINKDOWN BIT(3)
|
||||
+#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */
|
||||
+#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */
|
||||
+#define MTK_PHY_LED_FORCE_ON BIT(6)
|
||||
+#define MTK_PHY_LED_POLARITY BIT(14)
|
||||
+#define MTK_PHY_LED_ENABLE BIT(15)
|
||||
+
|
||||
+#define MTK_PHY_LED0_BLINK_CTRL 0x25
|
||||
+#define MTK_PHY_LED1_BLINK_CTRL 0x27
|
||||
+#define MTK_PHY_LED_1000TX BIT(0)
|
||||
+#define MTK_PHY_LED_1000RX BIT(1)
|
||||
+#define MTK_PHY_LED_100TX BIT(2)
|
||||
+#define MTK_PHY_LED_100RX BIT(3)
|
||||
+#define MTK_PHY_LED_10TX BIT(4)
|
||||
+#define MTK_PHY_LED_10RX BIT(5)
|
||||
+#define MTK_PHY_LED_COLLISION BIT(6)
|
||||
+#define MTK_PHY_LED_RX_CRC_ERR BIT(7)
|
||||
+#define MTK_PHY_LED_RX_IDLE_ERR BIT(8)
|
||||
+#define MTK_PHY_LED_FORCE_BLINK BIT(9)
|
||||
+
|
||||
#define MTK_PHY_RG_BG_RASEL 0x115
|
||||
#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0)
|
||||
|
||||
+/* Register in boottrap syscon defining the initial state of the 4 PHY LEDs */
|
||||
+#define RG_GPIO_MISC_TPBANK0 0x6f0
|
||||
+#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8)
|
||||
+
|
||||
/* These macro privides efuse parsing for internal phy. */
|
||||
#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0))
|
||||
#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0))
|
||||
@@ -238,13 +271,6 @@ enum {
|
||||
PAIR_D,
|
||||
};
|
||||
|
||||
-enum {
|
||||
- GPHY_PORT0,
|
||||
- GPHY_PORT1,
|
||||
- GPHY_PORT2,
|
||||
- GPHY_PORT3,
|
||||
-};
|
||||
-
|
||||
enum calibration_mode {
|
||||
EFUSE_K,
|
||||
SW_K
|
||||
@@ -263,6 +289,10 @@ enum CAL_MODE {
|
||||
SW_M
|
||||
};
|
||||
|
||||
+struct mtk_socphy_shared {
|
||||
+ u32 boottrap;
|
||||
+};
|
||||
+
|
||||
static int mtk_socphy_read_page(struct phy_device *phydev)
|
||||
{
|
||||
return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
|
||||
@@ -1073,6 +1103,104 @@ static int mt798x_phy_config_init(struct
|
||||
return mt798x_phy_calibration(phydev);
|
||||
}
|
||||
|
||||
+static int mt798x_phy_setup_led(struct phy_device *phydev, bool inverted)
|
||||
+{
|
||||
+ struct pinctrl *pinctrl;
|
||||
+ const u16 led_on_ctrl_defaults = MTK_PHY_LED_ENABLE |
|
||||
+ MTK_PHY_LED_ON_LINK1000 |
|
||||
+ MTK_PHY_LED_ON_LINK100 |
|
||||
+ MTK_PHY_LED_ON_LINK10;
|
||||
+ const u16 led_blink_defaults = MTK_PHY_LED_1000TX |
|
||||
+ MTK_PHY_LED_1000RX |
|
||||
+ MTK_PHY_LED_100TX |
|
||||
+ MTK_PHY_LED_100RX |
|
||||
+ MTK_PHY_LED_10TX |
|
||||
+ MTK_PHY_LED_10RX;
|
||||
+
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
|
||||
+ led_on_ctrl_defaults ^
|
||||
+ (inverted ? MTK_PHY_LED_POLARITY : 0));
|
||||
+
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
|
||||
+ led_on_ctrl_defaults);
|
||||
+
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
|
||||
+ led_blink_defaults);
|
||||
+
|
||||
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
|
||||
+ led_blink_defaults);
|
||||
+
|
||||
+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led");
|
||||
+ if (IS_ERR(pinctrl))
|
||||
+ dev_err(&phydev->mdio.bus->dev, "Failed to setup PHY LED\n");
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int mt7988_phy_probe_shared(struct phy_device *phydev)
|
||||
+{
|
||||
+ struct device_node *np = dev_of_node(&phydev->mdio.bus->dev);
|
||||
+ struct mtk_socphy_shared *priv = phydev->shared->priv;
|
||||
+ struct regmap *regmap;
|
||||
+ u32 reg;
|
||||
+ int ret;
|
||||
+
|
||||
+ /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B,
|
||||
+ * LED_C and LED_D respectively. At the same time those pins are used to
|
||||
+ * bootstrap configuration of the reference clock source (LED_A),
|
||||
+ * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D).
|
||||
+ * In practise this is done using a LED and a resistor pulling the pin
|
||||
+ * either to GND or to VIO.
|
||||
+ * The detected value at boot time is accessible at run-time using the
|
||||
+ * TPBANK0 register located in the gpio base of the pinctrl, in order
|
||||
+ * to read it here it needs to be referenced by a phandle called
|
||||
+ * 'mediatek,pio' in the MDIO bus hosting the PHY.
|
||||
+ * The 4 bits in TPBANK0 are kept as package shared data and are used to
|
||||
+ * set LED polarity for each of the LED0.
|
||||
+ */
|
||||
+ regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,pio");
|
||||
+ if (IS_ERR(regmap))
|
||||
+ return PTR_ERR(regmap);
|
||||
+
|
||||
+ ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ priv->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static bool mt7988_phy_get_boottrap_polarity(struct phy_device *phydev)
|
||||
+{
|
||||
+ struct mtk_socphy_shared *priv = phydev->shared->priv;
|
||||
+
|
||||
+ if (priv->boottrap & BIT(phydev->mdio.addr))
|
||||
+ return false;
|
||||
+
|
||||
+ return true;
|
||||
+}
|
||||
+
|
||||
+static int mt7988_phy_probe(struct phy_device *phydev)
|
||||
+{
|
||||
+ int err;
|
||||
+
|
||||
+ err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0,
|
||||
+ sizeof(struct mtk_socphy_shared));
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ if (phy_package_probe_once(phydev)) {
|
||||
+ err = mt7988_phy_probe_shared(phydev);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+ }
|
||||
+
|
||||
+ mt798x_phy_setup_led(phydev, mt7988_phy_get_boottrap_polarity(phydev));
|
||||
+
|
||||
+ return mt798x_phy_calibration(phydev);
|
||||
+}
|
||||
+
|
||||
static struct phy_driver mtk_socphy_driver[] = {
|
||||
{
|
||||
PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981),
|
||||
@@ -1092,7 +1220,7 @@ static struct phy_driver mtk_socphy_driv
|
||||
.config_init = mt798x_phy_config_init,
|
||||
.config_intr = genphy_no_config_intr,
|
||||
.handle_interrupt = genphy_handle_interrupt_no_ack,
|
||||
- .probe = mt798x_phy_calibration,
|
||||
+ .probe = mt7988_phy_probe,
|
||||
.suspend = genphy_suspend,
|
||||
.resume = genphy_resume,
|
||||
.read_page = mtk_socphy_read_page,
|
||||
@ -0,0 +1,63 @@
|
||||
From a969b663c866129ed9eb217785a6574fbe826f1d Mon Sep 17 00:00:00 2001
|
||||
From: Daniel Golle <daniel@makrotopia.org>
|
||||
Date: Thu, 6 Apr 2023 23:36:50 +0100
|
||||
Subject: [PATCH] net: phy: mxl-gpy: don't use SGMII AN if using phylink
|
||||
|
||||
MAC drivers using phylink expect SGMII in-band-status to be switched off
|
||||
when attached to a PHY. Make sure this is the case also for mxl-gpy which
|
||||
keeps SGMII in-band-status in case of SGMII interface mode is used.
|
||||
|
||||
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
||||
---
|
||||
drivers/net/phy/mxl-gpy.c | 19 ++++++++++++++++---
|
||||
1 file changed, 16 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/net/phy/mxl-gpy.c
|
||||
+++ b/drivers/net/phy/mxl-gpy.c
|
||||
@@ -191,8 +191,11 @@ static bool gpy_2500basex_chk(struct phy
|
||||
|
||||
phydev->speed = SPEED_2500;
|
||||
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
||||
- phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
- VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
+
|
||||
+ if (!phydev->phylink)
|
||||
+ phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
+ VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
+
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -216,6 +219,14 @@ static int gpy_config_aneg(struct phy_de
|
||||
u32 adv;
|
||||
int ret;
|
||||
|
||||
+ /* Disable SGMII auto-negotiation if using phylink */
|
||||
+ if (phydev->phylink) {
|
||||
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
+ VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
+ if (ret < 0)
|
||||
+ return ret;
|
||||
+ }
|
||||
+
|
||||
if (phydev->autoneg == AUTONEG_DISABLE) {
|
||||
/* Configure half duplex with genphy_setup_forced,
|
||||
* because genphy_c45_pma_setup_forced does not support.
|
||||
@@ -306,6 +317,8 @@ static void gpy_update_interface(struct
|
||||
switch (phydev->speed) {
|
||||
case SPEED_2500:
|
||||
phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
|
||||
+ if (phydev->phylink)
|
||||
+ break;
|
||||
ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, VSPEC1_SGMII_CTRL,
|
||||
VSPEC1_SGMII_CTRL_ANEN, 0);
|
||||
if (ret < 0)
|
||||
@@ -317,7 +330,7 @@ static void gpy_update_interface(struct
|
||||
case SPEED_100:
|
||||
case SPEED_10:
|
||||
phydev->interface = PHY_INTERFACE_MODE_SGMII;
|
||||
- if (gpy_sgmii_aneg_en(phydev))
|
||||
+ if (phydev->phylink || gpy_sgmii_aneg_en(phydev))
|
||||
break;
|
||||
/* Enable and restart SGMII ANEG for 10/100/1000Mbps link speed
|
||||
* if ANEG is disabled (in 2500-BaseX mode).
|
||||
@ -7,6 +7,7 @@ include $(INCLUDE_DIR)/image.mk
|
||||
|
||||
DEVICE_VARS += LOADER_TYPE LOADER_FLASH_OFFS LZMA_TEXT_START
|
||||
DEVICE_VARS += NETGEAR_BOARD_ID NETGEAR_HW_ID
|
||||
DEVICE_VARS += NETGEAR_ENC_MODEL NETGEAR_ENC_REGION NETGEAR_ENC_HW_ID_LIST NETGEAR_ENC_MODEL_LIST
|
||||
DEVICE_VARS += BUFFALO_TAG_PLATFORM BUFFALO_TAG_VERSION BUFFALO_TAG_MINOR
|
||||
DEVICE_VARS += SEAMA_SIGNATURE SEAMA_MTDBLOCK
|
||||
DEVICE_VARS += SERCOMM_HWNAME SERCOMM_HWID SERCOMM_HWVER SERCOMM_SWVER
|
||||
@ -179,6 +180,10 @@ define Device/Default
|
||||
SOC := $(DEFAULT_SOC)
|
||||
DEVICE_DTS_DIR := ../dts
|
||||
DEVICE_DTS = $$(SOC)_$(1)
|
||||
NETGEAR_ENC_MODEL :=
|
||||
NETGEAR_ENC_REGION :=
|
||||
NETGEAR_ENC_HW_ID_LIST :=
|
||||
NETGEAR_ENC_MODEL_LIST :=
|
||||
IMAGES := sysupgrade.bin
|
||||
COMPILE :=
|
||||
sysupgrade_bin := append-kernel | append-rootfs | pad-rootfs
|
||||
|
||||
Loading…
Reference in New Issue
Block a user