496436c0e0
Copy patches and config from 5.15 kernel version. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
115 lines
3.7 KiB
Diff
115 lines
3.7 KiB
Diff
From eefc791ec8040d6cacf3e940d778b7fc82c5e99e Mon Sep 17 00:00:00 2001
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From: YouMin Chen <cym@rock-chips.com>
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Date: Mon, 5 Feb 2018 10:57:23 +0800
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Subject: [PATCH] PM / devfreq: event: add support for px30 dfi
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Change-Id: Ib6808d961b65d993fea05ab15d648d814d14a4a2
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Signed-off-by: YouMin Chen <cym@rock-chips.com>
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---
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.../bindings/devfreq/event/rockchip-dfi.txt | 1 +
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drivers/devfreq/event/rockchip-dfi.c | 41 +++++++++++++++++--
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2 files changed, 39 insertions(+), 3 deletions(-)
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--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
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+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
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@@ -3,6 +3,7 @@
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Required properties:
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- compatible: Should be one of the following.
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+ - "rockchip,px30-dfi" - for PX30 SoCs.
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- "rockchip,rk3128-dfi" - for RK3128 SoCs.
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- "rockchip,rk3288-dfi" - for RK3288 SoCs.
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- "rockchip,rk3328-dfi" - for RK3328 SoCs.
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--- a/drivers/devfreq/event/rockchip-dfi.c
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+++ b/drivers/devfreq/event/rockchip-dfi.c
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@@ -20,6 +20,8 @@
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#include <soc/rockchip/rk3399_grf.h>
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+#define PX30_PMUGRF_OS_REG2 0x208
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+
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#define RK3128_GRF_SOC_CON0 0x140
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#define RK3128_GRF_OS_REG1 0x1cc
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#define RK3128_GRF_DFI_WRNUM 0x220
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@@ -56,7 +58,7 @@
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#define DDR4_EN (0x10001 << 5)
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#define LPDDR4_EN (0x10001 << 4)
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#define HARDWARE_EN (0x10001 << 3)
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-#define LPDDR3_EN (0x10001 << 2)
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+#define LPDDR2_3_EN (0x10001 << 2)
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#define SOFTWARE_EN (0x10001 << 1)
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#define SOFTWARE_DIS (0x10000 << 1)
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#define TIME_CNT_EN (0x10001 << 0)
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@@ -72,6 +74,7 @@
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enum {
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DDR4 = 0,
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DDR3 = 3,
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+ LPDDR2 = 5,
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LPDDR3 = 6,
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LPDDR4 = 7,
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UNUSED = 0xFF
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@@ -95,6 +98,7 @@ struct rockchip_dfi {
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void __iomem *regs;
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struct regmap *regmap_pmu;
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struct regmap *regmap_grf;
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+ struct regmap *regmap_pmugrf;
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struct clk *clk;
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u32 dram_type;
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/*
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@@ -338,8 +342,8 @@ static void rockchip_dfi_start_hardware_
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writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
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/* set ddr type to dfi */
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- if (info->dram_type == LPDDR3)
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- writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
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+ if (info->dram_type == LPDDR3 || info->dram_type == LPDDR2)
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+ writel_relaxed(LPDDR2_3_EN, dfi_regs + DDRMON_CTRL);
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else if (info->dram_type == LPDDR4)
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writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
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else if (info->dram_type == DDR4)
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@@ -443,6 +447,36 @@ static const struct devfreq_event_ops ro
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.set_event = rockchip_dfi_set_event,
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};
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+static __init int px30_dfi_init(struct platform_device *pdev,
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+ struct rockchip_dfi *data,
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+ struct devfreq_event_desc *desc)
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+{
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+ struct device_node *np = pdev->dev.of_node, *node;
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+ struct resource *res;
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+ u32 val;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ data->regs = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(data->regs))
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+ return PTR_ERR(data->regs);
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+
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+ node = of_parse_phandle(np, "rockchip,pmugrf", 0);
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+ if (node) {
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+ data->regmap_pmugrf = syscon_node_to_regmap(node);
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+ if (IS_ERR(data->regmap_pmugrf))
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+ return PTR_ERR(data->regmap_pmugrf);
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+ }
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+
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+ regmap_read(data->regmap_pmugrf, PX30_PMUGRF_OS_REG2, &val);
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+ data->dram_type = READ_DRAMTYPE_INFO(val);
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+ data->ch_msk = 1;
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+ data->clk = NULL;
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+
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+ desc->ops = &rockchip_dfi_ops;
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+
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+ return 0;
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+}
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+
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static __init int rk3128_dfi_init(struct platform_device *pdev,
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struct rockchip_dfi *data,
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struct devfreq_event_desc *desc)
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@@ -583,6 +617,7 @@ static __init int rk3328_dfi_init(struct
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}
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static const struct of_device_id rockchip_dfi_id_match[] = {
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+ { .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
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{ .compatible = "rockchip,rk3128-dfi", .data = rk3128_dfi_init },
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{ .compatible = "rockchip,rk3288-dfi", .data = rk3288_dfi_init },
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{ .compatible = "rockchip,rk3328-dfi", .data = rk3328_dfi_init },
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