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uboot-rockchip: initial rk3568 support

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2022-11-01 16:56:11 +08:00
parent f3da7ddae2
commit 7459187f3b
No known key found for this signature in database
GPG Key ID: 6850B6345C862176
11 changed files with 4028 additions and 0 deletions
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2839
package/boot/uboot-rockchip/patches/010-arm-dts-rockchip-rk356x-sync-with-Linux-6.0.patch Normal file
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43
package/boot/uboot-rockchip/patches/100-clk-rockchip-rk3568-fix-reset-handler.patch Normal file
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@ -0,0 +1,43 @@
From: Peter Geis <pgwipeout@gmail.com>
To: Simon Glass <sjg@chromium.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Kever Yang <kever.yang@rock-chips.com>,
Lukasz Majewski <lukma@denx.de>,
Sean Anderson <seanga2@gmail.com>,
Elaine Zhang <zhangqing@rock-chips.com>
Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
Subject: [PATCH v1 01/11] clk: rockchip: rk3568: fix reset handler
Date: Mon, 21 Feb 2022 20:31:20 -0500 [thread overview]
Message-ID: <20220222013131.3114990-2-pgwipeout@gmail.com> (raw)
In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com>
The reset handler for rk3568 is missing its private data. This leads to
an abort when a reset is triggered.
Add the missing dev_set_priv to the rk3568 clk driver.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
drivers/clk/rockchip/clk_rk3568.c | 2 ++
1 file changed, 2 insertions(+)
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -14,6 +14,7 @@
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
+#include <dm/device-internal.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3568-cru.h>
@@ -2934,6 +2935,7 @@ static int rk3568_clk_bind(struct udevic
glb_srst_fst);
priv->glb_srst_snd_value = offsetof(struct rk3568_cru,
glb_srsr_snd);
+ dev_set_priv(sys_child, priv);
}
#if CONFIG_IS_ENABLED(RESET_ROCKCHIP)

40
package/boot/uboot-rockchip/patches/101-spl-support-adc-drivers-in-spl.patch Normal file
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@ -0,0 +1,40 @@
From: Peter Geis <pgwipeout@gmail.com>
Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
Subject: [PATCH v1 05/11] spl: support adc drivers in spl
Date: Mon, 21 Feb 2022 20:31:24 -0500 [thread overview]
Message-ID: <20220222013131.3114990-6-pgwipeout@gmail.com> (raw)
In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com>
In order to handle the rockchip recovery handler in spl, we need the adc
code to be available in spl.
Add a toggle to allow adc drivers to function in spl.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
common/spl/Kconfig | 5 +++++
drivers/Makefile | 1 +
2 files changed, 6 insertions(+)
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -578,6 +578,11 @@ config SPL_FIT_IMAGE_TINY
ensure this information is available to the next image
invoked).
+config SPL_ADC
+ bool "Support ADC drivers in SPL"
+ help
+ Enable ADC drivers in SPL.
+
config SPL_CACHE
bool "Support CACHE drivers"
help
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
+obj-$(CONFIG_$(SPL_)ADC) += adc/
obj-$(CONFIG_$(SPL_TPL_)BOOTCOUNT_LIMIT) += bootcount/
obj-$(CONFIG_$(SPL_TPL_)BUTTON) += button/
obj-$(CONFIG_$(SPL_TPL_)CACHE) += cache/

95
package/boot/uboot-rockchip/patches/102-rockchip-handle-bootrom-recovery-mode-in-spl.patch Normal file
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@ -0,0 +1,95 @@
From: Peter Geis <pgwipeout@gmail.com>
To: Simon Glass <sjg@chromium.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Kever Yang <kever.yang@rock-chips.com>
Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
Subject: [PATCH v1 06/11] rockchip: handle bootrom recovery mode in spl
Date: Mon, 21 Feb 2022 20:31:25 -0500 [thread overview]
Message-ID: <20220222013131.3114990-7-pgwipeout@gmail.com> (raw)
In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com>
Fixup the bootrom recovery mode code to function in spl, so we can
handle recovery mode in case u-boot loading is broken.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/Makefile | 6 +++---
arch/arm/mach-rockchip/boot_mode.c | 4 +++-
arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++
3 files changed, 29 insertions(+), 4 deletions(-)
--- a/arch/arm/mach-rockchip/Makefile
+++ b/arch/arm/mach-rockchip/Makefile
@@ -15,13 +15,13 @@ obj-tpl-$(CONFIG_ROCKCHIP_PX30) += px30-
obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
-
# Always include boot_mode.o, as we bypass it (i.e. turn it off)
# inside of boot_mode.c when CONFIG_BOOT_MODE_REG is 0. This way,
# we can have the preprocessor correctly recognise both 0x0 and 0
# meaning "turn it off".
-obj-y += boot_mode.o
+obj-$(CONFIG_ARCH_ROCKCHIP) += boot_mode.o
+
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),)
obj-$(CONFIG_ROCKCHIP_COMMON_BOARD) += board.o
obj-$(CONFIG_MISC_INIT_R) += misc.o
endif
--- a/arch/arm/mach-rockchip/boot_mode.c
+++ b/arch/arm/mach-rockchip/boot_mode.c
@@ -51,7 +51,7 @@ __weak int rockchip_dnl_key_pressed(void
ret = -ENODEV;
uclass_foreach_dev(dev, uc) {
if (!strncmp(dev->name, "saradc", 6)) {
- ret = adc_channel_single_shot(dev->name, 1, &val);
+ ret = adc_channel_single_shot(dev->name, 0, &val);
break;
}
}
@@ -89,6 +89,7 @@ int setup_boot_mode(void)
boot_mode = readl(reg);
debug("%s: boot mode 0x%08x\n", __func__, boot_mode);
+#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
/* Clear boot mode */
writel(BOOT_NORMAL, reg);
@@ -102,6 +103,7 @@ int setup_boot_mode(void)
env_set("preboot", "setenv preboot; ums mmc 0");
break;
}
+#endif
return 0;
}
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -104,3 +104,26 @@ int arch_cpu_init(void)
#endif
return 0;
}
+
+#ifdef CONFIG_SPL_BUILD
+
+void __weak led_setup(void)
+{
+}
+
+void spl_board_init(void)
+{
+ led_setup();
+
+#if (CONFIG_IS_ENABLED(DM_REGULATOR))
+ /*
+ * Turning the eMMC and SPI back on (if disabled via the Qseven
+ * BIOS_ENABLE) signal is done through a always-on regulator).
+ */
+ if (regulators_enable_boot_on(false))
+ debug("%s: Cannot enable boot on regulator\n", __func__);
+#endif
+
+ setup_boot_mode();
+}
+#endif

48
package/boot/uboot-rockchip/patches/103-rockchip-rk3568-add-boot-device-detection.patch Normal file
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@ -0,0 +1,48 @@
From: Peter Geis <pgwipeout@gmail.com>
To: Simon Glass <sjg@chromium.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Kever Yang <kever.yang@rock-chips.com>
Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
Subject: [PATCH v1 07/11] rockchip: rk3568: add boot device detection
Date: Mon, 21 Feb 2022 20:31:26 -0500 [thread overview]
Message-ID: <20220222013131.3114990-8-pgwipeout@gmail.com> (raw)
In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com>
Enable rk3568 spl to detect which device it was booted from.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 8 ++++++++
1 file changed, 8 insertions(+)
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/grf_rk3568.h>
#include <asm/arch-rockchip/hardware.h>
#include <dt-bindings/clock/rk3568-cru.h>
@@ -23,6 +24,7 @@
#define SGRF_SOC_CON4 0x10
#define EMMC_HPROT_SECURE_CTRL 0x03
#define SDMMC0_HPROT_SECURE_CTRL 0x01
+
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
@@ -43,6 +45,12 @@ enum {
UART2_IO_SEL_M0 = 0,
};
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe310000",
+ [BROM_BOOTSOURCE_SPINOR] = "/spi@fe300000/flash@0",
+ [BROM_BOOTSOURCE_SD] = "/mmc@fe2b0000",
+};
+
static struct mm_region rk3568_mem_map[] = {
{
.virt = 0x0UL,

57
package/boot/uboot-rockchip/patches/104-rockchip-rk3568-enable-automatic-clock-gating.patch Normal file
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@ -0,0 +1,57 @@
From: Peter Geis <pgwipeout@gmail.com>
To: Simon Glass <sjg@chromium.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Kever Yang <kever.yang@rock-chips.com>
Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
Subject: [PATCH v1 08/11] rockchip: rk3568: enable automatic clock gating
Date: Mon, 21 Feb 2022 20:31:27 -0500 [thread overview]
Message-ID: <20220222013131.3114990-9-pgwipeout@gmail.com> (raw)
In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com>
Enable automatic clock gating on rk3568, which solves a 7c temperature
difference on SoQuartz compared to downstream.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -25,6 +25,15 @@
#define EMMC_HPROT_SECURE_CTRL 0x03
#define SDMMC0_HPROT_SECURE_CTRL 0x01
+#define PMU_BASE_ADDR 0xfdd90000
+#define PMU_NOC_AUTO_CON0 (0x70)
+#define PMU_NOC_AUTO_CON1 (0x74)
+#define EDP_PHY_GRF_BASE 0xfdcb0000
+#define EDP_PHY_GRF_CON0 (EDP_PHY_GRF_BASE + 0x00)
+#define EDP_PHY_GRF_CON10 (EDP_PHY_GRF_BASE + 0x28)
+#define CPU_GRF_BASE 0xfdc30000
+#define GRF_CORE_PVTPLL_CON0 (0x10)
+
/* PMU_GRF_GPIO0D_IOMUX_L */
enum {
GPIO0D1_SHIFT = 4,
@@ -99,6 +108,20 @@ void board_debug_uart_init(void)
int arch_cpu_init(void)
{
#ifdef CONFIG_SPL_BUILD
+ /*
+ * When perform idle operation, corresponding clock can
+ * be opened or gated automatically.
+ */
+ writel(0xffffffff, PMU_BASE_ADDR + PMU_NOC_AUTO_CON0);
+ writel(0x000f000f, PMU_BASE_ADDR + PMU_NOC_AUTO_CON1);
+
+ /* Disable eDP phy by default */
+ writel(0x00070007, EDP_PHY_GRF_CON10);
+ writel(0x0ff10ff1, EDP_PHY_GRF_CON0);
+
+ /* Set core pvtpll ring length */
+ writel(0x00ff002b, CPU_GRF_BASE + GRF_CORE_PVTPLL_CON0);
+
/* Set the emmc sdmmc0 to secure */
rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
| SDMMC0_HPROT_SECURE_CTRL << 4));

87
package/boot/uboot-rockchip/patches/105-rockchip-move-dwc3-config-to-chip-specific-handler.patch Normal file
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@ -0,0 +1,87 @@
From: Peter Geis <pgwipeout@gmail.com>
To: Simon Glass <sjg@chromium.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Kever Yang <kever.yang@rock-chips.com>
Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
Subject: [PATCH v1 09/11] rockchip: move dwc3 config to chip specific handler
Date: Mon, 21 Feb 2022 20:31:28 -0500 [thread overview]
Message-ID: <20220222013131.3114990-10-pgwipeout@gmail.com> (raw)
In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com>
The dwc3 code in the mach-rockchip board file is specific to the rk3399.
Move it to the rk3399 chip specific code.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/board.c | 24 ---------------------
arch/arm/mach-rockchip/rk3399/rk3399.c | 29 ++++++++++++++++++++++++++
2 files changed, 29 insertions(+), 24 deletions(-)
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -127,30 +127,6 @@ int board_usb_cleanup(int index, enum us
}
#endif /* CONFIG_USB_GADGET_DWC2_OTG */
-#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
-#include <dwc3-uboot.h>
-
-static struct dwc3_device dwc3_device_data = {
- .maximum_speed = USB_SPEED_HIGH,
- .base = 0xfe800000,
- .dr_mode = USB_DR_MODE_PERIPHERAL,
- .index = 0,
- .dis_u2_susphy_quirk = 1,
- .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
-};
-
-int usb_gadget_handle_interrupts(int index)
-{
- dwc3_uboot_handle_interrupt(0);
- return 0;
-}
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- return dwc3_uboot_init(&dwc3_device_data);
-}
-#endif /* CONFIG_USB_DWC3_GADGET */
-
#endif /* CONFIG_USB_GADGET */
#if CONFIG_IS_ENABLED(FASTBOOT)
--- a/arch/arm/mach-rockchip/rk3399/rk3399.c
+++ b/arch/arm/mach-rockchip/rk3399/rk3399.c
@@ -285,3 +285,32 @@ void spl_board_init(void)
#endif
}
#endif
+
+#if defined(CONFIG_USB_GADGET)
+#include <usb.h>
+
+#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
+#include <dwc3-uboot.h>
+
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = 0xfe800000,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+ .dis_u2_susphy_quirk = 1,
+ .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return dwc3_uboot_init(&dwc3_device_data);
+}
+#endif /* CONFIG_USB_DWC3_GADGET */
+
+#endif /* CONFIG_USB_GADGET */

53
package/boot/uboot-rockchip/patches/106-rockchip-rk3568-add-dwc3-otg-support.patch Normal file
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@ -0,0 +1,53 @@
From: Peter Geis <pgwipeout@gmail.com>
To: Simon Glass <sjg@chromium.org>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Kever Yang <kever.yang@rock-chips.com>
Cc: Peter Geis <pgwipeout@gmail.com>, u-boot@lists.denx.de
Subject: [PATCH v1 10/11] rockchip: rk3568: add dwc3 otg support
Date: Mon, 21 Feb 2022 20:31:29 -0500 [thread overview]
Message-ID: <20220222013131.3114990-11-pgwipeout@gmail.com> (raw)
In-Reply-To: <20220222013131.3114990-1-pgwipeout@gmail.com>
Add the required platform data to the rk3568 chip config, in order to
support dwc3 otg on this chip.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
--- a/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -158,3 +158,32 @@ void spl_board_init(void)
setup_boot_mode();
}
#endif
+
+#if defined(CONFIG_USB_GADGET)
+#include <usb.h>
+
+#if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
+#include <dwc3-uboot.h>
+
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = 0xfcc00000,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+ .dis_u2_susphy_quirk = 1,
+ .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
+};
+
+int usb_gadget_handle_interrupts(int index)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return dwc3_uboot_init(&dwc3_device_data);
+}
+#endif /* CONFIG_USB_DWC3_GADGET */
+
+#endif /* CONFIG_USB_GADGET */

755
package/boot/uboot-rockchip/patches/107-gpio-rockchip-rk_gpio-support-v2-gpio-controller.patch.patch Normal file
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@ -0,0 +1,755 @@
From 3a4d973a743bc76cc734db9616f9053f45fa922f Mon Sep 17 00:00:00 2001
From: Jianqun Xu <jay.xu@rock-chips.com>
Date: Thu, 28 May 2020 11:01:58 +0800
Subject: [PATCH 07/11] gpio/rockchip: rk_gpio support v2 gpio controller
The v2 gpio controller add write enable bit for some register,
such as data register, data direction register and so on.
This patch support v2 gpio controller by redefine the read and
write operation functions.
Also adds support for the rk3568 pinctrl device.
Squash all fixes into this commit.
Change-Id: I2adbcca06a37c48e6f494b89833cd034ba0dae29
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm/include/asm/arch-rockchip/gpio.h | 36 ++
drivers/gpio/Kconfig | 13 +
drivers/gpio/rk_gpio.c | 89 ++++-
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rk3568.c | 360 ++++++++++++++++++
.../pinctrl/rockchip/pinctrl-rockchip-core.c | 11 +-
drivers/pinctrl/rockchip/pinctrl-rockchip.h | 42 ++
7 files changed, 530 insertions(+), 22 deletions(-)
create mode 100644 drivers/pinctrl/rockchip/pinctrl-rk3568.c
--- a/arch/arm/include/asm/arch-rockchip/gpio.h
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -6,6 +6,7 @@
#ifndef _ASM_ARCH_GPIO_H
#define _ASM_ARCH_GPIO_H
+#ifndef CONFIG_ROCKCHIP_GPIO_V2
struct rockchip_gpio_regs {
u32 swport_dr;
u32 swport_ddr;
@@ -23,6 +24,41 @@ struct rockchip_gpio_regs {
u32 ls_sync;
};
check_member(rockchip_gpio_regs, ls_sync, 0x60);
+#else
+struct rockchip_gpio_regs {
+ u32 swport_dr_l; /* ADDRESS OFFSET: 0x0000 */
+ u32 swport_dr_h; /* ADDRESS OFFSET: 0x0004 */
+ u32 swport_ddr_l; /* ADDRESS OFFSET: 0x0008 */
+ u32 swport_ddr_h; /* ADDRESS OFFSET: 0x000c */
+ u32 int_en_l; /* ADDRESS OFFSET: 0x0010 */
+ u32 int_en_h; /* ADDRESS OFFSET: 0x0014 */
+ u32 int_mask_l; /* ADDRESS OFFSET: 0x0018 */
+ u32 int_mask_h; /* ADDRESS OFFSET: 0x001c */
+ u32 int_type_l; /* ADDRESS OFFSET: 0x0020 */
+ u32 int_type_h; /* ADDRESS OFFSET: 0x0024 */
+ u32 int_polarity_l; /* ADDRESS OFFSET: 0x0028 */
+ u32 int_polarity_h; /* ADDRESS OFFSET: 0x002c */
+ u32 int_bothedge_l; /* ADDRESS OFFSET: 0x0030 */
+ u32 int_bothedge_h; /* ADDRESS OFFSET: 0x0034 */
+ u32 debounce_l; /* ADDRESS OFFSET: 0x0038 */
+ u32 debounce_h; /* ADDRESS OFFSET: 0x003c */
+ u32 dbclk_div_en_l; /* ADDRESS OFFSET: 0x0040 */
+ u32 dbclk_div_en_h; /* ADDRESS OFFSET: 0x0044 */
+ u32 dbclk_div_con; /* ADDRESS OFFSET: 0x0048 */
+ u32 reserved004c; /* ADDRESS OFFSET: 0x004c */
+ u32 int_status; /* ADDRESS OFFSET: 0x0050 */
+ u32 reserved0054; /* ADDRESS OFFSET: 0x0054 */
+ u32 int_rawstatus; /* ADDRESS OFFSET: 0x0058 */
+ u32 reserved005c; /* ADDRESS OFFSET: 0x005c */
+ u32 port_eoi_l; /* ADDRESS OFFSET: 0x0060 */
+ u32 port_eoi_h; /* ADDRESS OFFSET: 0x0064 */
+ u32 reserved0068[2]; /* ADDRESS OFFSET: 0x0068 */
+ u32 ext_port; /* ADDRESS OFFSET: 0x0070 */
+ u32 reserved0074; /* ADDRESS OFFSET: 0x0074 */
+ u32 ver_id; /* ADDRESS OFFSET: 0x0078 */
+};
+check_member(rockchip_gpio_regs, ver_id, 0x0078);
+#endif
enum gpio_pu_pd {
GPIO_PULL_NORMAL = 0,
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -341,6 +341,19 @@ config ROCKCHIP_GPIO
The GPIOs for a device are defined in the device tree with one node
for each bank.
+config ROCKCHIP_GPIO_V2
+ bool "Rockchip GPIO driver version 2.0"
+ depends on ROCKCHIP_GPIO
+ default n
+ help
+ Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
+ a number of banks (different for each SoC type) each with 32 GPIOs.
+ The GPIOs for a device are defined in the device tree with one node
+ for each bank.
+
+ Support version 2.0 GPIO controller, which support write enable bits
+ for some registers, such as dr, ddr.
+
config SANDBOX_GPIO
bool "Enable sandbox GPIO driver"
depends on SANDBOX && DM && DM_GPIO
--- a/drivers/gpio/rk_gpio.c
+++ b/drivers/gpio/rk_gpio.c
@@ -2,12 +2,15 @@
/*
* (C) Copyright 2015 Google, Inc
*
- * (C) Copyright 2008-2014 Rockchip Electronics
+ * (C) Copyright 2008-2020 Rockchip Electronics
* Peter, Software Engineering, <superpeter.cai@gmail.com>.
+ * Jianqun Xu, Software Engineering, <jay.xu@rock-chips.com>.
*/
#include <common.h>
#include <dm.h>
+#include <dm/of_access.h>
+#include <dm/device_compat.h>
#include <syscon.h>
#include <linux/errno.h>
#include <asm/gpio.h>
@@ -17,12 +20,34 @@
#include <dm/pinctrl.h>
#include <dt-bindings/clock/rk3288-cru.h>
-enum {
- ROCKCHIP_GPIOS_PER_BANK = 32,
-};
+#include "../pinctrl/rockchip/pinctrl-rockchip.h"
#define OFFSET_TO_BIT(bit) (1UL << (bit))
+#ifdef CONFIG_ROCKCHIP_GPIO_V2
+#define REG_L(R) (R##_l)
+#define REG_H(R) (R##_h)
+#define READ_REG(REG) ((readl(REG_L(REG)) & 0xFFFF) | \
+ ((readl(REG_H(REG)) & 0xFFFF) << 16))
+#define WRITE_REG(REG, VAL) \
+{\
+ writel(((VAL) & 0xFFFF) | 0xFFFF0000, REG_L(REG)); \
+ writel((((VAL) & 0xFFFF0000) >> 16) | 0xFFFF0000, REG_H(REG));\
+}
+#define CLRBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) & ~(MASK))
+#define SETBITS_LE32(REG, MASK) WRITE_REG(REG, READ_REG(REG) | (MASK))
+#define CLRSETBITS_LE32(REG, MASK, VAL) WRITE_REG(REG, \
+ (READ_REG(REG) & ~(MASK)) | (VAL))
+
+#else
+#define READ_REG(REG) readl(REG)
+#define WRITE_REG(REG, VAL) writel(VAL, REG)
+#define CLRBITS_LE32(REG, MASK) clrbits_le32(REG, MASK)
+#define SETBITS_LE32(REG, MASK) setbits_le32(REG, MASK)
+#define CLRSETBITS_LE32(REG, MASK, VAL) clrsetbits_le32(REG, MASK, VAL)
+#endif
+
+
struct rockchip_gpio_priv {
struct rockchip_gpio_regs *regs;
struct udevice *pinctrl;
@@ -35,7 +60,7 @@ static int rockchip_gpio_direction_input
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
struct rockchip_gpio_regs *regs = priv->regs;
- clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
+ CLRBITS_LE32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
return 0;
}
@@ -47,8 +72,8 @@ static int rockchip_gpio_direction_outpu
struct rockchip_gpio_regs *regs = priv->regs;
int mask = OFFSET_TO_BIT(offset);
- clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
- setbits_le32(&regs->swport_ddr, mask);
+ CLRSETBITS_LE32(&regs->swport_dr, mask, value ? mask : 0);
+ SETBITS_LE32(&regs->swport_ddr, mask);
return 0;
}
@@ -68,7 +93,7 @@ static int rockchip_gpio_set_value(struc
struct rockchip_gpio_regs *regs = priv->regs;
int mask = OFFSET_TO_BIT(offset);
- clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
+ CLRSETBITS_LE32(&regs->swport_dr, mask, value ? mask : 0);
return 0;
}
@@ -86,8 +111,8 @@ static int rockchip_gpio_get_function(st
ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
if (ret)
return ret;
- is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
-
+ is_output = READ_REG(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
+
return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
#endif
}
@@ -142,19 +167,49 @@ static int rockchip_gpio_probe(struct ud
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct rockchip_gpio_priv *priv = dev_get_priv(dev);
- char *end;
- int ret;
+ struct rockchip_pinctrl_priv *pctrl_priv;
+ struct rockchip_pin_bank *bank;
+ char *end = NULL;
+ static int gpio;
+ int id = -1, ret;
priv->regs = dev_read_addr_ptr(dev);
ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
- if (ret)
+ if (ret) {
+ dev_err(dev, "failed to get pinctrl device %d\n", ret);
return ret;
+ }
+
+ pctrl_priv = dev_get_priv(priv->pinctrl);
+ if (!pctrl_priv) {
+ dev_err(dev, "failed to get pinctrl priv\n");
+ return -EINVAL;
+ }
- uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
end = strrchr(dev->name, '@');
- priv->bank = trailing_strtoln(dev->name, end);
- priv->name[0] = 'A' + priv->bank;
- uc_priv->bank_name = priv->name;
+ if (end)
+ id = trailing_strtoln(dev->name, end);
+ else
+ dev_read_alias_seq(dev, &id);
+
+ if (id < 0)
+ id = gpio++;
+
+ if (id >= pctrl_priv->ctrl->nr_banks) {
+ dev_err(dev, "bank id invalid\n");
+ return -EINVAL;
+ }
+
+ bank = &pctrl_priv->ctrl->pin_banks[id];
+ if (bank->bank_num != id) {
+ dev_err(dev, "bank id mismatch with pinctrl\n");
+ return -EINVAL;
+ }
+
+ priv->bank = bank->bank_num;
+ uc_priv->gpio_count = bank->nr_pins;
+ uc_priv->gpio_base = bank->pin_base;
+ uc_priv->bank_name = bank->name;
return 0;
}
--- a/drivers/pinctrl/rockchip/Makefile
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += pinctrl
obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3568.c
@@ -0,0 +1,360 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+
+static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
+ MR_TOPGRF(RK_GPIO0, RK_PB3, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(0, 0, 0)), /* CAN0 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PA1, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(0, 0, 1)), /* CAN0 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 0)), /* CAN1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PC3, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(2, 2, 1)), /* CAN1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PB5, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(4, 4, 0)), /* CAN2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PB2, RK_FUNC_4, 0x0300, RK_GENMASK_VAL(4, 4, 1)), /* CAN2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PC4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(6, 6, 0)), /* EDPDP_HPDIN IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PC2, RK_FUNC_2, 0x0300, RK_GENMASK_VAL(6, 6, 1)), /* EDPDP_HPDIN IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PB1, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 0)), /* GMAC1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PA7, RK_FUNC_3, 0x0300, RK_GENMASK_VAL(8, 8, 1)), /* GMAC1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PD1, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 0)), /* HDMITX IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PC7, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(10, 10, 1)), /* HDMITX IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PB6, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 0)), /* I2C2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PB4, RK_FUNC_1, 0x0300, RK_GENMASK_VAL(14, 14, 1)), /* I2C2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA0, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(0, 0, 0)), /* I2C3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PB6, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(0, 0, 1)), /* I2C3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PB2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(2, 2, 0)), /* I2C4 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PB1, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(2, 2, 1)), /* I2C4 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PB4, RK_FUNC_4, 0x0304, RK_GENMASK_VAL(4, 4, 0)), /* I2C5 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PD0, RK_FUNC_2, 0x0304, RK_GENMASK_VAL(4, 4, 1)), /* I2C5 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 0)), /* PWM4 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(6, 6, 1)), /* PWM4 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 0)), /* PWM5 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(8, 8, 1)), /* PWM5 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 0)), /* PWM6 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(10, 10, 1)), /* PWM6 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 0)), /* PWM7 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(12, 12, 1)), /* PWM7 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 0)), /* PWM8 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0304, RK_GENMASK_VAL(14, 14, 1)), /* PWM8 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 0)), /* PWM9 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(0, 0, 1)), /* PWM9 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 0)), /* PWM10 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(2, 2, 1)), /* PWM10 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 0)), /* PWM11 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(4, 4, 1)), /* PWM11 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 0)), /* PWM12 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(6, 6, 1)), /* PWM12 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 0)), /* PWM13 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(8, 8, 1)), /* PWM13 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 0)), /* PWM14 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(10, 10, 1)), /* PWM14 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 0)), /* PWM15 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0308, RK_GENMASK_VAL(12, 12, 1)), /* PWM15 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_3, 0x0308, RK_GENMASK_VAL(14, 14, 0)), /* SDMMC2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PA5, RK_FUNC_5, 0x0308, RK_GENMASK_VAL(14, 14, 1)), /* SDMMC2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PB5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(0, 0, 0)), /* SPI0 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(0, 0, 1)), /* SPI0 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PB5, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 0)), /* SPI1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PC3, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(2, 2, 1)), /* SPI1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(4, 4, 0)), /* SPI2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PA0, RK_FUNC_3, 0x030c, RK_GENMASK_VAL(4, 4, 1)), /* SPI2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PB3, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(6, 6, 0)), /* SPI3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(6, 6, 1)), /* SPI3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PB4, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(8, 8, 0)), /* UART1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(8, 8, 1)), /* UART1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PD1, RK_FUNC_1, 0x030c, RK_GENMASK_VAL(10, 10, 0)), /* UART2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(10, 10, 1)), /* UART2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA1, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(12, 12, 0)), /* UART3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PB7, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(12, 12, 1)), /* UART3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_2, 0x030c, RK_GENMASK_VAL(14, 14, 0)), /* UART4 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PB2, RK_FUNC_4, 0x030c, RK_GENMASK_VAL(14, 14, 1)), /* UART4 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PA2, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(0, 0, 0)), /* UART5 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PC2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(0, 0, 1)), /* UART5 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PA4, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 0)), /* UART6 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO1, RK_PD5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(2, 2, 1)), /* UART6 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PA6, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(5, 4, 0)), /* UART7 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PC4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(5, 4, 1)), /* UART7 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PD2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(5, 4, 2)), /* UART7 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO2, RK_PC5, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(6, 6, 0)), /* UART8 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD7, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(6, 6, 1)), /* UART8 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PB0, RK_FUNC_3, 0x0310, RK_GENMASK_VAL(9, 8, 0)), /* UART9 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PC5, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 1)), /* UART9 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PA4, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(9, 8, 2)), /* UART9 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO1, RK_PA2, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(11, 10, 0)), /* I2S1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PC6, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(11, 10, 1)), /* I2S1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(11, 10, 2)), /* I2S1 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO2, RK_PC1, RK_FUNC_1, 0x0310, RK_GENMASK_VAL(12, 12, 0)), /* I2S2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PB6, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(12, 12, 1)), /* I2S2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO3, RK_PA2, RK_FUNC_4, 0x0310, RK_GENMASK_VAL(14, 14, 0)), /* I2S3 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_5, 0x0310, RK_GENMASK_VAL(14, 14, 1)), /* I2S3 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA6, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(0, 0, 0)), /* PDM IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO3, RK_PD6, RK_FUNC_5, 0x0314, RK_GENMASK_VAL(0, 0, 1)), /* PDM IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO0, RK_PA5, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(3, 2, 0)), /* PCIE20 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 1)), /* PCIE20 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PB0, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(3, 2, 2)), /* PCIE20 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO0, RK_PA4, RK_FUNC_3, 0x0314, RK_GENMASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO1, RK_PA5, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux selection M2 */
+ MR_TOPGRF(RK_GPIO0, RK_PA6, RK_FUNC_2, 0x0314, RK_GENMASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux selection M0 */
+ MR_TOPGRF(RK_GPIO2, RK_PD4, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux selection M1 */
+ MR_TOPGRF(RK_GPIO4, RK_PC2, RK_FUNC_4, 0x0314, RK_GENMASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux selection M2 */
+};
+
+static int rk3568_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask;
+ u8 bit;
+ u32 data;
+
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+ if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
+ regmap = priv->regmap_pmu;
+ else
+ regmap = priv->regmap_base;
+
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3568_PULL_PMU_OFFSET 0x20
+#define RK3568_PULL_GRF_OFFSET 0x80
+#define RK3568_PULL_BITS_PER_PIN 2
+#define RK3568_PULL_PINS_PER_REG 8
+#define RK3568_PULL_BANK_STRIDE 0x10
+
+static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *info = bank->priv;
+
+ if (bank->bank_num == 0) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3568_PULL_PMU_OFFSET;
+ *reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3568_PULL_GRF_OFFSET;
+ *reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
+ *bit = (pin_num % RK3568_PULL_PINS_PER_REG);
+ *bit *= RK3568_PULL_BITS_PER_PIN;
+}
+
+#define RK3568_DRV_PMU_OFFSET 0x70
+#define RK3568_DRV_GRF_OFFSET 0x200
+#define RK3568_DRV_BITS_PER_PIN 8
+#define RK3568_DRV_PINS_PER_REG 2
+#define RK3568_DRV_BANK_STRIDE 0x40
+
+static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *info = bank->priv;
+
+ /* The first 32 pins of the first bank are located in PMU */
+ if (bank->bank_num == 0) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3568_DRV_PMU_OFFSET;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3568_DRV_GRF_OFFSET;
+ *reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
+ *bit = (pin_num % RK3568_DRV_PINS_PER_REG);
+ *bit *= RK3568_DRV_BITS_PER_PIN;
+}
+
+#define RK3568_SCHMITT_BITS_PER_PIN 2
+#define RK3568_SCHMITT_PINS_PER_REG 8
+#define RK3568_SCHMITT_BANK_STRIDE 0x10
+#define RK3568_SCHMITT_GRF_OFFSET 0xc0
+#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
+
+static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *info = bank->priv;
+
+ if (bank->bank_num == 0) {
+ *regmap = info->regmap_pmu;
+ *reg = RK3568_SCHMITT_PMUGRF_OFFSET;
+ } else {
+ *regmap = info->regmap_base;
+ *reg = RK3568_SCHMITT_GRF_OFFSET;
+ *reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
+ }
+
+ *reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
+ *bit *= RK3568_SCHMITT_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rk3568_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3568_calc_pull_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+static int rk3568_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data;
+ u8 bit;
+ int drv = (1 << (strength + 1)) - 1;
+ int ret = 0;
+
+ rk3568_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (drv << bit);
+
+ ret = regmap_write(regmap, reg, data);
+ if (ret)
+ return ret;
+
+ if (bank->bank_num == 1 && pin_num == 21)
+ reg = 0x0840;
+ else if (bank->bank_num == 2 && pin_num == 2)
+ reg = 0x0844;
+ else if (bank->bank_num == 2 && pin_num == 8)
+ reg = 0x0848;
+ else if (bank->bank_num == 3 && pin_num == 0)
+ reg = 0x084c;
+ else if (bank->bank_num == 3 && pin_num == 6)
+ reg = 0x0850;
+ else if (bank->bank_num == 4 && pin_num == 0)
+ reg = 0x0854;
+ else
+ return 0;
+
+ data = ((1 << RK3568_DRV_BITS_PER_PIN) - 1) << 16;
+ data |= drv;
+
+ return regmap_write(regmap, reg, data);
+}
+
+static int rk3568_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg;
+ u32 data;
+ u8 bit;
+
+ rk3568_calc_schmitt_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (enable << bit);
+
+ return regmap_write(regmap, reg, data);
+}
+static struct rockchip_pin_bank rk3568_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
+ IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+ PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT),
+};
+
+static const struct rockchip_pin_ctrl rk3568_pin_ctrl = {
+ .pin_banks = rk3568_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3568_pin_banks),
+ .nr_pins = 160,
+ .grf_mux_offset = 0x0,
+ .pmu_mux_offset = 0x0,
+ .iomux_routes = rk3568_mux_route_data,
+ .niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
+ .set_mux = rk3568_set_mux,
+ .set_pull = rk3568_set_pull,
+ .set_drive = rk3568_set_drive,
+ .set_schmitt = rk3568_set_schmitt,
+};
+
+static const struct udevice_id rk3568_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3568-pinctrl",
+ .data = (ulong)&rk3568_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3568) = {
+ .name = "rockchip_rk3568_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3568_pinctrl_ids,
+ .priv_auto = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c
@@ -400,7 +400,7 @@ static int rockchip_pinctrl_set_state(st
int prop_len, param;
const u32 *data;
ofnode node;
-#ifdef CONFIG_OF_LIVE
+#if CONFIG_IS_ENABLED(OF_LIVE)
const struct device_node *np;
struct property *pp;
#else
@@ -440,7 +440,7 @@ static int rockchip_pinctrl_set_state(st
node = ofnode_get_by_phandle(conf);
if (!ofnode_valid(node))
return -ENODEV;
-#ifdef CONFIG_OF_LIVE
+#if CONFIG_IS_ENABLED(OF_LIVE)
np = ofnode_to_np(node);
for (pp = np->properties; pp; pp = pp->next) {
prop_name = pp->name;
@@ -515,13 +515,14 @@ static struct rockchip_pin_ctrl *rockchi
/* preset iomux offset value, set new start value */
if (iom->offset >= 0) {
- if (iom->type & IOMUX_SOURCE_PMU)
+ if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU))
pmu_offs = iom->offset;
else
grf_offs = iom->offset;
} else { /* set current iomux offset */
- iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
- pmu_offs : grf_offs;
+ iom->offset = ((iom->type & IOMUX_SOURCE_PMU) ||
+ (iom->type & IOMUX_L_SOURCE_PMU)) ?
+ pmu_offs : grf_offs;
}
/* preset drv offset value, set new start value */
--- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h
+++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h
@@ -6,9 +6,13 @@
#ifndef __DRIVERS_PINCTRL_ROCKCHIP_H
#define __DRIVERS_PINCTRL_ROCKCHIP_H
+#include <dt-bindings/pinctrl/rockchip.h>
#include <linux/bitops.h>
#include <linux/types.h>
+#define RK_GENMASK_VAL(h, l, v) \
+ (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
+
/**
* Encode variants of iomux registers into a type variable
*/
@@ -18,6 +22,8 @@
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_8WIDTH_2BIT BIT(5)
+#define IOMUX_WRITABLE_32BIT BIT(6)
+#define IOMUX_L_SOURCE_PMU BIT(7)
/**
* Defined some common pins constants
@@ -63,6 +69,21 @@ enum rockchip_pin_pull_type {
};
/**
+ * enum mux route register type, should be invalid/default/topgrf/pmugrf.
+ * INVALID: means do not need to set mux route
+ * DEFAULT: means same regmap as pin iomux
+ * TOPGRF: means mux route setting in topgrf
+ * PMUGRF: means mux route setting in pmugrf
+ */
+enum rockchip_pin_route_type {
+ ROUTE_TYPE_DEFAULT = 0,
+ ROUTE_TYPE_TOPGRF = 1,
+ ROUTE_TYPE_PMUGRF = 2,
+
+ ROUTE_TYPE_INVALID = -1,
+};
+
+/**
* @drv_type: drive strength variant using rockchip_perpin_drv_type
* @offset: if initialized to -1 it will be autocalculated, by specifying
* an initial offset value the relevant source offset can be reset
@@ -220,6 +241,25 @@ struct rockchip_pin_bank {
.pull_type[3] = pull3, \
}
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
+ { \
+ .bank_num = ID, \
+ .pin = PIN, \
+ .func = FUNC, \
+ .route_offset = REG, \
+ .route_val = VAL, \
+ .route_type = FLAG, \
+ }
+
+#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT)
+
+#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF)
+
+#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \
+ PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF)
+
/**
* struct rockchip_mux_recalced_data: recalculate a pin iomux data.
* @num: bank number.
@@ -241,6 +281,7 @@ struct rockchip_mux_recalced_data {
* @bank_num: bank number.
* @pin: index at register or used to calc index.
* @func: the min pin.
+ * @route_type: the register type.
* @route_offset: the max pin.
* @route_val: the register offset.
*/
@@ -248,6 +289,7 @@ struct rockchip_mux_route_data {
u8 bank_num;
u8 pin;
u8 func;
+ enum rockchip_pin_route_type route_type : 8;
u32 route_offset;
u32 route_val;
};

11
package/boot/uboot-rockchip/patches/108-hack-fix-build-rk356x-idbloader.patch Normal file
View File

@ -0,0 +1,11 @@
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -20,7 +20,7 @@
mkimage {
filename = "idbloader.img";
args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
-#ifdef CONFIG_TPL
+#if defined(CONFIG_TPL) || defined(CONFIG_ROCKCHIP_RK3566) || defined(CONFIG_ROCKCHIP_RK3568)
multiple-data-files;
u-boot-tpl {

0
package/boot/uboot-rockchip/patches/100-arm-add-dts-files.patch → package/boot/uboot-rockchip/patches/900-arm-add-dts-files.patch
View File