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ath79: add kernel 5.4 support

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This commit is contained in:
AmadeusGhost 2020-04-23 12:00:03 +08:00
parent a18cb784eb
commit 83f3fc7c9d
149 changed files with 4342 additions and 5866 deletions
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3
target/linux/ath79/Makefile
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@ -4,11 +4,12 @@ ARCH:=mips
BOARD:=ath79
BOARDNAME:=Atheros ATH79 (DTS)
CPU_TYPE:=24kc
SUBTARGETS:=generic nand tiny
SUBTARGETS:=generic mikrotik nand tiny
FEATURES:=ramdisk
KERNEL_PATCHVER:=4.19
KERNEL_TESTING_PATCHVER:=5.4
include $(INCLUDE_DIR)/target.mk

79
target/linux/ath79/config-4.14 → target/linux/ath79/config-5.4
View File

@ -3,27 +3,25 @@ CONFIG_AG71XX=y
CONFIG_AG71XX_DEBUG_FS=y
CONFIG_AR8216_PHY=y
CONFIG_AR8216_PHY_LEDS=y
CONFIG_ARCH_BINFMT_ELF_STATE=y
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_CLOCKSOURCE_DATA=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y
CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y
CONFIG_ARCH_HAS_DMA_WRITE_COMBINE=y
CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
# CONFIG_ARCH_HAS_SG_CHAIN is not set
# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set
# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set
CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y
CONFIG_ARCH_HAS_UNCACHED_SEGMENT=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_USE_MEMREMAP_PROT=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_ATH79=y
CONFIG_ATH79_WDT=y
@ -36,8 +34,10 @@ CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
# CONFIG_COMMON_CLK_BOSTON is not set
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_LOAD_STORE_LR=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_RIXI=y
CONFIG_CPU_HAS_SYNC=y
@ -46,26 +46,36 @@ CONFIG_CPU_MIPS32_R2=y
CONFIG_CPU_MIPSR2=y
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_CPU_R4K_FPU=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_NONCOHERENT=y
CONFIG_DMA_NONCOHERENT_CACHE_SYNC=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_EFI_EARLYCON=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_FIXED_PHY=y
CONFIG_FONT_8x16=y
CONFIG_FONT_AUTOSELECT=y
CONFIG_FONT_SUPPORT=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
CONFIG_GENERIC_LIB_CMPDI2=y
CONFIG_GENERIC_LIB_LSHRDI3=y
CONFIG_GENERIC_LIB_UCMPDI2=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
@ -80,21 +90,17 @@ CONFIG_GPIO_74X164=y
CONFIG_GPIO_ATH79=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_SYSFS=y
# CONFIG_GRO_CELLS is not set
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT_MAP=y
# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
# CONFIG_HAVE_ARCH_BITREVERSE is not set
CONFIG_HAVE_ARCH_COMPILER_H=y
CONFIG_HAVE_ARCH_JUMP_LABEL=y
CONFIG_HAVE_ARCH_KGDB=y
CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
CONFIG_HAVE_CBPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_ASM_MODVERSIONS=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CLK_PREPARE=y
CONFIG_HAVE_CONTEXT_TRACKING=y
@ -102,28 +108,29 @@ CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
CONFIG_HAVE_DMA_API_DEBUG=y
CONFIG_HAVE_DMA_CONTIGUOUS=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FAST_GUP=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_HAVE_GENERIC_VDSO=y
CONFIG_HAVE_IDE=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y
CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
CONFIG_HAVE_KVM=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_HAVE_MEMBLOCK=y
CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION=y
CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
CONFIG_HAVE_NET_DSA=y
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_PCI=y
CONFIG_HAVE_PERF_EVENTS=y
CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
CONFIG_HAVE_RSEQ=y
CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
CONFIG_HW_HAS_PCI=y
CONFIG_HZ_PERIODIC=y
CONFIG_IMAGE_CMDLINE_HACK=y
CONFIG_INITRAMFS_SOURCE=""
@ -135,11 +142,14 @@ CONFIG_IRQ_WORK=y
CONFIG_LEDS_GPIO=y
# CONFIG_LEDS_RESET is not set
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_GPIO=y
CONFIG_MEMFD_CREATE=y
CONFIG_MFD_SYSCON=y
CONFIG_MIGRATION=y
CONFIG_MIPS=y
CONFIG_MIPS_ASID_BITS=8
CONFIG_MIPS_ASID_SHIFT=0
@ -149,9 +159,7 @@ CONFIG_MIPS_CLOCK_VSYSCALL=y
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
# CONFIG_MIPS_ELF_APPENDED_DTB is not set
# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_MACHINE is not set
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_MIPS_RAW_APPENDED_DTB=y
CONFIG_MIPS_SPRAM=y
@ -161,13 +169,11 @@ CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_CFI_I2 is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_M25P80=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
CONFIG_MTD_PARSER_CYBERTAN=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_LZMA_FW=y
CONFIG_MTD_SPLIT_SEAMA_FW=y
CONFIG_MTD_SPLIT_TPLINK_FW=y
@ -177,18 +183,16 @@ CONFIG_MTD_VIRT_CONCAT=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_PER_CPU_KM=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
# CONFIG_NO_IOPORT_MAP is not set
CONFIG_NVMEM=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_ADDRESS_PCI=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OF_NET=y
CONFIG_OF_PCI=y
CONFIG_OF_PCI_IRQ=y
CONFIG_PCI=y
CONFIG_PCI_AR71XX=y
CONFIG_PCI_AR724X=y
@ -200,28 +204,27 @@ CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
# CONFIG_PHY_AR7100_USB is not set
# CONFIG_PHY_AR7200_USB is not set
# CONFIG_PHY_ATH79_USB is not set
CONFIG_PINCTRL=y
CONFIG_RATIONAL=y
# CONFIG_RCU_NEED_SEGCBLIST is not set
# CONFIG_RCU_STALL_COMMON is not set
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RESET_ATH79=y
CONFIG_RESET_CONTROLLER=y
# CONFIG_SCHED_INFO is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SERIAL_8250_FSL is not set
CONFIG_SERIAL_8250_NR_UARTS=1
CONFIG_SERIAL_8250_RUNTIME_UARTS=1
CONFIG_SERIAL_AR933X=y
CONFIG_SERIAL_AR933X_CONSOLE=y
CONFIG_SERIAL_AR933X_NR_UARTS=2
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_AR934X=y
CONFIG_SPI_ATH79=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_GPIO=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_RB4XX is not set
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
@ -236,7 +239,9 @@ CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_SYS_SUPPORTS_ZBOOT=y
CONFIG_SYS_SUPPORTS_ZBOOT_UART_PROM=y
CONFIG_TARGET_ISA_REV=2
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y

4
target/linux/ath79/dts/ar7161_buffalo_wzr-hp-ag300h.dts
View File

@ -234,14 +234,14 @@
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-max-frequency = <50000000>;
m25p,fast-read;
};
flash1: flash@1 {
compatible = "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <104000000>;
spi-max-frequency = <50000000>;
m25p,fast-read;
};
};

22
target/linux/ath79/dts/ar7240_ubnt_bullet-m-ar7240.dts Normal file
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@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar7240.dtsi"
#include "ar724x_ubnt_xm.dtsi"
#include "ar724x_ubnt_xm_outdoor.dtsi"
/ {
compatible = "ubnt,bullet-m-ar7240", "ubnt,xm", "qca,ar7240";
model = "Ubiquiti Bullet M XM (AR7240)";
};
&eth0 {
fixed-link {
speed = <100>;
full-duplex;
};
};
&eth1 {
compatible = "syscon", "simple-mfd";
};

3
target/linux/ath79/dts/ar7241_ubnt_airrouter.dts
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@ -1,7 +1,8 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar7241_ubnt_xm.dtsi"
#include "ar7241.dtsi"
#include "ar724x_ubnt_xm.dtsi"
/ {
compatible = "ubnt,airrouter", "ubnt,xm", "qca,ar7241";

15
target/linux/ath79/dts/ar7241_ubnt_bullet-m-ar7241.dts Normal file
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@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar7241.dtsi"
#include "ar724x_ubnt_xm.dtsi"
#include "ar724x_ubnt_xm_outdoor.dtsi"
/ {
compatible = "ubnt,bullet-m-ar7241", "ubnt,xm", "qca,ar7241";
model = "Ubiquiti Bullet M XM (AR7241)";
};
&eth1 {
compatible = "syscon", "simple-mfd";
};

13
target/linux/ath79/dts/ar7241_ubnt_bullet-m.dts
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@ -1,13 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar7241_ubnt_xm_outdoor.dtsi"
/ {
compatible = "ubnt,bullet-m", "ubnt,xm", "qca,ar7241";
model = "Ubiquiti Bullet M";
};
&eth1 {
compatible = "syscon", "simple-mfd";
};

15
target/linux/ath79/dts/ar7241_ubnt_nanobridge-m.dts Normal file
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@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar7241.dtsi"
#include "ar724x_ubnt_xm.dtsi"
#include "ar724x_ubnt_xm_outdoor.dtsi"
/ {
compatible = "ubnt,nanobridge-m", "ubnt,xm", "qca,ar7241";
model = "Ubiquiti NanoBridge M";
};
&eth1 {
compatible = "syscon", "simple-mfd";
};

4
target/linux/ath79/dts/ar7241_ubnt_nanostation-loco-m.dts
View File

@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar7241_ubnt_xm_outdoor.dtsi"
#include "ar7241.dtsi"
#include "ar724x_ubnt_xm.dtsi"
#include "ar724x_ubnt_xm_outdoor.dtsi"
/ {
compatible = "ubnt,nanostation-loco-m", "ubnt,xm", "qca,ar7241";

4
target/linux/ath79/dts/ar7241_ubnt_nanostation-m.dts
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@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar7241_ubnt_xm_outdoor.dtsi"
#include "ar7241.dtsi"
#include "ar724x_ubnt_xm.dtsi"
#include "ar724x_ubnt_xm_outdoor.dtsi"
/ {
compatible = "ubnt,nanostation-m", "ubnt,xm", "qca,ar7241";

4
target/linux/ath79/dts/ar7241_ubnt_picostation-m.dts
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@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar7241_ubnt_xm_outdoor.dtsi"
#include "ar7241.dtsi"
#include "ar724x_ubnt_xm.dtsi"
#include "ar724x_ubnt_xm_outdoor.dtsi"
/ {
compatible = "ubnt,picostation-m", "ubnt,xm", "qca,ar7241";

4
target/linux/ath79/dts/ar7241_ubnt_rocket-m.dts
View File

@ -1,7 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar7241_ubnt_xm_outdoor.dtsi"
#include "ar7241.dtsi"
#include "ar724x_ubnt_xm.dtsi"
#include "ar724x_ubnt_xm_outdoor.dtsi"
/ {
compatible = "ubnt,rocket-m", "ubnt,xm", "qca,ar7241";

1
target/linux/ath79/dts/ar7242_tplink_tl-wr2543-v1.dts
View File

@ -109,6 +109,7 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";

3
target/linux/ath79/dts/ar724x.dtsi
View File

@ -130,6 +130,9 @@
interrupt-parent = <&cpuintc>;
interrupts = <2>;
resets = <&rst 6>, <&rst 7>;
reset-names = "hc", "phy";
interrupt-controller;
#interrupt-cells = <1>;

5
target/linux/ath79/dts/ar7241_ubnt_xm.dtsi → target/linux/ath79/dts/ar724x_ubnt_xm.dtsi
View File

@ -3,12 +3,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ar7241.dtsi"
/ {
compatible = "ubnt,xm", "qca,ar7241";
model = "Ubiquiti Networks XM (rev 1.0) board";
keys {
compatible = "gpio-keys";

2
target/linux/ath79/dts/ar7241_ubnt_xm_outdoor.dtsi → target/linux/ath79/dts/ar724x_ubnt_xm_outdoor.dtsi
View File

@ -1,7 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "ar7241_ubnt_xm.dtsi"
/ {
aliases {
led-boot = &led_link4;

1
target/linux/ath79/dts/ar9132_tplink_tl-wr1043nd-v1.dts
View File

@ -112,6 +112,7 @@
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";

2
target/linux/ath79/dts/ar9330_glinet_gl-ar150.dts
View File

@ -86,7 +86,7 @@
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
spi-max-frequency = <50000000>;
reg = <0>;
partitions {

2
target/linux/ath79/dts/ar9330_pqi_air-pen.dts
View File

@ -75,7 +75,7 @@
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
spi-max-frequency = <50000000>;
reg = <0>;
partitions {

2
target/linux/ath79/dts/ar9331_8dev_carambola2.dts
View File

@ -73,7 +73,7 @@
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
spi-max-frequency = <50000000>;
reg = <0>;
partitions {

4
target/linux/ath79/dts/ar9331_embeddedwireless_dorin.dts
View File

@ -33,7 +33,7 @@
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
};
reset {
@ -68,7 +68,7 @@
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
spi-max-frequency = <50000000>;
reg = <0>;
partitions {

2
target/linux/ath79/dts/ar9331_tplink_tl-mr3020-v1.dts
View File

@ -120,7 +120,7 @@
/* Spansion S25FL032PIF SPI flash */
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
spi-max-frequency = <50000000>;
reg = <0>;
partitions {

2
target/linux/ath79/dts/ar9331_tplink_tl-mr3040-v2.dts
View File

@ -114,7 +114,7 @@
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <104000000>;
spi-max-frequency = <50000000>;
reg = <0>;
partitions {

9
target/linux/ath79/dts/ar9331_tplink_tl-wr740n-v5.dts Normal file
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar9331_tplink_tl-wr741nd-v4.dtsi"
/ {
model = "TP-Link TL-WR740N v5";
compatible = "tplink,tl-wr740n-v5", "qca,ar9331";
};

72
target/linux/ath79/dts/ar9341_tplink_tl-wa860re-v1.dts Normal file
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@ -0,0 +1,72 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar9341_tplink_tl-wa.dtsi"
/ {
model = "TP-Link TL-WA860RE v1";
compatible = "tplink,tl-wa860re-v1", "qca,ar9341";
aliases {
led-boot = &led_power_green;
led-failsafe = &led_power_orange;
led-running = &led_power_green;
led-upgrade = &led_power_orange;
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
wps {
label = "WPS";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
onoff {
label = "ONOFF";
linux,code = <BTN_1>;
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
leds {
compatible = "gpio-leds";
lan {
label = "tp-link:green:lan";
gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
};
led_power_green: power_green {
label = "tp-link:green:power";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
default-state = "on";
};
led_power_orange: power_orange {
label = "tp-link:orange:power";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
};
wlan_green {
label = "tp-link:green:wlan";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wlan_orange {
label = "tp-link:orange:wlan";
gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
};
};
};

3
target/linux/ath79/dts/ar9344.dtsi
View File

@ -46,6 +46,9 @@
interrupt-parent = <&intc2>;
interrupts = <1>;
resets = <&rst 6>, <&rst 7>;
reset-names = "hc", "phy";
interrupt-controller;
#interrupt-cells = <1>;

182
target/linux/ath79/dts/ar9344_devolo_magic-2-wifi.dts Normal file
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@ -0,0 +1,182 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "ar9344.dtsi"
/ {
model = "Devolo Magic 2 Wifi";
compatible = "devolo,magic-2-wifi", "qca,ar9344";
aliases {
led-boot = &led_dlan_red;
led-failsafe = &led_dlan_red;
led-running = &led_dlan_white;
led-upgrade = &led_dlan_red;
};
leds {
compatible = "gpio-leds";
wlan {
label = "devolo:white:wlan";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
led_dlan_white: dlan_white {
label = "devolo:white:dlan";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
};
led_dlan_red: dlan_red {
label = "devolo:red:dlan";
gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
panic-indicator;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
linux,code = <KEY_RESTART>;
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
wifi {
label = "WIFI button";
linux,code = <KEY_RFKILL>;
gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
debounce-interval = <60>;
};
dlan {
label = "DLAN button";
linux,code = <BTN_0>;
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
};
&gpio {
status = "okay";
wlan_power {
gpio-hog;
line-name = "WLAN power";
gpios = <&gpio 21 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
uboot: partition@0 {
label = "u-boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x10000>;
read-only;
};
partition@50000 {
label = "Config1";
reg = <0x50000 0x10000>;
read-only;
};
partition@60000 {
label = "Config2";
reg = <0x60000 0x10000>;
read-only;
};
partition@70000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x70000 0xf80000>;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x10000>;
read-only;
};
};
};
};
&ref {
clock-frequency = <40000000>;
};
&uart {
status = "okay";
};
&eth0 {
status = "okay";
pll-data = <0x02000000 0x00000101 0x00001616>;
mtd-mac-address = <&art 0x1002>;
mtd-mac-address-increment = <2>;
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
};
&pcie {
status = "okay";
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0 0 0 0 0>;
};
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
phy-mode = "rgmii";
qca,ar8327-initvals = <
/* PORT0: RGMII, MAC0/6 exchage, tx_delay 01, No rx_delay */
0x04 0x06400000
0x08 0x00000000 /* PORT5 PAD MODE CTRL */
0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
};

9
target/linux/ath79/dts/ar9344_tplink_tl-wdr4310-v1.dts Normal file
View File

@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "ar9344_tplink_tl-wdr4300.dtsi"
/ {
model = "TP-Link TL-WDR4310 v1";
compatible = "tplink,tl-wdr4310-v1", "qca,ar9344";
};

8
target/linux/ath79/dts/ar934x.dtsi
View File

@ -232,6 +232,8 @@
pll-handle = <&pll>;
resets = <&rst 9>, <&rst 22>;
reset-names = "mac", "mdio";
clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
clock-names = "eth", "mdio";
};
&mdio1 {
@ -272,8 +274,10 @@
&eth1 {
compatible = "qca,ar9340-eth", "syscon";
resets = <&rst 13>;
reset-names = "mac";
resets = <&rst 13>, <&rst 23>;
reset-names = "mac", "mdio";
clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
clock-names = "eth", "mdio";
phy-mode = "gmii";
fixed-link {

4
target/linux/ath79/dts/ath79.dtsi
View File

@ -49,7 +49,7 @@
interrupts = <4>;
phy-mode = "mii";
mdio0: mdio-bus {
mdio0: mdio {
status = "disabled";
compatible = "qca,ath79-mdio";
@ -72,7 +72,7 @@
interrupts = <5>;
phy-mode = "mii";
mdio1: mdio-bus {
mdio1: mdio {
status = "disabled";
compatible = "qca,ath79-mdio";

132
target/linux/ath79/dts/qca9531_comfast_cf-ew72.dts Normal file
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@ -0,0 +1,132 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "qca953x.dtsi"
/ {
compatible = "comfast,cf-ew72", "qca,qca9531";
model = "COMFAST CF-EW72";
aliases {
serial0 = &uart;
led-boot = &led_wan;
led-failsafe = &led_wan;
led-upgrade = &led_wan;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&jtag_disable_pins>;
lan {
label = "cf-ew72:blue:lan";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
};
led_wan: wan {
label = "cf-ew72:blue:wan";
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
wlan {
label = "cf-ew72:blue:wlan";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
watchdog {
compatible = "linux,wdt-gpio";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
hw_algo = "toggle";
hw_margin_ms = <1200>;
always-running;
};
};
&pcie0 {
status = "okay";
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "winbond,w25q128", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x010000>;
read-only;
};
art: partition@10000 {
label = "art";
reg = <0x010000 0x010000>;
read-only;
};
partition@20000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x020000 0xfd0000>;
};
partition@ff0000 {
label = "nvram";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&uart {
status = "okay";
};
&eth0 {
status = "okay";
phy-handle = <&swphy4>;
mtd-mac-address = <&art 0x0>;
mtd-mac-address-increment = <1>;
};
&eth1 {
mtd-mac-address = <&art 0x0>;
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
mtd-mac-address = <&art 0x0>;
mtd-mac-address-increment = <3>;
};

133
target/linux/ath79/dts/qca9531_comfast_cf-wr752ac-v1.dts Normal file
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@ -0,0 +1,133 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "qca953x.dtsi"
/ {
compatible = "comfast,cf-wr752ac-v1", "qca,qca9531";
model = "COMFAST CF-WR752AC v1";
aliases {
serial0 = &uart;
led-boot = &led_lan;
led-failsafe = &led_lan;
led-upgrade = &led_lan;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&jtag_disable_pins &pinmux_led_rssihigh &pinmux_led_rssilow>;
led_lan: lan {
label = "cf-wr752ac-v1:blue:lan";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
};
rssihigh {
label = "cf-wr752ac-v1:green:rssihigh";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
rssilow {
label = "cf-wr752ac-v1:red:rssilow";
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
button {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
};
&pinmux {
pinmux_led_rssihigh: pinmux_led_rssihigh {
pinctrl-single,bits = <0xc 0x0 0xff000000>;
};
pinmux_led_rssilow: pinmux_led_rssilow {
pinctrl-single,bits = <0x8 0x0 0xff000000>;
};
};
&pcie0 {
status = "okay";
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x010000>;
read-only;
};
art: partition@10000 {
label = "art";
reg = <0x010000 0x010000>;
read-only;
};
partition@20000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x020000 0xfd0000>;
};
partition@ff0000 {
label = "nvram";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&uart {
status = "okay";
};
&eth0 {
status = "okay";
phy-handle = <&swphy4>;
mtd-mac-address = <&art 0x0>;
};
&eth1 {
compatible = "syscon", "simple-mfd";
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
mtd-mac-address = <&art 0x0>;
mtd-mac-address-increment = <10>;
};

6
target/linux/ath79/dts/qca9531_glinet_gl-ar750.dts
View File

@ -11,6 +11,10 @@
model = "GL.iNet GL-AR750";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
label-mac-device = &eth0;
};
@ -36,7 +40,7 @@
leds {
compatible = "gpio-leds";
power {
led_power: power {
label = "gl-ar750:white:power";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
default-state = "on";

209
target/linux/ath79/dts/qca9531_tplink_tl-mr3420-v3.dts Normal file
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@ -0,0 +1,209 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "qca953x.dtsi"
/ {
compatible = "tplink,tl-mr3420-v3", "qca,qca9531";
model = "TP-Link TL-MR3420 v3";
aliases {
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
label-mac-device = &wmac;
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
led_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <10000000>;
};
};
gpio-export {
compatible = "gpio-export";
gpio_shift_register_oe {
gpio-export,name = "tp-link:oe:sr";
gpio-export,output = <0>;
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
gpio_shift_register_reset {
gpio-export,name = "tp-link:reset:sr";
gpio-export,output = <1>;
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_system: system {
label = "tp-link:green:system";
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
default-state = "on";
};
lan4 {
label = "tp-link:green:lan4";
gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
};
lan3 {
label = "tp-link:green:lan3";
gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
};
lan2 {
label = "tp-link:green:lan2";
gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
};
lan1 {
label = "tp-link:green:lan1";
gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
};
wan {
label = "tp-link:green:wan";
gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
};
wan_fail {
label = "tp-link:orange:wan";
gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
};
wlan {
label = "tp-link:green:wlan";
gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
usb {
label = "tp-link:green:usb";
gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
trigger-sources = <&hub_port>;
linux,default-trigger = "usbport";
};
qss {
label = "tp-link:green:qss";
gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
linux,code = <KEY_RESTART>;
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
rfkill {
label = "RF kill button";
linux,code = <KEY_RFKILL>;
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
};
&uart {
status = "okay";
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
uboot: partition@0 {
label = "u-boot";
reg = <0x000000 0x020000>;
read-only;
};
partition@20000 {
compatible = "tplink,firmware";
label = "firmware";
reg = <0x020000 0x3d0000>;
};
art: partition@3f0000 {
label = "art";
reg = <0x3f0000 0x010000>;
read-only;
};
};
};
};
&eth1 {
mtd-mac-address = <&uboot 0x1fc00>;
};
&eth0 {
status = "okay";
phy-handle = <&swphy4>;
mtd-mac-address = <&uboot 0x1fc00>;
mtd-mac-address-increment = <1>;
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
mtd-mac-address = <&uboot 0x1fc00>;
};
&usb0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
hub_port: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&usb_phy {
status = "okay";
};

3
target/linux/ath79/dts/qca953x.dtsi
View File

@ -164,6 +164,9 @@
interrupt-parent = <&intc2>;
interrupts = <1>;
resets = <&rst 6>, <&rst 7>;
reset-names = "hc", "phy";
interrupt-controller;
#interrupt-cells = <1>;

93
target/linux/ath79/dts/qca9556_avm_fritz-repeater.dtsi Normal file
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@ -0,0 +1,93 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "qca9557.dtsi"
/ {
chosen {
bootargs = "console=ttyS0,115200n8";
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
};
};
};
&uart {
status = "okay";
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "urlader";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
compatible = "avm,eva-firmware";
label = "firmware";
reg = <0x20000 0xee0000>;
};
partition@f00000 {
label = "tffs (1)";
reg = <0xf00000 0x80000>;
read-only;
};
partition@f80000 {
label = "tffs (2)";
reg = <0xf80000 0x80000>;
read-only;
};
};
};
};
&wmac {
status = "okay";
qca,no-eeprom;
};
&eth1 {
status = "okay";
phy-handle = <&phy0>;
pll-data = <0x3000000 0x101 0x1313>;
gmac-config {
device = <&gmac>;
ge0-sgmii = <0>;
};
};
&mdio1 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
};
};

112
target/linux/ath79/dts/qca9556_avm_fritz1750e.dts Normal file
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@ -0,0 +1,112 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/gpio/gpio.h>
#include "qca9556_avm_fritz-repeater.dtsi"
/ {
compatible = "avm,fritz1750e", "qca,qca9557";
model = "AVM FRITZ!WLAN Repeater 1750E";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
led_spi {
compatible = "spi-gpio";
#address-cells = <1>;
#size-cells = <0>;
sck-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
num-chipselects = <0>;
spi_gpio: led_gpio@0 {
compatible = "fairchild,74hc595";
reg = <0>;
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
spi-max-frequency = <10000000>;
gpio_latch_bit {
gpio-hog;
gpios = <7 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio-latch-bit";
};
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "fritz1750e:green:power";
gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
};
wlan {
label = "fritz1750e:green:wlan";
gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
lan {
label = "fritz1750e:green:lan";
gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
};
rssi0 {
label = "fritz1750e:green:rssi0";
gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
};
rssi1 {
label = "fritz1750e:green:rssi1";
gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
};
rssi2 {
label = "fritz1750e:green:rssi2";
gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;
};
rssi3 {
label = "fritz1750e:green:rssi3";
gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;
};
rssi4 {
label = "fritz1750e:green:rssi4";
gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;
};
};
};
&pcie0 {
status = "okay";
};
&phy0 {
reset-gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
};
&gpio {
reset-pcie-ep {
gpio-hog;
gpios = <17 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PCIE EP reset";
};
reset-pcie {
gpio-hog;
gpios = <18 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "PCIE Bus reset";
};
};

76
target/linux/ath79/dts/qca9556_avm_fritz450e.dts Normal file
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@ -0,0 +1,76 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/gpio/gpio.h>
#include "qca9556_avm_fritz-repeater.dtsi"
/ {
compatible = "avm,fritz450e", "qca,qca9557";
model = "AVM FRITZ!WLAN Repeater 450E";
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "fritz450e:green:power";
gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
};
wlan {
label = "fritz450e:green:wlan";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
lan {
label = "fritz450e:green:lan";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
};
rssi2 {
label = "fritz450e:green:rssi2";
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
rssi3 {
label = "fritz450e:green:rssi3";
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
};
rssi4 {
label = "fritz450e:green:rssi4";
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
};
};
};
&gpio {
/*
* Wondered why rssi0 and rssi1 are missing?
*
* AVM seems to have run low on usable GPIO pins, so
* instead of adding a shift register like they did for
* the 1750E they figured out "Why not use the LEDs on
* the AR8033?".
*
* EVA configures the PHY in a way it does not display
* the link-state using it's LEDs. When we reset the PHY
* using the reset-mechanism of the PHY subsystem, this
* setting is cleared.
*
* We avoid this by keeping the reset line high.
*/
phy-reset {
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "phy-reset";
};
};

55
target/linux/ath79/dts/qca9556_mikrotik_routerboard-wap-g-5hact2hnd.dts
View File

@ -53,7 +53,7 @@
&eth1 {
status = "okay";
mtd-mac-address = <&art 0x10>;
mtd-mac-address = <&hard_config 0x10>;
pll-data = <0x03000101 0x80000101 0x80001313>;
phy-handle = <&phy0>;
@ -73,7 +73,7 @@
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <104000000>;
spi-max-frequency = <40000000>;
partitions {
compatible = "fixed-partitions";
@ -81,32 +81,41 @@
#size-cells = <1>;
partition@0 {
label = "routerboot";
reg = <0x000000 0x00e000>;
label = "RouterBoot";
reg = <0x0 0x20000>;
read-only;
};
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
art: partition@e000 {
label = "art";
reg = <0x000e000 0x001000>;
read-only;
};
partition@0 {
label = "bootloader1";
reg = <0x0 0xe000>;
read-only;
};
partition@f000 {
label = "bios";
reg = <0x000f000 0x001000>;
read-only;
};
hard_config: partition@e000 {
label = "hard_config";
reg = <0xe000 0x1000>;
read-only;
};
partition@10000 {
label = "routerboot2";
reg = <0x010000 0x00f000>;
read-only;
};
partition@f000 {
label = "bios";
reg = <0xf000 0x1000>;
read-only;
};
partition@1f000 {
label = "soft_config";
reg = <0x001f000 0x001000>;
partition@10000 {
label = "bootloader2";
reg = <0x10000 0xf000>;
read-only;
};
partition@1f000 {
label = "soft_config";
reg = <0x1f000 0x1000>;
};
};
partition@20000 {

10
target/linux/ath79/dts/qca9557.dtsi
View File

@ -202,7 +202,7 @@
};
pcie0: pcie-controller@180c0000 {
compatible = "qcom,ar7240-pci";
compatible = "qcom,qca9550-pci", "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x0>;
@ -215,6 +215,9 @@
interrupt-parent = <&intc2>;
interrupts = <1>;
resets = <&rst 6>, <&rst 7>;
reset-names = "hc", "phy";
interrupt-controller;
#interrupt-cells = <1>;
@ -234,7 +237,7 @@
};
pcie1: pcie-controller@18250000 {
compatible = "qcom,ar7240-pci";
compatible = "qcom,qca9550-pci", "qcom,ar7240-pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0x0>;
@ -247,6 +250,9 @@
interrupt-parent = <&intc3>;
interrupts = <0>;
resets = <&rst2 6>, <&rst2 7>;
reset-names = "hc", "phy";
interrupt-controller;
#interrupt-cells = <1>;

217
target/linux/ath79/dts/qca9558_domywifi_dw33d.dts Normal file
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@ -0,0 +1,217 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "qca9557.dtsi"
/ {
compatible = "domywifi,dw33d", "qca,qca9558";
model = "DomyWifi DW33D";
chosen {
bootargs = "console=ttyS0,115200n8";
};
aliases {
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
};
leds {
compatible = "gpio-leds";
led_system: system {
label = "dw33d:blue:system";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
};
mmc {
label = "dw33d:blue:mmc";
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
trigger-sources = <&hub_port0>;
linux,default-trigger = "usbport";
};
usb {
label = "dw33d:blue:usb";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
trigger-sources = <&hub_port1>;
linux,default-trigger = "usbport";
};
wlan2g {
label = "dw33d:blue:wlan2g";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
internet {
label = "dw33d:blue:internet";
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "Reset button";
linux,code = <KEY_RESTART>;
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
};
&pcie0 {
status = "okay";
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0 0 0 0 0>;
};
};
&uart {
status = "okay";
};
&usb_phy0 {
status = "okay";
};
&usb0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
hub_port0: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&usb_phy1 {
status = "okay";
};
&usb1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
hub_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x40000 0x10000>;
};
partition@50000 {
label = "oem-firmware";
reg = <0x50000 0xfa0000>;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x10000>;
read-only;
};
};
};
};
&nand {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "kernel";
reg = <0x0 0x500000>;
};
partition@500000 {
label = "ubi";
reg = <0x500000 0x5b00000>;
};
partition@6000000 {
label = "oem-backup";
reg = <0x6000000 0x2000000>;
};
};
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x04 0x87600000 /* PORT0 PAD MODE CTRL */
0x0c 0x00080080 /* PORT6 PAD MODE CTRL */
0x7c 0x0000007e /* PORT0_STATUS */
0x94 0x0000007e /* PORT6 STATUS */
>;
};
};
&eth0 {
status = "okay";
mtd-mac-address = <&art 0x0>;
pll-data = <0x56000000 0x00000101 0x00001616>;
phy-handle = <&phy0>;
};
&eth1 {
status = "okay";
mtd-mac-address = <&art 0x6>;
pll-data = <0x03000101 0x00000101 0x00001616>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
mtd-mac-address = <&art 0xc>;
};

187
target/linux/ath79/dts/qca9558_mikrotik_routerboard-922uags-5hpacd.dts Normal file
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@ -0,0 +1,187 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "qca9557.dtsi"
/ {
compatible = "mikrotik,routerboard-922uags-5hpacd", "qca,qca9558";
model = "MikroTik RouterBOARD 922UAGS-5HPacD";
aliases {
label-mac-device = &eth0;
led-boot = &led_user;
led-failsafe = &led_user;
led-upgrade = &led_user;
serial0 = &uart;
};
chosen {
bootargs = "console=ttyS0,115200n8";
};
leds {
compatible = "gpio-leds";
led_user: user {
label = "mikrotik:green:user";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
};
};
ath10k-leds {
compatible = "gpio-leds";
wlan5g {
label = "mikrotik:green:wlan5g";
gpios = <&ath10k 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
};
gpio-export {
compatible = "gpio-export";
gpio_usb_power {
gpio-export,name = "mikrotik:power:usb";
gpio-export,output = <0>;
gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
};
gpio_nand_power {
gpio-export,name = "mikrotik:power:nand";
gpio-export,output = <0>;
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
};
};
};
&mdio0 {
status = "okay";
phy4: ethernet-phy@4 {
reg = <4>;
};
};
&eth0 {
status = "okay";
mtd-mac-address = <&hard_config 0x10>;
phy-handle = <&phy4>;
pll-data = <0x8f000000 0xa0000101 0xa0001313>;
gmac-config {
device = <&gmac>;
rgmii-enabled = <1>;
};
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "routerboot";
reg = <0x0000000 0x000c000>;
read-only;
};
hard_config: partition@c000 {
label = "hard_config";
reg = <0x000c000 0x0001000>;
read-only;
};
partition@d000 {
label = "bios";
reg = <0x000d000 0x0001000>;
read-only;
};
partition@e000 {
label = "soft_config";
reg = <0x000e000 0x0001000>;
read-only;
};
};
};
};
&nand {
status = "okay";
nand-ecc-mode = "soft";
qca,nand-swap-dma;
qca,nand-scan-fixup;
partitions {
compatible = "fixed-partitions";
#size-cells = <1>;
partition@0 {
label = "booter";
reg = <0x0000000 0x0040000>;
read-only;
};
partition@40000 {
label = "kernel";
reg = <0x0040000 0x03c0000>;
};
partition@400000 {
label = "ubi";
reg = <0x0400000 0x7c00000>;
};
};
};
&uart {
status = "okay";
};
&pcie0 {
status = "okay";
ath10k: wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0 0 0 0 0>;
#gpio-cells = <2>;
gpio-controller;
};
};
&pcie1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb_phy0 {
status = "okay";
};

186
target/linux/ath79/dts/qca9558_sitecom_wlr-8100.dts Normal file
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@ -0,0 +1,186 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "qca9557.dtsi"
/ {
model = "Sitecom WLR-8100 (X8 AC1750)";
compatible = "sitecom,wlr-8100", "qca,qca9558";
chosen {
bootargs = "console=ttyS0,115200n8";
};
aliases {
led-boot = &led_status_amber;
led-failsafe = &led_status_amber;
led-running = &led_status_amber;
led-upgrade = &led_status_amber;
};
keys {
compatible = "gpio-keys";
wifi2g_rfkill {
label = "2.4GHz - RFKILL";
gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
};
wifi5g_restart {
label = "5GHz - RESTART";
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
led_status_amber: status_amber {
label = "wlr-8100:amber:status";
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
default-state = "on";
};
ops {
label = "wlr-8100:white:ops";
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
};
wifi2g {
label = "wlr-8100:blue:wifi2g";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wifi5g {
label = "wlr-8100:blue:wifi5g";
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
};
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
uboot: partition@0 {
label = "u-boot";
reg = <0x000000 0x030000>;
read-only;
};
partition@30000 {
label = "u-boot-env";
reg = <0x030000 0x010000>;
read-only;
};
partition@40000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x040000 0xf10000>;
};
partition@f50000 {
label = "manufacture";
reg = <0xf50000 0x040000>;
read-only;
};
partition@f90000 {
label = "backup";
reg = <0xf90000 0x010000>;
read-only;
};
partition@fa0000 {
label = "storage";
reg = <0xfa0000 0x050000>;
read-only;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0 0 0 0 0>;
};
};
&uart {
status = "okay";
};
&usb_phy0 {
status = "okay";
};
&usb0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x04 0x87600000 /* PORT0 PAD MODE CTRL */
0x50 0xc437c437 /* LED Control Register 0 */
0x54 0xc337c337 /* LED Control Register 1 */
0x58 0x00000000 /* LED Control Register 2 */
0x5c 0x03ffff00 /* LED Control Register 3 */
0x7c 0x0000007e /* PORT0_STATUS */
>;
};
};
&eth0 {
status = "okay";
phy-handle = <&phy0>;
pll-data = <0xa6000000 0x00000101 0x00001616>;
gmac-config {
device = <&gmac>;
rgmii-enabled = <1>;
};
};
&wmac {
status = "okay";
qca,no-eeprom;
};

87
target/linux/ath79/dts/qca9558_tplink_archer-d7-v1.dts Normal file
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@ -0,0 +1,87 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "qca9558_tplink_archer-d7.dtsi"
/ {
compatible = "tplink,archer-d7-v1", "qca,qca9558";
model = "TP-Link Archer D7 v1";
aliases {
label-mac-device = &wmac;
};
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x020000>;
read-only;
};
partition@20000 {
compatible = "tplink,firmware";
label = "firmware";
reg = <0x020000 0xf90000>;
};
partition@fb0000 {
label = "radioDECT";
reg = <0xfb0000 0x010000>;
read-only;
};
partition@fc0000 {
label = "config";
reg = <0xfc0000 0x010000>;
read-only;
};
romfs: partition@fd0000 {
label = "romfs";
reg = <0xfd0000 0x010000>;
read-only;
};
partition@fe0000 {
label = "rom";
reg = <0xfe0000 0x010000>;
read-only;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&eth0 {
mtd-mac-address = <&romfs 0xf100>;
mtd-mac-address-increment = <1>;
};
&eth1 {
mtd-mac-address = <&romfs 0xf100>;
};
&wmac {
mtd-cal-data = <&art 0x1000>;
mtd-mac-address = <&romfs 0xf100>;
};

179
target/linux/ath79/dts/qca9558_tplink_archer-d7.dtsi Normal file
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@ -0,0 +1,179 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "qca9557.dtsi"
/ {
chosen {
bootargs = "console=ttyS0,115200n8";
};
aliases {
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
led-upgrade = &led_system;
};
leds {
compatible = "gpio-leds";
led_system: system {
label = "tp-link:white:system";
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
default-state = "on";
};
wlan {
label = "tp-link:white:wlan";
gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
};
lan {
label = "tp-link:white:lan";
gpios = <&gpio 23 GPIO_ACTIVE_LOW>;
};
usb {
label = "tp-link:white:usb";
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
trigger-sources = <&hub_port1>, <&hub_port0>;
linux,default-trigger = "usbport";
};
qss {
label = "tp-link:white:qss";
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
wifi {
label = "WiFi button";
linux,code = <KEY_RFKILL>;
gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
};
wps {
label = "WPS button";
linux,code = <KEY_WPS_BUTTON>;
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
};
reset {
label = "Reset button";
linux,code = <KEY_RESTART>;
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
};
};
reg_usb0_vbus: regulator {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb1_vbus: regulator {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 22 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x04 0x00080080 /* PORT0 PAD MODE CTRL */
0x0c 0x07600000 /* PORT6 PAD MODE CTRL */
0x50 0xc737c737 /* LED_CTRL0 */
0x54 0x00000000 /* LED_CTRL1 */
0x58 0x00000000 /* LED_CTRL2 */
0x5c 0x0030c300 /* LED_CTRL3 */
0x7c 0x0000007e /* PORT0_STATUS */
0x94 0x0000007e /* PORT6 STATUS */
>;
};
};
&eth0 {
status = "okay";
phy-handle = <&phy0>;
pll-data = <0x56000000 0x00000101 0x00001616>;
gmac-config {
device = <&gmac>;
rgmii-enabled = <1>;
};
};
&eth1 {
status = "okay";
pll-data = <0x03000101 0x00000101 0x00001616>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&wmac {
status = "okay";
};
&pcie1 {
status = "okay";
};
&uart {
status = "okay";
};
&usb_phy0 {
status = "okay";
};
&usb0 {
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "host";
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
hub_port0: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&usb_phy1 {
status = "okay";
};
&usb1 {
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "host";
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
hub_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};

81
target/linux/ath79/dts/qca9558_tplink_archer-d7b-v1.dts Normal file
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@ -0,0 +1,81 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "qca9558_tplink_archer-d7.dtsi"
/ {
compatible = "tplink,archer-d7b-v1", "qca,qca9558";
model = "TP-Link Archer D7b v1";
aliases {
label-mac-device = &wmac;
};
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x020000>;
read-only;
};
partition@20000 {
compatible = "tplink,firmware";
label = "firmware";
reg = <0x020000 0xfa0000>;
};
partition@fc0000 {
label = "config";
reg = <0xfc0000 0x010000>;
read-only;
};
romfs: partition@fd0000 {
label = "romfs";
reg = <0xfd0000 0x010000>;
read-only;
};
partition@fe0000 {
label = "reserve";
reg = <0xfe0000 0x010000>;
read-only;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
};
&eth0 {
mtd-mac-address = <&romfs 0xf100>;
mtd-mac-address-increment = <1>;
};
&eth1 {
mtd-mac-address = <&romfs 0xf100>;
};
&wmac {
mtd-cal-data = <&art 0x1000>;
mtd-mac-address = <&romfs 0xf100>;
};

23
target/linux/ath79/dts/qca9558_zyxel_nbg6716.dts
View File

@ -29,7 +29,7 @@
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
};
wan {
internet {
label = "nbg6716:white:internet";
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
};
@ -38,31 +38,31 @@
label = "nbg6716:white:usb1";
gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
trigger-sources = <&hub_port0>;
trigger-sources = <&hub_port1>;
};
usb2 {
label = "nbg6716:white:usb2";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "usbport";
trigger-sources = <&hub_port1>;
trigger-sources = <&hub_port0>;
};
wifi2 {
label = "nbg6716:white:wifi2";
wifi2g {
label = "nbg6716:white:wifi2g";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
wifi5 {
label = "nbg6716:white:wifi5";
wifi5g {
label = "nbg6716:white:wifi5g";
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy0tpt";
};
wps {
label = "nbg6716:white:wps";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
};
};
@ -79,18 +79,21 @@
wifi {
label = "WiFi button";
linux,code = <KEY_RFKILL>;
gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
debounce-interval = <60>;
};
usb1 {
label = "USB1 eject button";
linux,code = <BTN_1>;
gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
usb2 {
label = "USB2 eject button";
linux,code = <BTN_2>;
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
debounce-interval = <60>;
};
@ -262,6 +265,8 @@
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
};
&pcie1 {

12
target/linux/ath79/dts/qca9561_tplink_archer-c60-v1.dts
View File

@ -8,6 +8,18 @@
model = "TP-Link Archer C60 v1";
};
&leds {
wan_amber {
label = "tp-link:amber:wan";
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
};
wps {
label = "tp-link:green:wps";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
};
};
&spi {
status = "okay";
num-cs = <1>;

12
target/linux/ath79/dts/qca9561_tplink_archer-c60-v2.dts
View File

@ -8,6 +8,18 @@
model = "TP-Link Archer C60 v2";
};
&leds {
wan_amber {
label = "tp-link:amber:wan";
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
};
wps {
label = "tp-link:green:wps";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
};
};
&spi {
status = "okay";
num-cs = <1>;

69
target/linux/ath79/dts/qca9561_tplink_archer-c60-v3.dts Normal file
View File

@ -0,0 +1,69 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;
#include "qca9561_tplink_archer-c6x.dtsi"
/ {
compatible = "tplink,archer-c60-v3", "qca,qca9561";
model = "TP-Link Archer C60 v3";
};
&leds {
wan_amber {
label = "tp-link:amber:wan";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
};
};
&spi {
status = "okay";
num-cs = <1>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "factory-boot";
reg = <0x000000 0x01fb00>;
read-only;
};
mac: partition@1fb00 {
label = "mac";
reg = <0x01fb00 0x000500>;
read-only;
};
partition@20000 {
label = "u-boot";
reg = <0x020000 0x010000>;
read-only;
};
partition@30000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x030000 0x7a0000>;
};
partition@7d0000 {
label = "tplink";
reg = <0x7d0000 0x020000>;
read-only;
};
art: partition@7f0000 {
label = "art";
reg = <0x7f0000 0x010000>;
read-only;
};
};
};
};

16
target/linux/ath79/dts/qca9561_tplink_archer-c6x.dtsi
View File

@ -15,7 +15,7 @@
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
label-mac-device = &eth0;
label-mac-device = &eth1;
};
keys {
@ -34,7 +34,7 @@
};
};
leds {
leds: leds {
compatible = "gpio-leds";
led_power: power {
@ -60,20 +60,10 @@
gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
};
wan_amber {
label = "tp-link:amber:wan";
gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
};
lan {
label = "tp-link:green:lan";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
};
wps {
label = "tp-link:green:wps";
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
};
};
};
@ -91,13 +81,13 @@
phy-handle = <&swphy4>;
mtd-mac-address = <&mac 0x8>;
mtd-mac-address-increment = <1>;
};
&eth1 {
status = "okay";
mtd-mac-address = <&mac 0x8>;
mtd-mac-address-increment = <1>;
};
&wmac {

1
target/linux/ath79/dts/qca9563_tplink_re450-v2.dts
View File

@ -180,6 +180,7 @@
&eth0 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy4>;
mtd-mac-address = <&info 0x8>;

1
target/linux/ath79/dts/qca9563_ubnt_unifiac-lite.dtsi
View File

@ -22,5 +22,6 @@
status = "okay";
mtd-mac-address = <&art 0x0>;
phy-mode = "sgmii";
phy-handle = <&phy4>;
};

3
target/linux/ath79/dts/qca956x.dtsi
View File

@ -168,6 +168,9 @@
interrupt-parent = <&intc3>;
interrupts = <0>;
resets = <&rst 6>, <&rst 7>;
reset-names = "hc", "phy";
interrupt-controller;
#interrupt-cells = <1>;

143
target/linux/ath79/files/drivers/mtd/nand/raw/ar934x_nand.c
View File

@ -631,11 +631,19 @@ static void ar934x_nfc_read_status(struct ar934x_nfc *nfc)
nfc->buf[0] = status;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static void ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command,
int column, int page_addr)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
struct nand_chip *nand = &nfc->nand_chip;
#else
static void ar934x_nfc_cmdfunc(struct nand_chip *nand, unsigned int command,
int column, int page_addr)
{
struct mtd_info *mtd = nand_to_mtd(nand);
struct ar934x_nfc *nfc = nand->priv;
#endif
nfc->read_id = false;
if (command != NAND_CMD_PAGEPROG)
@ -740,16 +748,28 @@ static void ar934x_nfc_cmdfunc(struct mtd_info *mtd, unsigned int command,
}
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_dev_ready(struct mtd_info *mtd)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_dev_ready(struct nand_chip *chip)
{
struct ar934x_nfc *nfc = chip->priv;
#endif
return __ar934x_nfc_dev_ready(nfc);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static u8 ar934x_nfc_read_byte(struct mtd_info *mtd)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static u8 ar934x_nfc_read_byte(struct nand_chip *chip)
{
struct ar934x_nfc *nfc = chip->priv;
#endif
u8 data;
WARN_ON(nfc->buf_index >= nfc->buf_size);
@ -764,9 +784,15 @@ static u8 ar934x_nfc_read_byte(struct mtd_info *mtd)
return data;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static void ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static void ar934x_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
{
struct ar934x_nfc *nfc = chip->priv;
#endif
int i;
WARN_ON(nfc->buf_index + len > nfc->buf_size);
@ -784,9 +810,15 @@ static void ar934x_nfc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
}
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static void ar934x_nfc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static void ar934x_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len)
{
struct ar934x_nfc *nfc = chip->priv;
#endif
int buf_index;
int i;
@ -821,10 +853,18 @@ static inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc)
nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_read_oob(struct nand_chip *chip,
int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
int err;
nfc_dbg(nfc, "read_oob: page:%d\n", page);
@ -839,11 +879,18 @@ static int ar934x_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
return 0;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_write_oob(struct nand_chip *chip,
int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
nfc_dbg(nfc, "write_oob: page:%d\n", page);
memcpy(nfc->buf, chip->oob_poi, mtd->oobsize);
@ -852,11 +899,20 @@ static int ar934x_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
page, mtd->oobsize);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_read_page_raw(struct mtd_info *mtd,
struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_read_page_raw(
struct nand_chip *chip, u8 *buf,
int oob_required, int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
int len;
int err;
@ -878,10 +934,18 @@ static int ar934x_nfc_read_page_raw(struct mtd_info *mtd,
return 0;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
u8 *buf, int oob_required, int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_read_page(struct nand_chip *chip,
u8 *buf, int oob_required, int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
u32 ecc_ctrl;
int max_bitflips = 0;
bool ecc_failed;
@ -950,11 +1014,20 @@ static int ar934x_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
return max_bitflips;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_write_page_raw(struct mtd_info *mtd,
struct nand_chip *chip, const u8 *buf,
int oob_required, int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_write_page_raw(
struct nand_chip *chip, const u8 *buf,
int oob_required, int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
int len;
nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required);
@ -970,10 +1043,18 @@ static int ar934x_nfc_write_page_raw(struct mtd_info *mtd,
return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len);
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static int ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
const u8 *buf, int oob_required, int page)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
#else
static int ar934x_nfc_write_page(struct nand_chip *chip,
const u8 *buf, int oob_required, int page)
{
struct ar934x_nfc *nfc = chip->priv;
struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
#endif
int err;
nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required);
@ -981,7 +1062,11 @@ static int ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
/* write OOB first */
if (oob_required &&
!is_all_ff(chip->oob_poi, mtd->oobsize)) {
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
err = ar934x_nfc_write_oob(mtd, chip, page);
#else
err = ar934x_nfc_write_oob(chip, page);
#endif
if (err)
return err;
}
@ -997,14 +1082,22 @@ static int ar934x_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
return err;
}
static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc *nfc) {
reset_control_assert(nfc->rst);
static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc *nfc)
{
int err;
err = reset_control_assert(nfc->rst);
udelay(250);
return err;
}
static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc *nfc) {
reset_control_deassert(nfc->rst);
static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc *nfc)
{
int err;
err = reset_control_deassert(nfc->rst);
udelay(250);
return err;
}
static int ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
@ -1083,6 +1176,11 @@ static int ar934x_nfc_init_tail(struct mtd_info *mtd)
{
struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
struct nand_chip *chip = &nfc->nand_chip;
#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)
u64 chipsize = chip->chipsize;
#else
u64 chipsize = nanddev_target_size(&chip->base);
#endif
u32 ctrl;
u32 t;
int err;
@ -1169,10 +1267,10 @@ static int ar934x_nfc_init_tail(struct mtd_info *mtd)
if (nfc->small_page) {
ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
if (chip->chipsize > (32 << 20)) {
if (chipsize > (32 << 20)) {
nfc->addr_count0 = 4;
nfc->addr_count1 = 3;
} else if (chip->chipsize > (2 << 16)) {
} else if (chipsize > (2 << 16)) {
nfc->addr_count0 = 3;
nfc->addr_count1 = 2;
} else {
@ -1180,10 +1278,10 @@ static int ar934x_nfc_init_tail(struct mtd_info *mtd)
nfc->addr_count1 = 1;
}
} else {
if (chip->chipsize > (128 << 20)) {
if (chipsize > (128 << 20)) {
nfc->addr_count0 = 5;
nfc->addr_count1 = 3;
} else if (chip->chipsize > (8 << 16)) {
} else if (chipsize > (8 << 16)) {
nfc->addr_count0 = 4;
nfc->addr_count1 = 2;
} else {
@ -1329,8 +1427,13 @@ static int ar934x_nfc_attach_chip(struct nand_chip *nand)
static u64 ar934x_nfc_dma_mask = DMA_BIT_MASK(32);
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
static void ar934x_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
unsigned int ctrl)
#else
static void ar934x_nfc_cmd_ctrl(struct nand_chip *chip, int dat,
unsigned int ctrl)
#endif
{
WARN_ON(dat != NAND_CMD_NONE);
}
@ -1401,6 +1504,7 @@ static int ar934x_nfc_probe(struct platform_device *pdev)
nand_set_controller_data(nand, nfc);
nand_set_flash_node(nand, pdev->dev.of_node);
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
nand->chip_delay = 25;
nand->dev_ready = ar934x_nfc_dev_ready;
nand->cmdfunc = ar934x_nfc_cmdfunc;
@ -1408,7 +1512,17 @@ static int ar934x_nfc_probe(struct platform_device *pdev)
nand->read_byte = ar934x_nfc_read_byte;
nand->write_buf = ar934x_nfc_write_buf;
nand->read_buf = ar934x_nfc_read_buf;
#else
nand->legacy.chip_delay = 25;
nand->legacy.dev_ready = ar934x_nfc_dev_ready;
nand->legacy.cmdfunc = ar934x_nfc_cmdfunc;
nand->legacy.cmd_ctrl = ar934x_nfc_cmd_ctrl; /* dummy */
nand->legacy.read_byte = ar934x_nfc_read_byte;
nand->legacy.write_buf = ar934x_nfc_write_buf;
nand->legacy.read_buf = ar934x_nfc_read_buf;
#endif
nand->ecc.mode = NAND_ECC_HW; /* default */
nand->priv = nfc;
platform_set_drvdata(pdev, nfc);
ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
@ -1421,8 +1535,13 @@ static int ar934x_nfc_probe(struct platform_device *pdev)
goto err_free_buf;
}
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
nand->dummy_controller.ops = &ar934x_nfc_controller_ops;
ret = nand_scan(mtd, 1);
#else
nand->legacy.dummy_controller.ops = &ar934x_nfc_controller_ops;
ret = nand_scan(nand, 1);
#endif
if (ret) {
dev_err(&pdev->dev, "nand_scan failed, err:%d\n", ret);
goto err_free_buf;
@ -1444,12 +1563,18 @@ err_free_buf:
static int ar934x_nfc_remove(struct platform_device *pdev)
{
struct ar934x_nfc *nfc;
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
struct mtd_info *mtd;
#endif
nfc = platform_get_drvdata(pdev);
if (nfc) {
#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0)
mtd = ar934x_nfc_to_mtd(nfc);
nand_release(mtd);
#else
nand_release(&nfc->nand_chip);
#endif
ar934x_nfc_free_buf(nfc);
}

10
target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
View File

@ -1581,11 +1581,15 @@ static int ag71xx_probe(struct platform_device *pdev)
ag->stop_desc->next = (u32) ag->stop_desc_dma;
mac_addr = of_get_mac_address(np);
if (mac_addr)
memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) {
#if (LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0))
if (!mac_addr || !is_valid_ether_addr(mac_addr)) {
#else
if (IS_ERR(mac_addr) || !is_valid_ether_addr(mac_addr)) {
#endif
dev_err(&pdev->dev, "invalid MAC address, using random address\n");
eth_random_addr(dev->dev_addr);
} else {
memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
}
ag->phy_if_mode = of_get_phy_mode(np);

37
target/linux/ath79/generic/base-files/etc/board.d/01_leds
View File

@ -12,9 +12,19 @@ case "$board" in
ucidef_set_led_netdev "lan" "LAN" "$boardname:orange:eth0" "eth0"
ucidef_set_led_switch "wan" "WAN" "$boardname:orange:eth1" "switch0" "0x04"
;;
alfa-network,ap121f)
alfa-network,ap121f|\
avm,fritz450e)
ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth0"
;;
avm,fritz1750e)
ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth0"
ucidef_set_rssimon "wlan1" "200000" "1"
ucidef_set_led_rssi "rssilow" "RSSILOW" "$boardname:green:rssi0" "wlan1" "1" "100"
ucidef_set_led_rssi "rssimediumlow" "RSSIMEDIUMLOW" "$boardname:green:rssi1" "wlan1" "20" "100"
ucidef_set_led_rssi "rssimedium" "RSSIMEDIUM" "$boardname:green:rssi2" "wlan1" "40" "100"
ucidef_set_led_rssi "rssimediumhigh" "RSSIMEDIUMHIGH" "$boardname:green:rssi3" "wlan1" "60" "100"
ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "$boardname:green:rssi4" "wlan1" "80" "100"
;;
avm,fritz300e)
ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth0"
ucidef_set_rssimon "wlan0" "200000" "1"
@ -80,15 +90,23 @@ comfast,cf-e560ac)
ucidef_set_led_switch "lan3" "LAN3" "$boardname:blue:lan3" "switch0" "0x08"
ucidef_set_led_switch "lan4" "LAN4" "$boardname:blue:lan4" "switch0" "0x10"
;;
comfast,cf-ew72)
ucidef_set_led_switch "lan" "LAN" "$boardname:blue:lan" "switch0" "0x02"
ucidef_set_led_netdev "wan" "WAN" "$boardname:blue:wan" "eth1"
;;
comfast,cf-wr752ac-v1|\
engenius,ecb1750)
ucidef_set_led_netdev "lan" "LAN" "$boardname:blue:lan" "eth0"
;;
devolo,magic-2-wifi)
ucidef_set_led_netdev "plcw" "dLAN" "devolo:white:dlan" "eth0.1" "rx"
;;
dlink,dir-842-c1|\
dlink,dir-842-c2|\
dlink,dir-842-c3|\
dlink,dir-859-a1)
ucidef_set_led_switch "internet" "WAN" "$boardname:green:internet" "switch0" "0x20"
;;
engenius,ecb1750)
ucidef_set_led_netdev "lan" "LAN" "$boardname:blue:lan" "eth0"
;;
engenius,ews511ap)
ucidef_set_led_netdev "lan1" "LAN1" "$boardname:blue:lan1" "eth1"
ucidef_set_led_netdev "lan2" "LAN2" "$boardname:blue:lan2" "eth0"
@ -174,7 +192,8 @@ tplink,archer-c58-v1|\
tplink,archer-c59-v1|\
tplink,archer-c59-v2|\
tplink,archer-c60-v1|\
tplink,archer-c60-v2)
tplink,archer-c60-v2|\
tplink,archer-c60-v3)
ucidef_set_led_switch "lan" "LAN" "tp-link:green:lan" "switch0" "0x1E"
ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1"
;;
@ -183,6 +202,10 @@ tplink,archer-d50-v1)
ucidef_set_led_switch "wan_data" "WAN Data" "tp-link:white:internet" "switch0" "0x02" "" "tx rx"
ucidef_set_led_switch "wan_link" "WAN Link" "tp-link:white:wan" "switch0" "0x02" "" "link"
;;
tplink,archer-d7-v1|\
tplink,archer-d7b-v1)
ucidef_set_led_switch "lan" "LAN" "tp-link:white:lan" "switch0" "0x3c"
;;
tplink,cpe210-v1|\
tplink,cpe220-v2|\
tplink,cpe220-v3|\
@ -242,8 +265,10 @@ tplink,tl-wr842n-v2)
trendnet,tew-823dru)
ucidef_set_led_netdev "wan" "WAN" "trendnet:green:planet" "eth0"
;;
ubnt,bullet-m|\
ubnt,bullet-m-ar7240|\
ubnt,bullet-m-ar7241|\
ubnt,bullet-m-xw|\
ubnt,nanobridge-m|\
ubnt,nanostation-loco-m|\
ubnt,nanostation-loco-m-xw|\
ubnt,nanostation-m|\

50
target/linux/ath79/generic/base-files/etc/board.d/02_network
View File

@ -13,7 +13,9 @@ ath79_setup_interfaces()
adtran,bsap1840|\
alfa-network,ap121f|\
aruba,ap-105|\
avm,fritz1750e|\
avm,fritz300e|\
comfast,cf-wr752ac-v1|\
devolo,dvl1200i|\
devolo,dvl1750c|\
devolo,dvl1750i|\
@ -21,7 +23,6 @@ ath79_setup_interfaces()
dlink,dir-505|\
engenius,ecb1750|\
glinet,gl-ar300m-lite|\
mikrotik,routerboard-wap-g-5hact2hnd|\
netgear,ex6400|\
netgear,ex7300|\
ocedo,koala|\
@ -41,11 +42,13 @@ ath79_setup_interfaces()
tplink,re450-v1|\
tplink,re450-v2|\
tplink,tl-wr902ac-v1|\
ubnt,bullet-m|\
ubnt,bullet-m-ar7240|\
ubnt,bullet-m-ar7241|\
ubnt,bullet-m-xw|\
ubnt,lap-120|\
ubnt,litebeam-ac-gen2|\
ubnt,nanobeam-ac|\
ubnt,nanobridge-m|\
ubnt,nanostation-ac-loco|\
ubnt,nanostation-loco-m|\
ubnt,nanostation-loco-m-xw|\
@ -80,6 +83,9 @@ ath79_setup_interfaces()
;;
buffalo,wzr-hp-ag300h|\
tplink,archer-c25-v1|\
tplink,archer-c60-v1|\
tplink,archer-c60-v2|\
tplink,archer-c60-v3|\
tplink,tl-wdr3500-v1|\
tplink,tl-wr842n-v1|\
tplink,tl-wr842n-v3|\
@ -106,9 +112,7 @@ ath79_setup_interfaces()
ubnt,routerstation)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;
comfast,cf-e560ac|\
tplink,archer-c60-v1|\
tplink,archer-c60-v2)
comfast,cf-e560ac)
ucidef_set_interface_wan "eth1"
ucidef_add_switch "switch0" \
"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan"
@ -123,6 +127,10 @@ ath79_setup_interfaces()
ocedo,ursus)
ucidef_set_interface_lan "eth0 eth1"
;;
devolo,magic-2-wifi)
ucidef_add_switch "switch0" \
"0@eth0" "2:wan" "3:lan" "4:lan"
;;
dlink,dir-825-b1)
ucidef_set_interface_wan "eth1"
ucidef_add_switch "switch0" \
@ -142,7 +150,8 @@ ath79_setup_interfaces()
"0@eth0" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5:wan"
;;
elecom,wrc-1750ghbk2-i|\
elecom,wrc-300ghbk2-i)
elecom,wrc-300ghbk2-i|\
sitecom,wlr-8100)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:4" "3:lan:3" "4:lan:2" "5:lan:1" "1:wan"
;;
@ -178,8 +187,6 @@ ath79_setup_interfaces()
;;
nec,wg1200cr|\
ubnt,nanostation-ac|\
ubnt,unifiac-mesh-pro|\
ubnt,unifiac-pro|\
yuncore,a782|\
yuncore,xd4200)
ucidef_add_switch "switch0" \
@ -232,7 +239,8 @@ ath79_setup_interfaces()
tplink,archer-c7-v5|\
tplink,tl-wdr3600-v1|\
tplink,tl-wdr4300-v1|\
tplink,tl-wdr4300-v1-il)
tplink,tl-wdr4300-v1-il|\
tplink,tl-wdr4310-v1)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:1" "3:lan:2" "4:lan:3" "5:lan:4" "1:wan"
;;
@ -247,6 +255,11 @@ ath79_setup_interfaces()
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:3" "3:lan:2" "4:lan:1" "1:wan"
;;
tplink,archer-d7-v1|\
tplink,archer-d7b-v1)
ucidef_add_switch "switch0" \
"0@eth1" "3:lan:3" "4:lan:2" "5:lan:1" "6@eth0" "2:wan:4" "1:wan:5"
;;
tplink,tl-mr6400-v1)
ucidef_set_interfaces_lan_wan "eth0.1 eth1" "usb0"
ucidef_add_switch "switch0" \
@ -295,6 +308,11 @@ ath79_setup_interfaces()
ucidef_add_switch "switch0" \
"0@eth0" "5:lan" "1:wan"
;;
ubnt,unifiac-mesh-pro|\
ubnt,unifiac-pro)
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:1" "3:lan:2"
;;
zbtlink,zbt-wd323|\
xiaomi,mi-router-4q)
ucidef_set_interface_wan "eth1"
@ -320,6 +338,10 @@ ath79_setup_macs()
alfa-network,ap121f)
label_mac=$(mtd_get_mac_binary art 0x1002)
;;
avm,fritz1750e|\
avm,fritz450e)
label_mac=$(fritz_tffs -n macwlan -i $(find_mtd_part "tffs (1)"))
;;
avm,fritz300e)
lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)"))
label_mac=$(fritz_tffs -n macwlan -i $(find_mtd_part "tffs (1)"))
@ -328,6 +350,9 @@ ath79_setup_macs()
lan_mac=$(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)"))
wan_mac=$(fritz_tffs -n macb -i $(find_mtd_part "tffs (1)"))
;;
devolo,magic-2-wifi)
label_mac=$(macaddr_add "$(mtd_get_mac_binary art 0x1002)" 3)
;;
dlink,dir-825-b1)
lan_mac=$(mtd_get_mac_text "caldata" 0xffa0)
wan_mac=$(mtd_get_mac_text "caldata" 0xffb4)
@ -407,7 +432,8 @@ ath79_setup_macs()
wan_mac=$(mtd_get_mac_binary factory 0x0)
lan_mac=$(macaddr_setbit_la "$wan_mac")
;;
sitecom,wlr-7100)
sitecom,wlr-7100|\
sitecom,wlr-8100)
lan_mac=$(mtd_get_mac_ascii u-boot-env ethaddr)
wan_mac=$(mtd_get_mac_ascii u-boot-env wanaddr)
label_mac=$lan_mac
@ -432,7 +458,9 @@ ath79_setup_macs()
label_mac=$wan_mac
;;
ubnt,airrouter|\
ubnt,bullet-m|\
ubnt,bullet-m-ar7240|\
ubnt,bullet-m-ar7241|\
ubnt,nanobridge-m|\
ubnt,nanostation-loco-m|\
ubnt,nanostation-m|\
ubnt,picostation-m|\

4
target/linux/ath79/generic/base-files/etc/board.d/03_gpio_switches
View File

@ -31,6 +31,10 @@ comfast,cf-e5)
ucidef_add_gpio_switch "lte_poweroff" "LTE Poweroff" "1" "1"
ucidef_add_gpio_switch "lte_reset" "LTE Reset" "12" "1"
;;
devolo,magic-2-wifi)
ucidef_add_gpio_switch "plc_pairing" "PLC pairing" "11" "1"
ucidef_add_gpio_switch "plc_enable" "PLC enable" "13" "1"
;;
dlink,dir-825-c1|\
dlink,dir-835-a1)
ucidef_add_gpio_switch "wan_led_auto" "WAN LED Auto" "20" "0"

13
target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
View File

@ -4,7 +4,6 @@
. /lib/functions.sh
. /lib/functions/system.sh
. /lib/functions/mikrotik-caldata.sh
ath9k_eeprom_die() {
echo "ath9k eeprom: " "$*"
@ -83,7 +82,9 @@ board=$(board_name)
case "$FIRMWARE" in
"ath9k-eeprom-ahb-18100000.wmac.bin")
case $board in
avm,fritz4020)
avm,fritz1750e|\
avm,fritz4020|\
avm,fritz450e)
ath9k_eeprom_extract_reverse "urlader" 0x1541 0x440
;;
dlink,dir-505|\
@ -114,10 +115,6 @@ case "$FIRMWARE" in
ath9k_eeprom_extract "art" 0x1000 0x440
ath9k_patch_fw_mac $(mtd_get_mac_ascii u-boot-env ethaddr) 0x2
;;
mikrotik,routerboard-wap-g-5hact2hnd)
mikrotik_caldata_extract "art" 0x1000 0x440
ath9k_patch_fw_mac $(macaddr_add $(mtd_get_mac_binary art 0x10) +2)
;;
nec,wg800hp)
ath9k_eeprom_extract "art" 0x1000 0x440
ath9k_patch_fw_mac $(mtd_get_mac_text board_data 0x680) 0x2
@ -162,7 +159,9 @@ case "$FIRMWARE" in
tplink,tl-wr2543-v1|\
tplink,tl-wr842n-v1|\
ubnt,airrouter|\
ubnt,bullet-m|\
ubnt,bullet-m-ar7240|\
ubnt,bullet-m-ar7241|\
ubnt,nanobridge-m|\
ubnt,nanostation-loco-m|\
ubnt,nanostation-m|\
ubnt,picostation-m|\

26
target/linux/ath79/generic/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
View File

@ -2,7 +2,6 @@
. /lib/functions.sh
. /lib/functions/k2t.sh
. /lib/functions/mikrotik-caldata.sh
ath10kcal_die() {
echo "ath10cal: " "$*"
@ -72,8 +71,12 @@ board=$(board_name)
case "$FIRMWARE" in
"ath10k/cal-pci-0000:00:00.0.bin")
case $board in
avm,fritz1750e)
ath10kcal_extract "urlader" 0x198a 0x844
;;
comfast,cf-wr650ac-v1|\
comfast,cf-wr650ac-v2|\
devolo,magic-2-wifi|\
ubnt,unifiac-lite|\
ubnt,unifiac-lr|\
ubnt,unifiac-mesh|\
@ -126,9 +129,6 @@ case "$FIRMWARE" in
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary art 0x0) +2)
;;
mikrotik,routerboard-wap-g-5hact2hnd)
mikrotik_caldata_extract "art" 0x5000 0x844
;;
nec,wg800hp)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac_crc $(mtd_get_mac_text board_data 0x880)
@ -163,6 +163,11 @@ case "$FIRMWARE" in
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary romfile 0xf100) +2)
;;
tplink,archer-d7-v1|\
tplink,archer-d7b-v1)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary romfs 0xf100) +2)
;;
tplink,re350k-v1)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_binary config 0x10008) +2)
@ -182,6 +187,14 @@ case "$FIRMWARE" in
;;
esac
;;
"ath10k/cal-pci-0000:01:00.0.bin")
case $board in
sitecom,wlr-8100)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) +1)
;;
esac
;;
"ath10k/pre-cal-pci-0000:00:00.0.bin")
case $board in
comfast,cf-e313ac)
@ -191,7 +204,9 @@ case "$FIRMWARE" in
/lib/firmware/ath10k/QCA9888/hw2.0/board.bin
rm /lib/firmware/ath10k/QCA9888/hw2.0/board-2.bin
;;
comfast,cf-e560ac)
comfast,cf-e560ac|\
comfast,cf-ew72|\
comfast,cf-wr752ac-v1)
ath10kcal_extract "art" 0x5000 0x2f20
ath10kcal_patch_mac_crc $(macaddr_add $(mtd_get_mac_binary art 0x0) +2)
ln -sf /lib/firmware/ath10k/pre-cal-pci-0000\:00\:00.0.bin \
@ -223,6 +238,7 @@ case "$FIRMWARE" in
tplink,archer-c59-v2|\
tplink,archer-c60-v1|\
tplink,archer-c60-v2|\
tplink,archer-c60-v3|\
tplink,archer-c6-v2|\
tplink,archer-c6-v2-us)
ath10kcal_extract "art" 0x5000 0x2f20

3
target/linux/ath79/generic/base-files/etc/uci-defaults/04_led_migration
View File

@ -24,7 +24,8 @@ tplink,tl-wr902ac-v1)
tplink,archer-c7-v2|\
tplink,tl-wdr3600-v1|\
tplink,tl-wdr4300-v1|\
tplink,tl-wdr4300-v1-il)
tplink,tl-wdr4300-v1-il|\
tplink,tl-wdr4310-v1)
migrate_leds ":blue:=:green:"
;;
tplink,re355-v1)

4
target/linux/ath79/generic/base-files/lib/preinit/10_fix_eth_mac.sh
View File

@ -4,6 +4,10 @@
preinit_set_mac_address() {
case $(board_name) in
avm,fritz1750e|\
avm,fritz450e)
ip link set dev eth0 address $(fritz_tffs -n maca -i $(find_mtd_part "tffs (1)"))
;;
siemens,ws-ap3610)
ip link set dev eth0 address $(mtd_get_mac_ascii cfg1 ethaddr)
;;

4
target/linux/ath79/generic/config-default
View File

@ -1,4 +1,5 @@
CONFIG_AT803X_PHY=y
CONFIG_BCM_NET_PHYLIB=y
CONFIG_BROADCOM_PHY=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
@ -7,10 +8,9 @@ CONFIG_IP17XX_PHY=y
CONFIG_LEDS_RESET=y
CONFIG_MARVELL_PHY=y
CONFIG_MICREL_PHY=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-3
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_SPLIT_EVA_FW=y
CONFIG_MTD_SPLIT_MINOR_FW=y
CONFIG_PHY_AR7100_USB=y
CONFIG_PHY_AR7200_USB=y
CONFIG_REGULATOR=y

2
target/linux/ath79/generic/target.mk
View File

@ -1,5 +1,5 @@
BOARDNAME:=Generic
FEATURES += minor squashfs
FEATURES += squashfs
DEFAULT_PACKAGES += wpad-basic

3
target/linux/ath79/image/Makefile
View File

@ -73,6 +73,9 @@ include ./generic.mk
include ./generic-tp-link.mk
include ./generic-ubnt.mk
endif
ifeq ($(SUBTARGET),mikrotik)
include ./mikrotik.mk
endif
ifeq ($(SUBTARGET),nand)
include ./nand.mk
endif

51
target/linux/ath79/image/generic-tp-link.mk
View File

@ -135,6 +135,17 @@ define Device/tplink_archer-c60-v2
endef
TARGET_DEVICES += tplink_archer-c60-v2
define Device/tplink_archer-c60-v3
$(Device/tplink-safeloader-uimage)
SOC := qca9561
IMAGE_SIZE := 7808k
DEVICE_MODEL := Archer C60
DEVICE_VARIANT := v3
TPLINK_BOARD_ID := ARCHER-C60-V3
DEVICE_PACKAGES := kmod-ath10k-ct-smallbuffers ath10k-firmware-qca9888-ct
endef
TARGET_DEVICES += tplink_archer-c60-v3
define Device/tplink_archer-c7-v1
$(Device/tplink-8mlzma)
SOC := qca9558
@ -206,6 +217,35 @@ define Device/tplink_archer-d50-v1
endef
TARGET_DEVICES += tplink_archer-d50-v1
define Device/tplink_archer-d7-v1
$(Device/tplink-v2)
SOC := qca9558
DEVICE_MODEL := Archer D7
DEVICE_VARIANT := v1
DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport \
kmod-ath10k-ct ath10k-firmware-qca988x-ct
IMAGE_SIZE := 15936k
TPLINK_HWID := 0x89300001
TPLINK_HWREV := 0x0000002D
TPLINK_FLASHLAYOUT := 16Mqca
TPLINK_HWREVADD := 0x00000002
endef
TARGET_DEVICES += tplink_archer-d7-v1
define Device/tplink_archer-d7b-v1
$(Device/tplink-v2)
SOC := qca9558
DEVICE_MODEL := Archer D7b
DEVICE_VARIANT := v1
DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport \
kmod-ath10k-ct ath10k-firmware-qca988x-ct
IMAGE_SIZE := 16000k
TPLINK_HWID := 0x89300001
TPLINK_HWREV := 0x0000003D
TPLINK_FLASHLAYOUT := 16Mqca
endef
TARGET_DEVICES += tplink_archer-d7b-v1
define Device/tplink_cpe210-v1
$(Device/tplink-safeloader-okli)
SOC := ar9344
@ -416,6 +456,17 @@ define Device/tplink_tl-wdr4300-v1-il
endef
TARGET_DEVICES += tplink_tl-wdr4300-v1-il
define Device/tplink_tl-wdr4310-v1
$(Device/tplink-8mlzma)
SOC := ar9344
DEVICE_MODEL := TL-WDR4310
DEVICE_VARIANT := v1
DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport
TPLINK_HWID := 0x43100001
SUPPORTED_DEVICES += tl-wdr4300
endef
TARGET_DEVICES += tplink_tl-wdr4310-v1
define Device/tplink_tl-wdr4900-v2
$(Device/tplink-8mlzma)
SOC := qca9558

31
target/linux/ath79/image/generic-ubnt.mk
View File

@ -71,7 +71,6 @@ endef
define Device/ubnt-xm
$(Device/ubnt)
SOC := ar7241
DEVICE_VARIANT := XM
DEVICE_PACKAGES += kmod-usb-ohci
IMAGE_SIZE := 7448k
@ -108,18 +107,31 @@ TARGET_DEVICES += ubnt_acb-isp
define Device/ubnt_airrouter
$(Device/ubnt-xm)
SOC := ar7241
DEVICE_MODEL := AirRouter
SUPPORTED_DEVICES += airrouter
endef
TARGET_DEVICES += ubnt_airrouter
define Device/ubnt_bullet-m
define Device/ubnt_bullet-m-ar7240
$(Device/ubnt-xm)
SOC := ar7240
DEVICE_MODEL := Bullet-M
DEVICE_VARIANT := XM (AR7240)
DEVICE_PACKAGES += rssileds
SUPPORTED_DEVICES += bullet-m
endef
TARGET_DEVICES += ubnt_bullet-m
TARGET_DEVICES += ubnt_bullet-m-ar7240
define Device/ubnt_bullet-m-ar7241
$(Device/ubnt-xm)
SOC := ar7241
DEVICE_MODEL := Bullet-M
DEVICE_VARIANT := XM (AR7241)
DEVICE_PACKAGES += rssileds
SUPPORTED_DEVICES += bullet-m ubnt,bullet-m
endef
TARGET_DEVICES += ubnt_bullet-m-ar7241
define Device/ubnt_bullet-m-xw
$(Device/ubnt-xw)
@ -165,6 +177,15 @@ define Device/ubnt_nanobeam-ac
endef
TARGET_DEVICES += ubnt_nanobeam-ac
define Device/ubnt_nanobridge-m
$(Device/ubnt-xm)
SOC := ar7241
DEVICE_MODEL := NanoBridge M
DEVICE_PACKAGES += rssileds
SUPPORTED_DEVICES += bullet-m
endef
TARGET_DEVICES += ubnt_nanobridge-m
define Device/ubnt_nanostation-ac
$(Device/ubnt-wa)
DEVICE_MODEL := Nanostation AC
@ -181,6 +202,7 @@ TARGET_DEVICES += ubnt_nanostation-ac-loco
define Device/ubnt_nanostation-loco-m
$(Device/ubnt-xm)
SOC := ar7241
DEVICE_MODEL := Nanostation Loco M
DEVICE_PACKAGES += rssileds
SUPPORTED_DEVICES += bullet-m
@ -197,6 +219,7 @@ TARGET_DEVICES += ubnt_nanostation-loco-m-xw
define Device/ubnt_nanostation-m
$(Device/ubnt-xm)
SOC := ar7241
DEVICE_MODEL := Nanostation M
DEVICE_PACKAGES += rssileds
SUPPORTED_DEVICES += nanostation-m
@ -213,6 +236,7 @@ TARGET_DEVICES += ubnt_nanostation-m-xw
define Device/ubnt_picostation-m
$(Device/ubnt-xm)
SOC := ar7241
DEVICE_MODEL := Picostation M
DEVICE_PACKAGES += rssileds
SUPPORTED_DEVICES += bullet-m
@ -221,6 +245,7 @@ TARGET_DEVICES += ubnt_picostation-m
define Device/ubnt_rocket-m
$(Device/ubnt-xm)
SOC := ar7241
DEVICE_MODEL := Rocket-M
DEVICE_PACKAGES += rssileds
SUPPORTED_DEVICES += rocket-m

124
target/linux/ath79/image/generic.mk
View File

@ -1,5 +1,4 @@
include ./common-buffalo.mk
include ./common-mikrotik.mk
include ./common-netgear.mk
include ./common-tp-link.mk
include ./common-yuncore.mk
@ -159,40 +158,58 @@ define Device/aruba_ap-105
DEVICE_VENDOR := Aruba
DEVICE_MODEL := AP-105
IMAGE_SIZE := 16000k
DEVICE_PACKAGES := kmod-i2c-core kmod-i2c-gpio kmod-tpm-i2c-atmel
DEVICE_PACKAGES := kmod-i2c-gpio kmod-tpm-i2c-atmel
endef
TARGET_DEVICES += aruba_ap-105
define Device/avm_fritz300e
SOC := ar7242
define Device/avm
DEVICE_VENDOR := AVM
DEVICE_MODEL := FRITZ!WLAN Repeater 300E
KERNEL := kernel-bin | append-dtb | lzma | eva-image
KERNEL_INITRAMFS := $$(KERNEL)
IMAGE_SIZE := 15232k
IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | \
append-squashfs-fakeroot-be | pad-to 256 | append-rootfs | pad-rootfs | \
append-metadata | check-size $$$$(IMAGE_SIZE)
DEVICE_PACKAGES := fritz-tffs rssileds -swconfig
SUPPORTED_DEVICES += fritz300e
endef
TARGET_DEVICES += avm_fritz300e
define Device/avm_fritz4020
SOC := qca9561
DEVICE_VENDOR := AVM
DEVICE_MODEL := FRITZ!Box 4020
IMAGE_SIZE := 15232k
KERNEL := kernel-bin | append-dtb | lzma | eva-image
KERNEL_INITRAMFS := $$(KERNEL)
IMAGE/sysupgrade.bin := append-kernel | pad-to 64k | \
append-squashfs-fakeroot-be | pad-to 256 | append-rootfs | pad-rootfs | \
append-metadata | check-size $$$$(IMAGE_SIZE)
DEVICE_PACKAGES := fritz-tffs
endef
define Device/avm_fritz1750e
$(Device/avm)
SOC := qca9556
IMAGE_SIZE := 15232k
DEVICE_MODEL := FRITZ!WLAN Repeater 1750E
DEVICE_PACKAGES += rssileds kmod-ath10k-ct-smallbuffers \
ath10k-firmware-qca988x-ct -swconfig
endef
TARGET_DEVICES += avm_fritz1750e
define Device/avm_fritz300e
$(Device/avm)
SOC := ar7242
IMAGE_SIZE := 15232k
DEVICE_MODEL := FRITZ!WLAN Repeater 300E
DEVICE_PACKAGES += rssileds -swconfig
SUPPORTED_DEVICES += fritz300e
endef
TARGET_DEVICES += avm_fritz300e
define Device/avm_fritz4020
$(Device/avm)
SOC := qca9561
IMAGE_SIZE := 15232k
DEVICE_MODEL := FRITZ!Box 4020
SUPPORTED_DEVICES += fritz4020
endef
TARGET_DEVICES += avm_fritz4020
define Device/avm_fritz450e
$(Device/avm)
SOC := qca9556
IMAGE_SIZE := 15232k
DEVICE_MODEL := FRITZ!WLAN Repeater 450E
SUPPORTED_DEVICES += fritz450e
endef
TARGET_DEVICES += avm_fritz450e
define Device/buffalo_bhr-4grv
SOC := ar7242
DEVICE_VENDOR := Buffalo
@ -327,6 +344,16 @@ define Device/comfast_cf-e560ac
endef
TARGET_DEVICES += comfast_cf-e560ac
define Device/comfast_cf-ew72
SOC := qca9531
DEVICE_VENDOR := COMFAST
DEVICE_MODEL := CF-EW72
DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9888-ct \
-uboot-envtools -swconfig
IMAGE_SIZE := 16192k
endef
TARGET_DEVICES += comfast_cf-ew72
define Device/comfast_cf-wr650ac-v1
SOC := qca9558
DEVICE_VENDOR := COMFAST
@ -347,6 +374,17 @@ define Device/comfast_cf-wr650ac-v2
endef
TARGET_DEVICES += comfast_cf-wr650ac-v2
define Device/comfast_cf-wr752ac-v1
SOC := qca9531
DEVICE_VENDOR := COMFAST
DEVICE_MODEL := CF-WR752AC
DEVICE_VARIANT := v1
DEVICE_PACKAGES := kmod-usb2 kmod-ath10k-ct ath10k-firmware-qca9888-ct \
-uboot-envtools
IMAGE_SIZE := 16192k
endef
TARGET_DEVICES += comfast_cf-wr752ac-v1
define Device/devolo_dvl1200e
SOC := qca9558
DEVICE_VENDOR := devolo
@ -401,6 +439,15 @@ define Device/devolo_dvl1750x
endef
TARGET_DEVICES += devolo_dvl1750x
define Device/devolo_magic-2-wifi
SOC := ar9344
DEVICE_VENDOR := Devolo
DEVICE_MODEL := Magic 2 WiFi
DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct
IMAGE_SIZE := 15872k
endef
TARGET_DEVICES += devolo_magic-2-wifi
define Device/dlink_dir-505
SOC := ar9330
DEVICE_VENDOR := D-Link
@ -756,19 +803,6 @@ define Device/librerouter_librerouter-v1
endef
TARGET_DEVICES += librerouter_librerouter-v1
define Device/mikrotik_routerboard-wap-g-5hact2hnd
$(Device/mikrotik)
SOC := qca9556
DEVICE_MODEL := RouterBOARD wAP G-5HacT2HnD (wAP AC)
IMAGE_SIZE := 16256k
IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 -e | \
pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \
append-metadata | check-size $$$$(IMAGE_SIZE)
DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct
SUPPORTED_DEVICES += rb-wapg-5hact2hnd
endef
TARGET_DEVICES += mikrotik_routerboard-wap-g-5hact2hnd
define Device/nec_wg1200cr
SOC := qca9563
DEVICE_VENDOR := NEC
@ -1012,7 +1046,7 @@ define Device/pisen_wmb001n
DEVICE_VENDOR := PISEN
DEVICE_MODEL := WMB001N
IMAGE_SIZE := 14080k
DEVICE_PACKAGES := kmod-i2c-core kmod-i2c-gpio kmod-usb2
DEVICE_PACKAGES := kmod-i2c-gpio kmod-usb2
LOADER_TYPE := bin
LOADER_FLASH_OFFS := 0x20000
COMPILE := loader-$(1).bin loader-$(1).uImage
@ -1086,6 +1120,22 @@ define Device/sitecom_wlr-7100
endef
TARGET_DEVICES += sitecom_wlr-7100
define Device/sitecom_wlr-8100
SOC := qca9558
DEVICE_VENDOR := Sitecom
DEVICE_MODEL := WLR-8100
DEVICE_ALT0_VENDOR := Sitecom
DEVICE_ALT0_MODEL := X8 AC1750
DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct kmod-usb2 kmod-usb3
SUPPORTED_DEVICES += wlr8100
IMAGES += factory.dlf
IMAGE/factory.dlf := append-kernel | pad-to $$$$(BLOCKSIZE) | \
append-rootfs | pad-rootfs | check-size $$$$(IMAGE_SIZE) | \
senao-header -r 0x222 -p 0x56 -t 2
IMAGE_SIZE := 15424k
endef
TARGET_DEVICES += sitecom_wlr-8100
define Device/teltonika_rut955
SOC := ar9344
DEVICE_VENDOR := Teltonika
@ -1157,7 +1207,7 @@ define Device/winchannel_wb2000
DEVICE_VENDOR := Winchannel
DEVICE_MODEL := WB2000
IMAGE_SIZE := 15872k
DEVICE_PACKAGES := kmod-i2c-core kmod-i2c-gpio kmod-rtc-ds1307 kmod-usb2 \
DEVICE_PACKAGES := kmod-i2c-gpio kmod-rtc-ds1307 kmod-usb2 \
kmod-usb-ledtrig-usbport
endef
TARGET_DEVICES += winchannel_wb2000
@ -1208,7 +1258,7 @@ define Device/zbtlink_zbt-wd323
DEVICE_VENDOR := ZBT
DEVICE_MODEL := WD323
IMAGE_SIZE := 16000k
DEVICE_PACKAGES := kmod-usb2 kmod-i2c-core kmod-i2c-gpio kmod-rtc-pcf8563 \
DEVICE_PACKAGES := kmod-usb2 kmod-i2c-gpio kmod-rtc-pcf8563 \
kmod-usb-serial kmod-usb-serial-cp210x uqmi
endef
TARGET_DEVICES += zbtlink_zbt-wd323

26
target/linux/ath79/image/mikrotik.mk Normal file
View File

@ -0,0 +1,26 @@
include ./common-mikrotik.mk
define Device/mikrotik_routerboard-922uags-5hpacd
$(Device/mikrotik)
SOC := qca9558
DEVICE_MODEL := RouterBOARD 922UAGS-5HPacD
IMAGE/sysupgrade.bin = append-kernel | kernel2minor -s 2048 -e -c | \
sysupgrade-tar kernel=$$$$@ | append-metadata
DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct \
kmod-usb2 nand-utils
SUPPORTED_DEVICES += rb-922uags-5hpacd
endef
TARGET_DEVICES += mikrotik_routerboard-922uags-5hpacd
define Device/mikrotik_routerboard-wap-g-5hact2hnd
$(Device/mikrotik)
SOC := qca9556
DEVICE_MODEL := RouterBOARD wAP G-5HacT2HnD (wAP AC)
IMAGE_SIZE := 16256k
IMAGE/sysupgrade.bin := append-kernel | kernel2minor -s 1024 -e | \
pad-to $$$$(BLOCKSIZE) | append-rootfs | pad-rootfs | \
append-metadata | check-size $$$$(IMAGE_SIZE)
DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct
SUPPORTED_DEVICES += rb-wapg-5hact2hnd
endef
TARGET_DEVICES += mikrotik_routerboard-wap-g-5hact2hnd

23
target/linux/ath79/image/nand.mk
View File

@ -1,5 +1,7 @@
include ./common-netgear.mk # for netgear-uImage
DEVICE_VARS += RAS_ROOTFS_SIZE RAS_BOARD RAS_VERSION
# attention: only zlib compression is allowed for the boot fs
define Build/zyxel-buildkerneljffs
rm -rf $(KDIR_TMP)/zyxelnbg6716
@ -46,6 +48,24 @@ define Device/aerohive_hiveap-121
endef
TARGET_DEVICES += aerohive_hiveap-121
define Device/domywifi_dw33d
SOC := qca9558
DEVICE_VENDOR := DomyWifi
DEVICE_MODEL := DW33D
DEVICE_PACKAGES := kmod-usb2 kmod-usb-storage kmod-usb-ledtrig-usbport \
kmod-ath10k-ct ath10k-firmware-qca988x-ct
KERNEL_SIZE := 5120k
IMAGE_SIZE := 98304k
BLOCKSIZE := 128k
PAGESIZE := 2048
UBINIZE_OPTS := -E 5
IMAGES += factory.bin
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | \
check-size $$$$(IMAGE_SIZE)
endef
TARGET_DEVICES += domywifi_dw33d
define Device/glinet_gl-ar300m-common-nand
SOC := qca9531
DEVICE_VENDOR := GL.iNet
@ -96,7 +116,7 @@ define Device/glinet_gl-ar750s-nor-nand
GL_UBOOT_UBI_OFFSET := 2048k
IMAGES += factory.img
IMAGE/factory.img := append-kernel | pad-to $$$$(GL_UBOOT_UBI_OFFSET) | \
append-ubi | check-kernel-size $$$$(GL_UBOOT_UBI_OFFSET)
append-ubi | check-kernel-size $$$$(GL_UBOOT_UBI_OFFSET)
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
SUPPORTED_DEVICES += glinet,gl-ar750s-nor
endef
@ -198,4 +218,3 @@ define Device/zyxel_nbg6716
UBINIZE_OPTS := -E 5
endef
TARGET_DEVICES += zyxel_nbg6716
DEVICE_VARS += RAS_ROOTFS_SIZE RAS_BOARD RAS_VERSION

30
target/linux/ath79/image/tiny-tp-link.mk
View File

@ -66,6 +66,16 @@ define Device/tplink_tl-mr3420-v2
endef
TARGET_DEVICES += tplink_tl-mr3420-v2
define Device/tplink_tl-mr3420-v3
$(Device/tplink-4mlzma)
SOC := qca9531
DEVICE_MODEL := TL-MR3420
DEVICE_VARIANT := v3
TPLINK_HWID := 0x34200003
DEVICE_PACKAGES := kmod-usb2 kmod-usb-ledtrig-usbport
endef
TARGET_DEVICES += tplink_tl-mr3420-v3
define Device/tplink_tl-wa701nd-v1
$(Device/tplink-4m)
SOC := ar7240
@ -130,6 +140,16 @@ define Device/tplink_tl-wa850re-v2
endef
TARGET_DEVICES += tplink_tl-wa850re-v2
define Device/tplink_tl-wa860re-v1
$(Device/tplink-4mlzma)
SOC := ar9341
DEVICE_MODEL := TL-WA860RE
DEVICE_VARIANT := v1
TPLINK_HWID := 0x08600001
SUPPORTED_DEVICES += tl-wa860re
endef
TARGET_DEVICES += tplink_tl-wa860re-v1
define Device/tplink_tl-wa901nd-v1
$(Device/tplink-4m)
SOC := ar7240
@ -146,6 +166,7 @@ define Device/tplink_tl-wa901nd-v2
DEVICE_MODEL := TL-WA901ND
DEVICE_VARIANT := v2
TPLINK_HWID := 0x09010002
SUPPORTED_DEVICES += tl-wa901nd-v2
endef
TARGET_DEVICES += tplink_tl-wa901nd-v2
@ -186,6 +207,15 @@ define Device/tplink_tl-wr740n-v4
endef
TARGET_DEVICES += tplink_tl-wr740n-v4
define Device/tplink_tl-wr740n-v5
$(Device/tplink-4mlzma)
SOC := ar9331
DEVICE_MODEL := TL-WR740N
DEVICE_VARIANT := v5
TPLINK_HWID := 0x07400005
endef
TARGET_DEVICES += tplink_tl-wr740n-v5
define Device/tplink_tl-wr741-v1
$(Device/tplink-4m)
SOC := ar7240

39
target/linux/ath79/mikrotik/base-files/etc/board.d/02_network Executable file
View File

@ -0,0 +1,39 @@
#!/bin/sh
. /lib/functions/system.sh
. /lib/functions/uci-defaults.sh
ath79_setup_interfaces()
{
local board="$1"
case "$board" in
mikrotik,routerboard-922uags-5hpacd|\
mikrotik,routerboard-wap-g-5hact2hnd)
ucidef_set_interface_lan "eth0"
;;
*)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
esac
}
ath79_setup_macs()
{
local board="$1"
case "$board" in
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
[ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
[ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
}
board_config_update
board=$(board_name)
ath79_setup_interfaces $board
ath79_setup_macs $board
board_config_flush
exit 0

54
target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom Normal file
View File

@ -0,0 +1,54 @@
#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
. /lib/functions/mikrotik-caldata.sh
ath9k_eeprom_die() {
echo "ath9k eeprom: " "$*"
exit 1
}
ath9k_patch_fw_mac() {
local mac=$1
local mac_offset=$(($2))
local chksum_offset=$3
local xor_mac
local xor_fw_mac
local xor_fw_chksum
[ -z "$mac" -o -z "$mac_offset" ] && return
[ -n "$chksum_offset" ] && {
xor_mac=${mac//:/}
xor_mac="${xor_mac:0:4} ${xor_mac:4:4} ${xor_mac:8:4}"
xor_fw_mac=$(hexdump -v -n 6 -s $mac_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE)
xor_fw_mac="${xor_fw_mac:0:4} ${xor_fw_mac:4:4} ${xor_fw_mac:8:4}"
xor_fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE)
xor_fw_chksum=$(xor $xor_fw_chksum $xor_fw_mac $xor_mac)
printf "%b" "\x${xor_fw_chksum:0:2}\x${xor_fw_chksum:2:2}" | \
dd of=/lib/firmware/$FIRMWARE conv=notrunc bs=1 seek=$(($chksum_offset)) count=2
}
macaddr_2bin $mac | dd of=/lib/firmware/$FIRMWARE conv=notrunc oflag=seek_bytes bs=6 seek=$mac_offset count=1
}
board=$(board_name)
case "$FIRMWARE" in
"ath9k-eeprom-ahb-18100000.wmac.bin")
case $board in
mikrotik,routerboard-wap-g-5hact2hnd)
mikrotik_caldata_extract "art" 0x1000 0x440
ath9k_patch_fw_mac $(macaddr_add $(mtd_get_mac_binary art 0x10) +2)
;;
*)
ath9k_eeprom_die "board $board is not supported yet"
;;
esac
;;
esac

28
target/linux/ath79/mikrotik/base-files/etc/hotplug.d/firmware/11-ath10k-caldata Normal file
View File

@ -0,0 +1,28 @@
#!/bin/sh
[ -e /lib/firmware/$FIRMWARE ] && exit 0
. /lib/functions/caldata.sh
. /lib/functions/mikrotik-caldata.sh
board=$(board_name)
case "$FIRMWARE" in
"ath10k/cal-pci-0000:00:00.0.bin")
case $board in
mikrotik,routerboard-wap-g-5hact2hnd)
mikrotik_caldata_extract "hard_config" 0x5000 0x844
;;
esac
;;
"ath10k/cal-pci-0000:01:00.0.bin")
case $board in
mikrotik,routerboard-922uags-5hpacd)
mikrotik_caldata_extract "hard_config" 0x5000 0x844
;;
esac
;;
*)
exit 1
;;
esac

17
target/linux/ath79/mikrotik/base-files/etc/uci-defaults/04_led_migration Normal file
View File

@ -0,0 +1,17 @@
#!/bin/sh
. /lib/functions.sh
. /lib/functions/migrations.sh
board=$(board_name)
boardonly="${board##*,}"
case "$board" in
mikrotik,*)
migrate_leds "^rb:=mikrotik:"
;;
esac
migrations_apply system
exit 0

9
target/linux/ath79/base-files/lib/functions/mikrotik-caldata.sh → target/linux/ath79/mikrotik/base-files/lib/functions/mikrotik-caldata.sh
View File

@ -9,13 +9,18 @@ mikrotik_caldata_extract() {
local offset=$(($2))
local count=$(($3))
local mtd
local erdfile="/lib/firmware/erd.bin"
local erdfile="/tmp/erd.bin"
local fwfile="/lib/firmware/${FIRMWARE}"
[ -e $fwfile ] && exit 0
mtd=$(find_mtd_chardev $part)
[ -n "$mtd" ] || caldata_die "no mtd device found for partition $part"
rbextract -e $mtd $erdfile
dd if=$erdfile of=/lib/firmware/$FIRMWARE iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \
dd if=$erdfile of=$fwfile iflag=skip_bytes bs=$count skip=$offset count=1 2>/dev/null || \
caldata_die "failed to extract calibration data from $mtd"
rm -f $erdfile
}

41
target/linux/ath79/mikrotik/base-files/lib/upgrade/platform.sh Normal file
View File

@ -0,0 +1,41 @@
# Copyright (C) 2011 OpenWrt.org
PART_NAME=firmware
REQUIRE_IMAGE_METADATA=1
platform_check_image() {
return 0
}
RAMFS_COPY_BIN='fw_printenv fw_setenv nandwrite'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
platform_do_upgrade_mikrotik_nand() {
CI_KERNPART=none
local fw_mtd=$(find_mtd_part kernel)
fw_mtd="${fw_mtd/block/}"
[ -n "$fw_mtd" ] || return
local board_dir=$(tar tf "$1" | grep -m 1 '^sysupgrade-.*/$')
board_dir=${board_dir%/}
[ -n "$board_dir" ] || return
mtd erase kernel
tar xf "$1" ${board_dir}/kernel -O | nandwrite -o "$fw_mtd" -
nand_do_upgrade "$1"
}
platform_do_upgrade() {
local board=$(board_name)
case "$board" in
mikrotik,routerboard-922uags-5hpacd)
platform_do_upgrade_mikrotik_nand "$1"
;;
*)
default_do_upgrade "$1"
;;
esac
}

34
target/linux/ath79/mikrotik/config-default Normal file
View File

@ -0,0 +1,34 @@
CONFIG_AT803X_PHY=y
CONFIG_CRC16=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_GPIO_LATCH=y
CONFIG_GPIO_WATCHDOG=y
CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
CONFIG_LEDS_RESET=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_AR934X=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_MTD_SPLIT_MINOR_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
CONFIG_NET_SWITCHDEV=y
CONFIG_PHY_AR7100_USB=y
CONFIG_PHY_AR7200_USB=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
CONFIG_WATCHDOG_CORE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

18
target/linux/ath79/mikrotik/profiles/00-default.mk Normal file
View File

@ -0,0 +1,18 @@
#
# Copyright (C) 2020 OpenWrt.org
#
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
define Profile/Default
NAME:=Default Profile (all drivers)
PACKAGES:= \
kmod-usb-ohci kmod-usb2 nand-utils
PRIORITY := 1
endef
define Profile/Default/Description
Default package set compatible with most boards.
endef
$(eval $(call Profile,Default))

9
target/linux/ath79/mikrotik/target.mk Normal file
View File

@ -0,0 +1,9 @@
BOARDNAME := MikroTik devices
FEATURES += minor nand squashfs
DEFAULT_PACKAGES += wpad-basic
define Target/Description
Build firmware images for MikroTik devices based on Qualcomm Atheros
MIPS SoCs (AR71xx, AR72xx, AR91xx, AR93xx, QCA95xx).
endef

8
target/linux/ath79/nand/base-files/etc/board.d/02_network
View File

@ -11,6 +11,10 @@ ath79_setup_interfaces()
aerohive,hiveap-121)
ucidef_set_interface_lan "eth0"
;;
domywifi,dw33d)
ucidef_add_switch "switch0" \
"0@eth0" "1:wan" "2:lan" "3:lan" "4:lan" "5:lan" "6@eth1"
;;
glinet,gl-ar750s-nor|\
glinet,gl-ar750s-nor-nand)
ucidef_add_switch "switch0" \
@ -44,10 +48,6 @@ ath79_setup_macs()
netgear,wndr4500-v3)
wan_mac=$(mtd_get_mac_binary caldata 0x6)
;;
zyxel,nbg6716)
lan_mac=$(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) +2)
wan_mac=$(macaddr_add $(mtd_get_mac_ascii u-boot-env ethaddr) +3)
;;
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac

4
target/linux/ath79/nand/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
View File

@ -32,6 +32,10 @@ board=$(board_name)
case "$FIRMWARE" in
"ath10k/cal-pci-0000:00:00.0.bin")
case $board in
domywifi,dw33d)
ath10kcal_extract "art" 0x5000 0x844
ath10kcal_patch_mac $(mtd_get_mac_binary art 0x12)
;;
glinet,gl-ar750s-nor|\
glinet,gl-ar750s-nor-nand)
ath10kcal_extract "art" 0x5000 0x844

18
target/linux/ath79/nand/base-files/etc/hotplug.d/ieee80211/10-fix-wifi-mac Normal file
View File

@ -0,0 +1,18 @@
[ "$ACTION" = "add" ] || exit 0
PHYNBR=${DEVPATH##*/phy}
[ -n $PHYNBR ] || exit 0
. /lib/functions.sh
. /lib/functions/system.sh
board=$(board_name)
case $board in
zyxel,nbg6716)
# Set mac address for 2.4g device
[ "$PHYNBR" -eq 1 ] && \
mtd_get_mac_ascii u-boot-env ethaddr > /sys${DEVPATH}/macaddress
;;
esac

14
target/linux/ath79/nand/base-files/lib/preinit/10_fix_eth_mac.sh Normal file
View File

@ -0,0 +1,14 @@
. /lib/functions.sh
. /lib/functions/system.sh
preinit_set_mac_address() {
case $(board_name) in
zyxel,nbg6716)
ethaddr=$(mtd_get_mac_ascii u-boot-env ethaddr)
ip link set dev eth0 address $(macaddr_add $ethaddr 2)
ip link set dev eth1 address $(macaddr_add $ethaddr 3)
;;
esac
}
boot_hook_add preinit_main preinit_set_mac_address

2
target/linux/ath79/nand/base-files/lib/upgrade/platform.sh
View File

@ -7,7 +7,7 @@ platform_check_image() {
return 0
}
RAMFS_COPY_BIN='fw_printenv fw_setenv'
RAMFS_COPY_BIN='fw_printenv fw_setenv nandwrite'
RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock'
platform_do_upgrade() {

18
target/linux/ath79/nand/config-default
View File

@ -1,18 +1,28 @@
CONFIG_CRC16=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_LZO=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_AR934X=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
# CONFIG_MTD_UBI_FASTMAP is not set
# CONFIG_MTD_UBI_GLUEBI is not set
CONFIG_MTD_UBI_WL_THRESHOLD=4096
# CONFIG_PCI_AR71XX is not set
# CONFIG_PHY_AR7100_USB is not set
CONFIG_PHY_AR7200_USB=y
CONFIG_SGL_ALLOC=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
CONFIG_UBIFS_FS_ZLIB=y
# CONFIG_UBIFS_FS_ZSTD is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

21
target/linux/ath79/patches-4.14/0001-tty-serial-drop-QCA-pecific-SoC-symbols.patch
View File

@ -1,21 +0,0 @@
From 58812f6d0f1e11b03ed266038ed3b7274ab6f121 Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 09:26:32 +0100
Subject: [PATCH 01/27] tty: serial: drop QCA pecific SoC symbols
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/tty/serial/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1463,7 +1463,7 @@ config SERIAL_XILINX_PS_UART_CONSOLE
config SERIAL_AR933X
tristate "AR933X serial port support"
- depends on HAVE_CLK && SOC_AR933X
+ depends on HAVE_CLK && ATH79
select SERIAL_CORE
help
If you have an Atheros AR933X SOC based board and want to use the

51
target/linux/ath79/patches-4.14/0006-usb-drop-deprecated-symbols.patch
View File

@ -1,51 +0,0 @@
From bd17da5b6297e0e52b787049292d076ad415362a Mon Sep 17 00:00:00 2001
From: John Crispin <john@phrozen.org>
Date: Tue, 6 Mar 2018 10:04:54 +0100
Subject: [PATCH 06/27] usb: drop deprecated symbols
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/usb/host/Kconfig | 25 -------------------------
1 file changed, 25 deletions(-)
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -297,19 +297,6 @@ config USB_CNS3XXX_EHCI
It is needed for high-speed (480Mbit/sec) USB 2.0 device
support.
-config USB_EHCI_ATH79
- bool "EHCI support for AR7XXX/AR9XXX SoCs (DEPRECATED)"
- depends on (SOC_AR71XX || SOC_AR724X || SOC_AR913X || SOC_AR933X)
- select USB_EHCI_ROOT_HUB_TT
- select USB_EHCI_HCD_PLATFORM
- default y
- ---help---
- This option is deprecated now and the driver was removed, use
- USB_EHCI_HCD_PLATFORM instead.
-
- Enables support for the built-in EHCI controller present
- on the Atheros AR7XXX/AR9XXX SoCs.
-
config USB_EHCI_HCD_PLATFORM
tristate "Generic EHCI driver for a platform device"
default n
@@ -493,18 +480,6 @@ config USB_OHCI_HCD_DAVINCI
controller. This driver cannot currently be a loadable
module because it lacks a proper PHY abstraction.
-config USB_OHCI_ATH79
- bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs (DEPRECATED)"
- depends on (SOC_AR71XX || SOC_AR724X)
- select USB_OHCI_HCD_PLATFORM
- default y
- help
- This option is deprecated now and the driver was removed, use
- USB_OHCI_HCD_PLATFORM instead.
-
- Enables support for the built-in OHCI controller present on the
- Atheros AR71XX/AR7240 SoCs.
-
config USB_OHCI_HCD_PPC_OF_BE
bool "OHCI support for OF platform bus (big endian)"
depends on PPC

980
target/linux/ath79/patches-4.14/0009-MIPS-ath79-add-lots-of-missing-registers.patch
View File

@ -1,980 +0,0 @@
From e93fe20529aeb8738b87533f66c46e2c21524530 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Tue, 6 Mar 2018 10:06:10 +0100
Subject: [PATCH 09/33] MIPS: ath79: add lots of missing registers
This patch adds many new registers for various QCA MIPS SoCs. The patch is
an aggragate of many contributions made to OpenWrt.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: Henryk Heisig <hyniu@o2.pl>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Julien Dusser <julien.dusser@free.fr>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 771 ++++++++++++++++++++++++-
1 file changed, 770 insertions(+), 1 deletion(-)
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -20,6 +20,10 @@
#include <linux/bitops.h>
#define AR71XX_APB_BASE 0x18000000
+#define AR71XX_GE0_BASE 0x19000000
+#define AR71XX_GE0_SIZE 0x10000
+#define AR71XX_GE1_BASE 0x1a000000
+#define AR71XX_GE1_SIZE 0x10000
#define AR71XX_EHCI_BASE 0x1b000000
#define AR71XX_EHCI_SIZE 0x1000
#define AR71XX_OHCI_BASE 0x1c000000
@@ -39,6 +43,8 @@
#define AR71XX_PLL_SIZE 0x100
#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
#define AR71XX_RESET_SIZE 0x100
+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
+#define AR71XX_MII_SIZE 0x100
#define AR71XX_PCI_MEM_BASE 0x10000000
#define AR71XX_PCI_MEM_SIZE 0x07000000
@@ -81,18 +87,39 @@
#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
#define AR933X_UART_SIZE 0x14
+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define AR933X_GMAC_SIZE 0x04
#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define AR933X_WMAC_SIZE 0x20000
#define AR933X_EHCI_BASE 0x1b000000
#define AR933X_EHCI_SIZE 0x1000
+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define AR934X_GMAC_SIZE 0x14
#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define AR934X_WMAC_SIZE 0x20000
#define AR934X_EHCI_BASE 0x1b000000
#define AR934X_EHCI_SIZE 0x200
+#define AR934X_NFC_BASE 0x1b000200
+#define AR934X_NFC_SIZE 0xb8
#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
#define AR934X_SRIF_SIZE 0x1000
+#define QCA953X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA953X_GMAC_SIZE 0x14
+#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define QCA953X_WMAC_SIZE 0x20000
+#define QCA953X_EHCI_BASE 0x1b000000
+#define QCA953X_EHCI_SIZE 0x200
+#define QCA953X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
+#define QCA953X_SRIF_SIZE 0x1000
+
+#define QCA953X_PCI_CFG_BASE0 0x14000000
+#define QCA953X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
+#define QCA953X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
+#define QCA953X_PCI_MEM_BASE0 0x10000000
+#define QCA953X_PCI_MEM_SIZE 0x02000000
+
#define QCA955X_PCI_MEM_BASE0 0x10000000
#define QCA955X_PCI_MEM_BASE1 0x12000000
#define QCA955X_PCI_MEM_SIZE 0x02000000
@@ -106,11 +133,72 @@
#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
#define QCA955X_PCI_CTRL_SIZE 0x100
+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA955X_GMAC_SIZE 0x40
#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
#define QCA955X_WMAC_SIZE 0x20000
#define QCA955X_EHCI0_BASE 0x1b000000
#define QCA955X_EHCI1_BASE 0x1b400000
#define QCA955X_EHCI_SIZE 0x1000
+#define QCA955X_NFC_BASE 0x1b800200
+#define QCA955X_NFC_SIZE 0xb8
+
+#define QCA956X_PCI_MEM_BASE1 0x12000000
+#define QCA956X_PCI_MEM_SIZE 0x02000000
+#define QCA956X_PCI_CFG_BASE1 0x16000000
+#define QCA956X_PCI_CFG_SIZE 0x1000
+#define QCA956X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
+#define QCA956X_PCI_CRP_SIZE 0x1000
+#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
+#define QCA956X_PCI_CTRL_SIZE 0x100
+
+#define QCA956X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
+#define QCA956X_WMAC_SIZE 0x20000
+#define QCA956X_EHCI0_BASE 0x1b000000
+#define QCA956X_EHCI1_BASE 0x1b400000
+#define QCA956X_EHCI_SIZE 0x200
+#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SGMII_SIZE 0x64
+#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
+#define QCA956X_PLL_SIZE 0x50
+#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
+#define QCA956X_GMAC_SIZE 0x64
+
+/*
+ * Hidden Registers
+ */
+#define QCA956X_MAC_CFG_BASE 0xb9000000
+#define QCA956X_MAC_CFG_SIZE 0x64
+
+#define QCA956X_MAC_CFG1_REG 0x00
+#define QCA956X_MAC_CFG1_SOFT_RST BIT(31)
+#define QCA956X_MAC_CFG1_RX_RST BIT(19)
+#define QCA956X_MAC_CFG1_TX_RST BIT(18)
+#define QCA956X_MAC_CFG1_LOOPBACK BIT(8)
+#define QCA956X_MAC_CFG1_RX_EN BIT(2)
+#define QCA956X_MAC_CFG1_TX_EN BIT(0)
+
+#define QCA956X_MAC_CFG2_REG 0x04
+#define QCA956X_MAC_CFG2_IF_1000 BIT(9)
+#define QCA956X_MAC_CFG2_IF_10_100 BIT(8)
+#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
+#define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)
+#define QCA956X_MAC_CFG2_PAD_CRC_EN BIT(2)
+#define QCA956X_MAC_CFG2_FDX BIT(0)
+
+#define QCA956X_MAC_MII_MGMT_CFG_REG 0x20
+#define QCA956X_MGMT_CFG_CLK_DIV_20 0x07
+
+#define QCA956X_MAC_FIFO_CFG0_REG 0x48
+#define QCA956X_MAC_FIFO_CFG1_REG 0x4c
+#define QCA956X_MAC_FIFO_CFG2_REG 0x50
+#define QCA956X_MAC_FIFO_CFG3_REG 0x54
+#define QCA956X_MAC_FIFO_CFG4_REG 0x58
+#define QCA956X_MAC_FIFO_CFG5_REG 0x5c
+
+#define QCA956X_DAM_RESET_OFFSET 0xb90001bc
+#define QCA956X_DAM_RESET_SIZE 0x4
+#define QCA956X_INLINE_CHKSUM_ENG BIT(27)
/*
* DDR_CTRL block
@@ -149,6 +237,12 @@
#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
#define AR934X_DDR_REG_FLUSH_WMAC 0xac
+#define QCA953X_DDR_REG_FLUSH_GE0 0x9c
+#define QCA953X_DDR_REG_FLUSH_GE1 0xa0
+#define QCA953X_DDR_REG_FLUSH_USB 0xa4
+#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
+#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
+
/*
* PLL block
*/
@@ -166,9 +260,15 @@
#define AR71XX_AHB_DIV_SHIFT 20
#define AR71XX_AHB_DIV_MASK 0x7
+#define AR71XX_ETH0_PLL_SHIFT 17
+#define AR71XX_ETH1_PLL_SHIFT 19
+
#define AR724X_PLL_REG_CPU_CONFIG 0x00
#define AR724X_PLL_REG_PCIE_CONFIG 0x10
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS BIT(16)
+#define AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET BIT(25)
+
#define AR724X_PLL_FB_SHIFT 0
#define AR724X_PLL_FB_MASK 0x3ff
#define AR724X_PLL_REF_DIV_SHIFT 10
@@ -178,6 +278,8 @@
#define AR724X_DDR_DIV_SHIFT 22
#define AR724X_DDR_DIV_MASK 0x3
+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
+
#define AR913X_PLL_REG_CPU_CONFIG 0x00
#define AR913X_PLL_REG_ETH_CONFIG 0x04
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
@@ -190,6 +292,9 @@
#define AR913X_AHB_DIV_SHIFT 19
#define AR913X_AHB_DIV_MASK 0x1
+#define AR913X_ETH0_PLL_SHIFT 20
+#define AR913X_ETH1_PLL_SHIFT 22
+
#define AR933X_PLL_CPU_CONFIG_REG 0x00
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
@@ -211,6 +316,8 @@
#define AR934X_PLL_CPU_CONFIG_REG 0x00
#define AR934X_PLL_DDR_CONFIG_REG 0x04
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
@@ -243,9 +350,52 @@
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
+
+#define QCA953X_PLL_CPU_CONFIG_REG 0x00
+#define QCA953X_PLL_DDR_CONFIG_REG 0x04
+#define QCA953X_PLL_CLK_CTRL_REG 0x08
+#define QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
+#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
+#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
+
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
+#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
+#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
+#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
+#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
+#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
+#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
+#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
+#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
#define QCA955X_PLL_CLK_CTRL_REG 0x08
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
+#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
@@ -278,6 +428,81 @@
#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
+#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
+#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
+
+#define QCA956X_PLL_CPU_CONFIG_REG 0x00
+#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
+#define QCA956X_PLL_DDR_CONFIG_REG 0x08
+#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
+#define QCA956X_PLL_CLK_CTRL_REG 0x10
+#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG 0x28
+#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
+#define QCA956X_PLL_ETH_SGMII_SERDES_REG 0x4c
+
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
+#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
+#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
+#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
+
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
+#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
+#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
+#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
+
+#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
+#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
+#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
+#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
+#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB BIT(5)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1 BIT(6)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL BIT(7)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK 0xf
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP BIT(12)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2 BIT(13)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1 BIT(14)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2 BIT(15)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE BIT(16)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE BIT(17)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL BIT(18)
+#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL BIT(19)
+
+#define QCA956X_PLL_ETH_XMII_TX_INVERT BIT(1)
+#define QCA956X_PLL_ETH_XMII_GIGE BIT(25)
+#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT 28
+#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK 0x3
+#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT 26
+#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK 3
+
+#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT BIT(2)
+#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK BIT(1)
+#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL BIT(0)
+
/*
* USB_CONFIG block
*/
@@ -317,10 +542,19 @@
#define AR934X_RESET_REG_BOOTSTRAP 0xb0
#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+#define QCA953X_RESET_REG_RESET_MODULE 0x1c
+#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
+#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
+
#define QCA955X_RESET_REG_RESET_MODULE 0x1c
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
+#define QCA956X_RESET_REG_RESET_MODULE 0x1c
+#define QCA956X_RESET_REG_BOOTSTRAP 0xb0
+#define QCA956X_RESET_REG_EXT_INT_STATUS 0xac
+
+#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
#define MISC_INT_ETHSW BIT(12)
#define MISC_INT_TIMER4 BIT(10)
#define MISC_INT_TIMER3 BIT(9)
@@ -370,16 +604,123 @@
#define AR913X_RESET_USB_HOST BIT(5)
#define AR913X_RESET_USB_PHY BIT(4)
+#define AR933X_RESET_GE1_MDIO BIT(23)
+#define AR933X_RESET_GE0_MDIO BIT(22)
+#define AR933X_RESET_GE1_MAC BIT(13)
#define AR933X_RESET_WMAC BIT(11)
+#define AR933X_RESET_GE0_MAC BIT(9)
#define AR933X_RESET_USB_HOST BIT(5)
#define AR933X_RESET_USB_PHY BIT(4)
#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
+#define AR934X_RESET_HOST BIT(31)
+#define AR934X_RESET_SLIC BIT(30)
+#define AR934X_RESET_HDMA BIT(29)
+#define AR934X_RESET_EXTERNAL BIT(28)
+#define AR934X_RESET_RTC BIT(27)
+#define AR934X_RESET_PCIE_EP_INT BIT(26)
+#define AR934X_RESET_CHKSUM_ACC BIT(25)
+#define AR934X_RESET_FULL_CHIP BIT(24)
+#define AR934X_RESET_GE1_MDIO BIT(23)
+#define AR934X_RESET_GE0_MDIO BIT(22)
+#define AR934X_RESET_CPU_NMI BIT(21)
+#define AR934X_RESET_CPU_COLD BIT(20)
+#define AR934X_RESET_HOST_RESET_INT BIT(19)
+#define AR934X_RESET_PCIE_EP BIT(18)
+#define AR934X_RESET_UART1 BIT(17)
+#define AR934X_RESET_DDR BIT(16)
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define AR934X_RESET_NANDF BIT(14)
+#define AR934X_RESET_GE1_MAC BIT(13)
+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
+#define AR934X_RESET_HOST_DMA_INT BIT(10)
+#define AR934X_RESET_GE0_MAC BIT(9)
+#define AR934X_RESET_ETH_SWITCH BIT(8)
+#define AR934X_RESET_PCIE_PHY BIT(7)
+#define AR934X_RESET_PCIE BIT(6)
#define AR934X_RESET_USB_HOST BIT(5)
#define AR934X_RESET_USB_PHY BIT(4)
#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
+#define AR934X_RESET_LUT BIT(2)
+#define AR934X_RESET_MBOX BIT(1)
+#define AR934X_RESET_I2S BIT(0)
+
+#define QCA953X_RESET_USB_EXT_PWR BIT(29)
+#define QCA953X_RESET_EXTERNAL BIT(28)
+#define QCA953X_RESET_RTC BIT(27)
+#define QCA953X_RESET_FULL_CHIP BIT(24)
+#define QCA953X_RESET_GE1_MDIO BIT(23)
+#define QCA953X_RESET_GE0_MDIO BIT(22)
+#define QCA953X_RESET_CPU_NMI BIT(21)
+#define QCA953X_RESET_CPU_COLD BIT(20)
+#define QCA953X_RESET_DDR BIT(16)
+#define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA953X_RESET_GE1_MAC BIT(13)
+#define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
+#define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
+#define QCA953X_RESET_GE0_MAC BIT(9)
+#define QCA953X_RESET_ETH_SWITCH BIT(8)
+#define QCA953X_RESET_PCIE_PHY BIT(7)
+#define QCA953X_RESET_PCIE BIT(6)
+#define QCA953X_RESET_USB_HOST BIT(5)
+#define QCA953X_RESET_USB_PHY BIT(4)
+#define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
+
+#define QCA955X_RESET_HOST BIT(31)
+#define QCA955X_RESET_SLIC BIT(30)
+#define QCA955X_RESET_HDMA BIT(29)
+#define QCA955X_RESET_EXTERNAL BIT(28)
+#define QCA955X_RESET_RTC BIT(27)
+#define QCA955X_RESET_PCIE_EP_INT BIT(26)
+#define QCA955X_RESET_CHKSUM_ACC BIT(25)
+#define QCA955X_RESET_FULL_CHIP BIT(24)
+#define QCA955X_RESET_GE1_MDIO BIT(23)
+#define QCA955X_RESET_GE0_MDIO BIT(22)
+#define QCA955X_RESET_CPU_NMI BIT(21)
+#define QCA955X_RESET_CPU_COLD BIT(20)
+#define QCA955X_RESET_HOST_RESET_INT BIT(19)
+#define QCA955X_RESET_PCIE_EP BIT(18)
+#define QCA955X_RESET_UART1 BIT(17)
+#define QCA955X_RESET_DDR BIT(16)
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
+#define QCA955X_RESET_NANDF BIT(14)
+#define QCA955X_RESET_GE1_MAC BIT(13)
+#define QCA955X_RESET_SGMII_ANALOG BIT(12)
+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
+#define QCA955X_RESET_HOST_DMA_INT BIT(10)
+#define QCA955X_RESET_GE0_MAC BIT(9)
+#define QCA955X_RESET_SGMII BIT(8)
+#define QCA955X_RESET_PCIE_PHY BIT(7)
+#define QCA955X_RESET_PCIE BIT(6)
+#define QCA955X_RESET_USB_HOST BIT(5)
+#define QCA955X_RESET_USB_PHY BIT(4)
+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
+#define QCA955X_RESET_LUT BIT(2)
+#define QCA955X_RESET_MBOX BIT(1)
+#define QCA955X_RESET_I2S BIT(0)
+
+#define QCA956X_RESET_EXTERNAL BIT(28)
+#define QCA956X_RESET_FULL_CHIP BIT(24)
+#define QCA956X_RESET_GE1_MDIO BIT(23)
+#define QCA956X_RESET_GE0_MDIO BIT(22)
+#define QCA956X_RESET_CPU_NMI BIT(21)
+#define QCA956X_RESET_CPU_COLD BIT(20)
+#define QCA956X_RESET_DMA BIT(19)
+#define QCA956X_RESET_DDR BIT(16)
+#define QCA956X_RESET_GE1_MAC BIT(13)
+#define QCA956X_RESET_SGMII_ANALOG BIT(12)
+#define QCA956X_RESET_USB_PHY_ANALOG BIT(11)
+#define QCA956X_RESET_GE0_MAC BIT(9)
+#define QCA956X_RESET_SGMII BIT(8)
+#define QCA956X_RESET_USB_HOST BIT(5)
+#define QCA956X_RESET_USB_PHY BIT(4)
+#define QCA956X_RESET_USBSUS_OVERRIDE BIT(3)
+#define QCA956X_RESET_SWITCH_ANALOG BIT(2)
+#define QCA956X_RESET_SWITCH BIT(0)
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
@@ -398,8 +739,17 @@
#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
#define AR934X_BOOTSTRAP_DDR1 BIT(0)
+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
+#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
+
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
+#define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
+
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
@@ -418,6 +768,24 @@
AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
AR934X_PCIE_WMAC_INT_PCIE_RC3)
+#define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
+#define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
+#define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
+#define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
+#define QCA953X_PCIE_WMAC_INT_WMAC_ALL \
+ (QCA953X_PCIE_WMAC_INT_WMAC_MISC | QCA953X_PCIE_WMAC_INT_WMAC_TX | \
+ QCA953X_PCIE_WMAC_INT_WMAC_RXLP | QCA953X_PCIE_WMAC_INT_WMAC_RXHP)
+
+#define QCA953X_PCIE_WMAC_INT_PCIE_ALL \
+ (QCA953X_PCIE_WMAC_INT_PCIE_RC | QCA953X_PCIE_WMAC_INT_PCIE_RC0 | \
+ QCA953X_PCIE_WMAC_INT_PCIE_RC1 | QCA953X_PCIE_WMAC_INT_PCIE_RC2 | \
+ QCA953X_PCIE_WMAC_INT_PCIE_RC3)
+
#define QCA955X_EXT_INT_WMAC_MISC BIT(0)
#define QCA955X_EXT_INT_WMAC_TX BIT(1)
#define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
@@ -449,6 +817,37 @@
QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
QCA955X_EXT_INT_PCIE_RC2_INT3)
+#define QCA956X_EXT_INT_WMAC_MISC BIT(0)
+#define QCA956X_EXT_INT_WMAC_TX BIT(1)
+#define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
+#define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
+#define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
+#define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
+#define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
+#define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
+#define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
+#define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
+#define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
+#define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
+#define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
+#define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
+#define QCA956X_EXT_INT_USB1 BIT(24)
+#define QCA956X_EXT_INT_USB2 BIT(28)
+
+#define QCA956X_EXT_INT_WMAC_ALL \
+ (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
+ QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
+
+#define QCA956X_EXT_INT_PCIE_RC1_ALL \
+ (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
+ QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
+ QCA956X_EXT_INT_PCIE_RC1_INT3)
+
+#define QCA956X_EXT_INT_PCIE_RC2_ALL \
+ (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
+ QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
+ QCA956X_EXT_INT_PCIE_RC2_INT3)
+
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0
@@ -460,8 +859,12 @@
#define REV_ID_MAJOR_AR9341 0x0120
#define REV_ID_MAJOR_AR9342 0x1120
#define REV_ID_MAJOR_AR9344 0x2120
+#define REV_ID_MAJOR_QCA9533 0x0140
+#define REV_ID_MAJOR_QCA9533_V2 0x0160
#define REV_ID_MAJOR_QCA9556 0x0130
#define REV_ID_MAJOR_QCA9558 0x1130
+#define REV_ID_MAJOR_TP9343 0x0150
+#define REV_ID_MAJOR_QCA956X 0x1150
#define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0
@@ -482,8 +885,12 @@
#define AR934X_REV_ID_REVISION_MASK 0xf
+#define QCA953X_REV_ID_REVISION_MASK 0xf
+
#define QCA955X_REV_ID_REVISION_MASK 0xf
+#define QCA956X_REV_ID_REVISION_MASK 0xf
+
/*
* SPI block
*/
@@ -521,15 +928,63 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
#define AR934X_GPIO_REG_FUNC 0x6c
+#define QCA953X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA953X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA953X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA953X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA953X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA953X_GPIO_REG_IN_ENABLE0 0x44
+#define QCA953X_GPIO_REG_FUNC 0x6c
+
+#define QCA953X_GPIO_OUT_MUX_SPI_CS1 10
+#define QCA953X_GPIO_OUT_MUX_SPI_CS2 11
+#define QCA953X_GPIO_OUT_MUX_SPI_CS0 9
+#define QCA953X_GPIO_OUT_MUX_SPI_CLK 8
+#define QCA953X_GPIO_OUT_MUX_SPI_MOSI 12
+#define QCA953X_GPIO_OUT_MUX_LED_LINK1 41
+#define QCA953X_GPIO_OUT_MUX_LED_LINK2 42
+#define QCA953X_GPIO_OUT_MUX_LED_LINK3 43
+#define QCA953X_GPIO_OUT_MUX_LED_LINK4 44
+#define QCA953X_GPIO_OUT_MUX_LED_LINK5 45
+
+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
+#define QCA955X_GPIO_REG_FUNC 0x6c
+
+#define QCA956X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA956X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA956X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA956X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA956X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA956X_GPIO_REG_OUT_FUNC5 0x40
+#define QCA956X_GPIO_REG_IN_ENABLE0 0x44
+#define QCA956X_GPIO_REG_IN_ENABLE3 0x50
+#define QCA956X_GPIO_REG_FUNC 0x6c
+
+#define QCA956X_GPIO_OUT_MUX_GE0_MDO 32
+#define QCA956X_GPIO_OUT_MUX_GE0_MDC 33
+
#define AR71XX_GPIO_COUNT 16
#define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20
#define AR913X_GPIO_COUNT 22
#define AR933X_GPIO_COUNT 30
#define AR934X_GPIO_COUNT 23
+#define QCA953X_GPIO_COUNT 18
#define QCA955X_GPIO_COUNT 24
+#define QCA956X_GPIO_COUNT 23
/*
* SRIF block
@@ -552,4 +1007,318 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+#define QCA953X_SRIF_CPU_DPLL1_REG 0x1c0
+#define QCA953X_SRIF_CPU_DPLL2_REG 0x1c4
+#define QCA953X_SRIF_CPU_DPLL3_REG 0x1c8
+
+#define QCA953X_SRIF_DDR_DPLL1_REG 0x240
+#define QCA953X_SRIF_DDR_DPLL2_REG 0x244
+#define QCA953X_SRIF_DDR_DPLL3_REG 0x248
+
+#define QCA953X_SRIF_DPLL1_REFDIV_SHIFT 27
+#define QCA953X_SRIF_DPLL1_REFDIV_MASK 0x1f
+#define QCA953X_SRIF_DPLL1_NINT_SHIFT 18
+#define QCA953X_SRIF_DPLL1_NINT_MASK 0x1ff
+#define QCA953X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
+
+#define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
+#define QCA953X_SRIF_DPLL2_OUTDIV_SHIFT 13
+#define QCA953X_SRIF_DPLL2_OUTDIV_MASK 0x7
+
+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
+
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
+
+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
+
+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
+
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
+#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
+
+#define AR934X_GPIO_OUT_GPIO 0
+#define AR934X_GPIO_OUT_SPI_CS1 7
+#define AR934X_GPIO_OUT_LED_LINK0 41
+#define AR934X_GPIO_OUT_LED_LINK1 42
+#define AR934X_GPIO_OUT_LED_LINK2 43
+#define AR934X_GPIO_OUT_LED_LINK3 44
+#define AR934X_GPIO_OUT_LED_LINK4 45
+#define AR934X_GPIO_OUT_EXT_LNA0 46
+#define AR934X_GPIO_OUT_EXT_LNA1 47
+
+#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
+#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
+#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
+#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
+#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
+#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
+#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
+#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
+
+#define QCA955X_GPIO_OUT_GPIO 0
+#define QCA955X_MII_EXT_MDI 1
+#define QCA955X_SLIC_DATA_OUT 3
+#define QCA955X_SLIC_PCM_FS 4
+#define QCA955X_SLIC_PCM_CLK 5
+#define QCA955X_SPI_CLK 8
+#define QCA955X_SPI_CS_0 9
+#define QCA955X_SPI_CS_1 10
+#define QCA955X_SPI_CS_2 11
+#define QCA955X_SPI_MISO 12
+#define QCA955X_I2S_CLK 13
+#define QCA955X_I2S_WS 14
+#define QCA955X_I2S_SD 15
+#define QCA955X_I2S_MCK 16
+#define QCA955X_SPDIF_OUT 17
+#define QCA955X_UART1_TD 18
+#define QCA955X_UART1_RTS 19
+#define QCA955X_UART1_RD 20
+#define QCA955X_UART1_CTS 21
+#define QCA955X_UART0_SOUT 22
+#define QCA955X_SPDIF2_OUT 23
+#define QCA955X_LED_SGMII_SPEED0 24
+#define QCA955X_LED_SGMII_SPEED1 25
+#define QCA955X_LED_SGMII_DUPLEX 26
+#define QCA955X_LED_SGMII_LINK_UP 27
+#define QCA955X_SGMII_SPEED0_INVERT 28
+#define QCA955X_SGMII_SPEED1_INVERT 29
+#define QCA955X_SGMII_DUPLEX_INVERT 30
+#define QCA955X_SGMII_LINK_UP_INVERT 31
+#define QCA955X_GE1_MII_MDO 32
+#define QCA955X_GE1_MII_MDC 33
+#define QCA955X_SWCOM2 38
+#define QCA955X_SWCOM3 39
+#define QCA955X_MAC2_GPIO 40
+#define QCA955X_MAC3_GPIO 41
+#define QCA955X_ATT_LED 42
+#define QCA955X_PWR_LED 43
+#define QCA955X_TX_FRAME 44
+#define QCA955X_RX_CLEAR_EXTERNAL 45
+#define QCA955X_LED_NETWORK_EN 46
+#define QCA955X_LED_POWER_EN 47
+#define QCA955X_WMAC_GLUE_WOW 68
+#define QCA955X_RX_CLEAR_EXTENSION 70
+#define QCA955X_CP_NAND_CS1 73
+#define QCA955X_USB_SUSPEND 74
+#define QCA955X_ETH_TX_ERR 75
+#define QCA955X_DDR_DQ_OE 76
+#define QCA955X_CLKREQ_N_EP 77
+#define QCA955X_CLKREQ_N_RC 78
+#define QCA955X_CLK_OBS0 79
+#define QCA955X_CLK_OBS1 80
+#define QCA955X_CLK_OBS2 81
+#define QCA955X_CLK_OBS3 82
+#define QCA955X_CLK_OBS4 83
+#define QCA955X_CLK_OBS5 84
+
+/*
+ * MII_CTRL block
+ */
+#define AR71XX_MII_REG_MII0_CTRL 0x00
+#define AR71XX_MII_REG_MII1_CTRL 0x04
+
+#define AR71XX_MII_CTRL_IF_MASK 3
+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
+#define AR71XX_MII_CTRL_SPEED_MASK 3
+#define AR71XX_MII_CTRL_SPEED_10 0
+#define AR71XX_MII_CTRL_SPEED_100 1
+#define AR71XX_MII_CTRL_SPEED_1000 2
+
+#define AR71XX_MII0_CTRL_IF_GMII 0
+#define AR71XX_MII0_CTRL_IF_MII 1
+#define AR71XX_MII0_CTRL_IF_RGMII 2
+#define AR71XX_MII0_CTRL_IF_RMII 3
+
+#define AR71XX_MII1_CTRL_IF_RGMII 0
+#define AR71XX_MII1_CTRL_IF_RMII 1
+
+/*
+ * AR933X GMAC interface
+ */
+#define AR933X_GMAC_REG_ETH_CFG 0x00
+
+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
+
+/*
+ * AR934X GMAC Interface
+ */
+#define AR934X_GMAC_REG_ETH_CFG 0x00
+
+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
+#define AR934X_ETH_CFG_RXD_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_RXD_DELAY_SHIFT 14
+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
+
+/*
+ * QCA953X GMAC Interface
+ */
+#define QCA953X_GMAC_REG_ETH_CFG 0x00
+
+#define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
+#define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
+#define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
+#define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+
+/*
+ * QCA955X GMAC Interface
+ */
+
+#define QCA955X_GMAC_REG_ETH_CFG 0x00
+#define QCA955X_GMAC_REG_SGMII_SERDES 0x18
+
+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
+#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
+#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
+#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
+#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
+#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
+#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
+#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
+#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
+#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
+#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
+#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
+#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
+#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
+
+#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
+#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
+/*
+ * QCA956X GMAC Interface
+ */
+
+#define QCA956X_GMAC_REG_ETH_CFG 0x00
+#define QCA956X_GMAC_REG_SGMII_RESET 0x14
+#define QCA956X_GMAC_REG_SGMII_SERDES 0x18
+#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c
+#define QCA956X_GMAC_REG_SGMII_CONFIG 0x34
+#define QCA956X_GMAC_REG_SGMII_DEBUG 0x58
+
+#define QCA956X_ETH_CFG_RGMII_EN BIT(0)
+#define QCA956X_ETH_CFG_GE0_SGMII BIT(6)
+#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
+#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
+#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
+#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
+#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
+#define QCA956X_ETH_CFG_RXD_DELAY_MASK 0x3
+#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT 14
+#define QCA956X_ETH_CFG_RDV_DELAY_MASK 0x3
+#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT 16
+
+#define QCA956X_SGMII_RESET_RX_CLK_N_RESET 0x0
+#define QCA956X_SGMII_RESET_RX_CLK_N BIT(0)
+#define QCA956X_SGMII_RESET_TX_CLK_N BIT(1)
+#define QCA956X_SGMII_RESET_RX_125M_N BIT(2)
+#define QCA956X_SGMII_RESET_TX_125M_N BIT(3)
+#define QCA956X_SGMII_RESET_HW_RX_125M_N BIT(4)
+
+#define QCA956X_SGMII_SERDES_CDR_BW_MASK 0x3
+#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT 1
+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK 0x7
+#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT 4
+#define QCA956X_SGMII_SERDES_PLL_BW BIT(8)
+#define QCA956X_SGMII_SERDES_VCO_FAST BIT(9)
+#define QCA956X_SGMII_SERDES_VCO_SLOW BIT(10)
+#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS BIT(15)
+#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT BIT(16)
+#define QCA956X_SGMII_SERDES_FIBER_SDO BIT(17)
+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
+#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
+#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT 27
+#define QCA956X_SGMII_SERDES_VCO_REG_MASK 0xf
+
+#define QCA956X_MR_AN_CONTROL_AN_ENABLE BIT(12)
+#define QCA956X_MR_AN_CONTROL_PHY_RESET BIT(15)
+
+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
+#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
+
#endif /* __ASM_MACH_AR71XX_REGS_H */

400
target/linux/ath79/patches-4.14/0010-MIPS-ath79-add-support-for-QCA953x-QCA956x-TP9343.patch
View File

@ -1,400 +0,0 @@
From 2741304648dbdab7697d7758166a582b5291c53d Mon Sep 17 00:00:00 2001
From: Matthias Schiffer <mschiffer@universe-factory.net>
Date: Sat, 23 Jun 2018 15:08:56 +0200
Subject: [PATCH 10/33] MIPS: ath79: add support for QCA953x QCA956x TP9343
This patch adds support for 2 new types of QCA silicon. TP9343 is
essentially the same as the QCA956X but is licensed by TPLink.
Signed-off-by: Weijie Gao <hackpascal@gmail.com>
Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 193 +++++++++++++++++++++++++++++++
arch/mips/ath79/common.c | 8 ++
arch/mips/ath79/early_printk.c | 4 +
arch/mips/ath79/setup.c | 34 +++++-
arch/mips/include/asm/mach-ath79/ath79.h | 33 ++++++
5 files changed, 269 insertions(+), 3 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(vo
iounmap(dpll_base);
}
+static void __init qca953x_clocks_init(void)
+{
+ unsigned long ref_rate;
+ unsigned long cpu_rate;
+ unsigned long ddr_rate;
+ unsigned long ahb_rate;
+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
+ u32 cpu_pll, ddr_pll;
+ u32 bootstrap;
+
+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
+ ref_rate = 40 * 1000 * 1000;
+ else
+ ref_rate = 25 * 1000 * 1000;
+
+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
+ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
+ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
+ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
+ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
+
+ cpu_pll = nint * ref_rate / ref_div;
+ cpu_pll += frac * (ref_rate >> 6) / ref_div;
+ cpu_pll /= (1 << out_div);
+
+ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
+ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
+ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
+ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
+ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
+ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
+
+ ddr_pll = nint * ref_rate / ref_div;
+ ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
+ ddr_pll /= (1 << out_div);
+
+ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
+
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+
+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
+ cpu_rate = ref_rate;
+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
+ cpu_rate = cpu_pll / (postdiv + 1);
+ else
+ cpu_rate = ddr_pll / (postdiv + 1);
+
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
+ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+
+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
+ ddr_rate = ref_rate;
+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
+ ddr_rate = ddr_pll / (postdiv + 1);
+ else
+ ddr_rate = cpu_pll / (postdiv + 1);
+
+ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
+ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+
+ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+ ahb_rate = ref_rate;
+ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
+ ahb_rate = ddr_pll / (postdiv + 1);
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+ ath79_add_sys_clkdev("ref", ref_rate);
+ ath79_add_sys_clkdev("cpu", cpu_rate);
+ ath79_add_sys_clkdev("ddr", ddr_rate);
+ ath79_add_sys_clkdev("ahb", ahb_rate);
+
+ clk_add_alias("wdt", NULL, "ref", NULL);
+ clk_add_alias("uart", NULL, "ref", NULL);
+}
+
static void __init qca955x_clocks_init(void)
{
unsigned long ref_rate;
@@ -440,6 +525,110 @@ static void __init qca955x_clocks_init(v
clk_add_alias("uart", NULL, "ref", NULL);
}
+static void __init qca956x_clocks_init(void)
+{
+ unsigned long ref_rate;
+ unsigned long cpu_rate;
+ unsigned long ddr_rate;
+ unsigned long ahb_rate;
+ u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
+ u32 cpu_pll, ddr_pll;
+ u32 bootstrap;
+
+ /*
+ * QCA956x timer init workaround has to be applied right before setting
+ * up the clock. Else, there will be no jiffies
+ */
+ u32 misc;
+
+ misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
+ misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
+ ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
+
+ bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
+ if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
+ ref_rate = 40 * 1000 * 1000;
+ else
+ ref_rate = 25 * 1000 * 1000;
+
+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
+ out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
+
+ pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
+ nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
+ hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
+ lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
+ QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
+
+ cpu_pll = nint * ref_rate / ref_div;
+ cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
+ cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
+ cpu_pll /= (1 << out_div);
+
+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
+ out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
+ ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
+ pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
+ nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
+ hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
+ lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
+ QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
+
+ ddr_pll = nint * ref_rate / ref_div;
+ ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
+ ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
+ ddr_pll /= (1 << out_div);
+
+ clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
+
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
+ QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+
+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
+ cpu_rate = ref_rate;
+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
+ cpu_rate = ddr_pll / (postdiv + 1);
+ else
+ cpu_rate = cpu_pll / (postdiv + 1);
+
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
+ QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+
+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
+ ddr_rate = ref_rate;
+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
+ ddr_rate = cpu_pll / (postdiv + 1);
+ else
+ ddr_rate = ddr_pll / (postdiv + 1);
+
+ postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
+ QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+
+ if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
+ ahb_rate = ref_rate;
+ else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
+ ahb_rate = ddr_pll / (postdiv + 1);
+ else
+ ahb_rate = cpu_pll / (postdiv + 1);
+
+ ath79_add_sys_clkdev("ref", ref_rate);
+ ath79_add_sys_clkdev("cpu", cpu_rate);
+ ath79_add_sys_clkdev("ddr", ddr_rate);
+ ath79_add_sys_clkdev("ahb", ahb_rate);
+
+ clk_add_alias("wdt", NULL, "ref", NULL);
+ clk_add_alias("uart", NULL, "ref", NULL);
+}
+
void __init ath79_clocks_init(void)
{
if (soc_is_ar71xx())
@@ -450,8 +639,12 @@ void __init ath79_clocks_init(void)
ar933x_clocks_init();
else if (soc_is_ar934x())
ar934x_clocks_init();
+ else if (soc_is_qca953x())
+ qca953x_clocks_init();
else if (soc_is_qca955x())
qca955x_clocks_init();
+ else if (soc_is_qca956x() || soc_is_tp9343())
+ qca956x_clocks_init();
else
BUG();
}
--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
@@ -103,8 +103,12 @@ void ath79_device_reset_set(u32 mask)
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca953x())
+ reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca956x() || soc_is_tp9343())
+ reg = QCA956X_RESET_REG_RESET_MODULE;
else
BUG();
@@ -131,8 +135,12 @@ void ath79_device_reset_clear(u32 mask)
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca953x())
+ reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
+ else if (soc_is_qca956x() || soc_is_tp9343())
+ reg = QCA956X_RESET_REG_RESET_MODULE;
else
BUG();
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -76,8 +76,12 @@ static void prom_putchar_init(void)
case REV_ID_MAJOR_AR9341:
case REV_ID_MAJOR_AR9342:
case REV_ID_MAJOR_AR9344:
+ case REV_ID_MAJOR_QCA9533:
+ case REV_ID_MAJOR_QCA9533_V2:
case REV_ID_MAJOR_QCA9556:
case REV_ID_MAJOR_QCA9558:
+ case REV_ID_MAJOR_TP9343:
+ case REV_ID_MAJOR_QCA956X:
_prom_putchar = prom_putchar_ar71xx;
break;
--- a/arch/mips/ath79/setup.c
+++ b/arch/mips/ath79/setup.c
@@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type
u32 major;
u32 minor;
u32 rev = 0;
+ u32 ver = 1;
id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
major = id & REV_ID_MAJOR_MASK;
@@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type
rev = id & AR934X_REV_ID_REVISION_MASK;
break;
+ case REV_ID_MAJOR_QCA9533_V2:
+ ver = 2;
+ ath79_soc_rev = 2;
+ /* drop through */
+
+ case REV_ID_MAJOR_QCA9533:
+ ath79_soc = ATH79_SOC_QCA9533;
+ chip = "9533";
+ rev = id & QCA953X_REV_ID_REVISION_MASK;
+ break;
+
case REV_ID_MAJOR_QCA9556:
ath79_soc = ATH79_SOC_QCA9556;
chip = "9556";
@@ -164,14 +176,30 @@ static void __init ath79_detect_sys_type
rev = id & QCA955X_REV_ID_REVISION_MASK;
break;
+ case REV_ID_MAJOR_QCA956X:
+ ath79_soc = ATH79_SOC_QCA956X;
+ chip = "956X";
+ rev = id & QCA956X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_TP9343:
+ ath79_soc = ATH79_SOC_TP9343;
+ chip = "9343";
+ rev = id & QCA956X_REV_ID_REVISION_MASK;
+ break;
+
default:
panic("ath79: unknown SoC, id:0x%08x", id);
}
- ath79_soc_rev = rev;
+ if (ver == 1)
+ ath79_soc_rev = rev;
- if (soc_is_qca955x())
- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
+ if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca956x())
+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
+ chip, ver, rev);
+ else if (soc_is_tp9343())
+ sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
chip, rev);
else
sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
--- a/arch/mips/include/asm/mach-ath79/ath79.h
+++ b/arch/mips/include/asm/mach-ath79/ath79.h
@@ -32,8 +32,11 @@ enum ath79_soc_type {
ATH79_SOC_AR9341,
ATH79_SOC_AR9342,
ATH79_SOC_AR9344,
+ ATH79_SOC_QCA9533,
ATH79_SOC_QCA9556,
ATH79_SOC_QCA9558,
+ ATH79_SOC_TP9343,
+ ATH79_SOC_QCA956X,
};
extern enum ath79_soc_type ath79_soc;
@@ -100,6 +103,16 @@ static inline int soc_is_ar934x(void)
return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
}
+static inline int soc_is_qca9533(void)
+{
+ return ath79_soc == ATH79_SOC_QCA9533;
+}
+
+static inline int soc_is_qca953x(void)
+{
+ return soc_is_qca9533();
+}
+
static inline int soc_is_qca9556(void)
{
return ath79_soc == ATH79_SOC_QCA9556;
@@ -115,6 +128,26 @@ static inline int soc_is_qca955x(void)
return soc_is_qca9556() || soc_is_qca9558();
}
+static inline int soc_is_tp9343(void)
+{
+ return ath79_soc == ATH79_SOC_TP9343;
+}
+
+static inline int soc_is_qca9561(void)
+{
+ return ath79_soc == ATH79_SOC_QCA956X;
+}
+
+static inline int soc_is_qca9563(void)
+{
+ return ath79_soc == ATH79_SOC_QCA956X;
+}
+
+static inline int soc_is_qca956x(void)
+{
+ return soc_is_qca9561() || soc_is_qca9563();
+}
+
void ath79_ddr_wb_flush(unsigned int reg);
void ath79_ddr_set_pci_windows(void);

42
target/linux/ath79/patches-4.14/0014-MIPS-ath79-finetune-cpu-overrides.patch
View File

@ -1,42 +0,0 @@
From 30dc99e95ac4410072850ae466f696cb56097bb4 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Mon, 5 Mar 2018 11:35:29 +0100
Subject: [PATCH 14/33] MIPS: ath79: finetune cpu-overrides
This patch adds a few additional cpu feature overrides so that they do not
need to be probed at runtime.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -36,6 +36,7 @@
#define cpu_has_mdmx 0
#define cpu_has_mips3d 0
#define cpu_has_smartmips 0
+#define cpu_has_rixi 0
#define cpu_has_mips32r1 1
#define cpu_has_mips32r2 1
@@ -43,6 +44,7 @@
#define cpu_has_mips64r2 0
#define cpu_has_mipsmt 0
+#define cpu_has_userlocal 0
#define cpu_has_64bits 0
#define cpu_has_64bit_zero_reg 0
@@ -51,5 +53,9 @@
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
+#define cpu_has_vtag_icache 0
+#define cpu_has_dc_aliases 1
+#define cpu_has_ic_fills_f_dc 0
+#define cpu_has_pindexed_dcache 0
#endif /* __ASM_MACH_ATH79_CPU_FEATURE_OVERRIDES_H */

75
target/linux/ath79/patches-4.14/0015-MIPS-ath79-enable-uart-during-early_prink.patch
View File

@ -1,75 +0,0 @@
From f55a400f4a691f3750eaf7bfcd6ecbf7ed1622f0 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Mon, 5 Mar 2018 11:38:21 +0100
Subject: [PATCH 15/33] MIPS: ath79: enable uart during early_prink
This patch ensures, that the poinmux register is properly setup for the
boot console uart when early_printk is enabled.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/early_printk.c | 44 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
--- a/arch/mips/ath79/early_printk.c
+++ b/arch/mips/ath79/early_printk.c
@@ -58,6 +58,46 @@ static void prom_putchar_dummy(unsigned
/* nothing to do */
}
+static void prom_enable_uart(u32 id)
+{
+ void __iomem *gpio_base;
+ u32 uart_en;
+ u32 t;
+
+ switch (id) {
+ case REV_ID_MAJOR_AR71XX:
+ uart_en = AR71XX_GPIO_FUNC_UART_EN;
+ break;
+
+ case REV_ID_MAJOR_AR7240:
+ case REV_ID_MAJOR_AR7241:
+ case REV_ID_MAJOR_AR7242:
+ uart_en = AR724X_GPIO_FUNC_UART_EN;
+ break;
+
+ case REV_ID_MAJOR_AR913X:
+ uart_en = AR913X_GPIO_FUNC_UART_EN;
+ break;
+
+ case REV_ID_MAJOR_AR9330:
+ case REV_ID_MAJOR_AR9331:
+ uart_en = AR933X_GPIO_FUNC_UART_EN;
+ break;
+
+ case REV_ID_MAJOR_AR9341:
+ case REV_ID_MAJOR_AR9342:
+ case REV_ID_MAJOR_AR9344:
+ /* TODO */
+ default:
+ return;
+ }
+
+ gpio_base = (void __iomem *)(KSEG1ADDR(AR71XX_GPIO_BASE));
+ t = __raw_readl(gpio_base + AR71XX_GPIO_REG_FUNC);
+ t |= uart_en;
+ __raw_writel(t, gpio_base + AR71XX_GPIO_REG_FUNC);
+}
+
static void prom_putchar_init(void)
{
void __iomem *base;
@@ -92,8 +132,10 @@ static void prom_putchar_init(void)
default:
_prom_putchar = prom_putchar_dummy;
- break;
+ return;
}
+
+ prom_enable_uart(id);
}
void prom_putchar(unsigned char ch)

101
target/linux/ath79/patches-4.14/0016-MIPS-ath79-get-PCIe-controller-out-of-reset.patch
View File

@ -1,101 +0,0 @@
From d3fa9694bc71338161ae2b9c7ee08b57b8140f93 Mon Sep 17 00:00:00 2001
From: Mathias Kresin <dev@kresin.me>
Date: Tue, 6 Mar 2018 08:37:43 +0100
Subject: [PATCH 16/33] MIPS: ath79: get PCIe controller out of reset
The ar724x pci driver expects the PCIe controller to be brought out of
reset by the bootloader.
At least the AVM Fritz 300E bootloader doesn't take care of releasing
the different PCIe controller related resets which causes an endless
hang as soon as either the PCIE Reset register (0x180f0018) or the PCI
Application Control register (0x180f0000) is read from.
Do the full "PCIE Root Complex Initialization Sequence" if the PCIe
host controller is still in reset during probing.
The QCA u-boot sleeps 10ms after the PCIE Application Control bit is
set to ready. It has been shown that 10ms might not be enough time if
PCIe should be used right after setting the bit. During my tests it
took up to 20ms till the link was up. Giving the link up to 100ms
should work for all cases.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/pci/pci-ar724x.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -12,14 +12,18 @@
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/init.h>
+#include <linux/delay.h>
#include <linux/platform_device.h>
#include <asm/mach-ath79/ath79.h>
#include <asm/mach-ath79/ar71xx_regs.h>
+#define AR724X_PCI_REG_APP 0x00
#define AR724X_PCI_REG_RESET 0x18
#define AR724X_PCI_REG_INT_STATUS 0x4c
#define AR724X_PCI_REG_INT_MASK 0x50
+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
+
#define AR724X_PCI_RESET_LINK_UP BIT(0)
#define AR724X_PCI_INT_DEV0 BIT(14)
@@ -325,6 +329,37 @@ static void ar724x_pci_irq_init(struct a
apc);
}
+static void ar724x_pci_hw_init(struct ar724x_pci_controller *apc)
+{
+ u32 ppl, app;
+ int wait = 0;
+
+ /* deassert PCIe host controller and PCIe PHY reset */
+ ath79_device_reset_clear(AR724X_RESET_PCIE);
+ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
+
+ /* remove the reset of the PCIE PLL */
+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
+
+ /* deassert bypass for the PCIE PLL */
+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
+
+ /* set PCIE Application Control to ready */
+ app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
+ app |= AR724X_PCI_APP_LTSSM_ENABLE;
+ __raw_writel(app, apc->ctrl_base + AR724X_PCI_REG_APP);
+
+ /* wait up to 100ms for PHY link up */
+ do {
+ mdelay(10);
+ wait++;
+ } while (wait < 10 && !ar724x_pci_check_link(apc));
+}
+
static int ar724x_pci_probe(struct platform_device *pdev)
{
struct ar724x_pci_controller *apc;
@@ -383,6 +418,13 @@ static int ar724x_pci_probe(struct platf
apc->pci_controller.io_resource = &apc->io_res;
apc->pci_controller.mem_resource = &apc->mem_res;
+ /*
+ * Do the full PCIE Root Complex Initialization Sequence if the PCIe
+ * host controller is in reset.
+ */
+ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
+ ar724x_pci_hw_init(apc);
+
apc->link_up = ar724x_pci_check_link(apc);
if (!apc->link_up)
dev_warn(&pdev->dev, "PCIe link is down\n");

243
target/linux/ath79/patches-4.14/0021-MIPS-ath79-add-helpers-for-setting-clocks-and-expose.patch
View File

@ -1,243 +0,0 @@
From 288a8eb0d41f09fda242e05f8a7bd1f5b3489477 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:19:26 +0100
Subject: [PATCH 21/33] MIPS: ath79: add helpers for setting clocks and expose
the ref clock
Preparation for transitioning the legacy clock setup code over
to OF.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 128 ++++++++++++++++++----------------
include/dt-bindings/clock/ath79-clk.h | 3 +-
2 files changed, 68 insertions(+), 63 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -37,20 +37,46 @@ static struct clk_onecell_data clk_data
.clk_num = ARRAY_SIZE(clks),
};
-static struct clk *__init ath79_add_sys_clkdev(
- const char *id, unsigned long rate)
+static const char * const clk_names[ATH79_CLK_END] = {
+ [ATH79_CLK_CPU] = "cpu",
+ [ATH79_CLK_DDR] = "ddr",
+ [ATH79_CLK_AHB] = "ahb",
+ [ATH79_CLK_REF] = "ref",
+};
+
+static const char * __init ath79_clk_name(int type)
{
- struct clk *clk;
- int err;
+ BUG_ON(type >= ARRAY_SIZE(clk_names) || !clk_names[type]);
+ return clk_names[type];
+}
- clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
+static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
+{
if (IS_ERR(clk))
- panic("failed to allocate %s clock structure", id);
+ panic("failed to allocate %s clock structure", clk_names[type]);
- err = clk_register_clkdev(clk, id, NULL);
- if (err)
- panic("unable to register %s clock device", id);
+ clks[type] = clk;
+ clk_register_clkdev(clk, name, NULL);
+}
+static struct clk * __init ath79_set_clk(int type, unsigned long rate)
+{
+ const char *name = ath79_clk_name(type);
+ struct clk *clk;
+
+ clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
+ __ath79_set_clk(type, name, clk);
+ return clk;
+}
+
+static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
+ unsigned int mult, unsigned int div)
+{
+ const char *name = ath79_clk_name(type);
+ struct clk *clk;
+
+ clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
+ __ath79_set_clk(type, name, clk);
return clk;
}
@@ -80,27 +106,15 @@ static void __init ar71xx_clocks_init(vo
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
ahb_rate = cpu_rate / div;
- ath79_add_sys_clkdev("ref", ref_rate);
- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
}
-static struct clk * __init ath79_reg_ffclk(const char *name,
- const char *parent_name, unsigned int mult, unsigned int div)
-{
- struct clk *clk;
-
- clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
- if (IS_ERR(clk))
- panic("failed to allocate %s clock structure", name);
-
- return clk;
-}
-
static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
{
u32 pll;
@@ -114,24 +128,19 @@ static void __init ar724x_clk_init(struc
ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
}
static void __init ar724x_clocks_init(void)
{
struct clk *ref_clk;
- ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
+ ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
ar724x_clk_init(ref_clk, ath79_pll_base);
- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
-
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
}
@@ -186,12 +195,12 @@ static void __init ar9330_clk_init(struc
AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
}
- clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
- ninit_mul, ref_div * out_div * cpu_div);
- clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
- ninit_mul, ref_div * out_div * ddr_div);
- clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
- ninit_mul, ref_div * out_div * ahb_div);
+ ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
+ ref_div * out_div * cpu_div);
+ ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
+ ref_div * out_div * ddr_div);
+ ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
+ ref_div * out_div * ahb_div);
}
static void __init ar933x_clocks_init(void)
@@ -206,15 +215,10 @@ static void __init ar933x_clocks_init(vo
else
ref_rate = (25 * 1000 * 1000);
- ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
+ ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
ar9330_clk_init(ref_clk, ath79_pll_base);
- /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
- clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
- clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
- clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
-
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
}
@@ -344,10 +348,10 @@ static void __init ar934x_clocks_init(vo
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_add_sys_clkdev("ref", ref_rate);
- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
@@ -431,10 +435,10 @@ static void __init qca953x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_add_sys_clkdev("ref", ref_rate);
- ath79_add_sys_clkdev("cpu", cpu_rate);
- ath79_add_sys_clkdev("ddr", ddr_rate);
- ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
@@ -516,10 +520,10 @@ static void __init qca955x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_add_sys_clkdev("ref", ref_rate);
- clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
- clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
- clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
@@ -620,10 +624,10 @@ static void __init qca956x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_add_sys_clkdev("ref", ref_rate);
- ath79_add_sys_clkdev("cpu", cpu_rate);
- ath79_add_sys_clkdev("ddr", ddr_rate);
- ath79_add_sys_clkdev("ahb", ahb_rate);
+ ath79_set_clk(ATH79_CLK_REF, ref_rate);
+ ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
+ ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
+ ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
--- a/include/dt-bindings/clock/ath79-clk.h
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -13,7 +13,8 @@
#define ATH79_CLK_CPU 0
#define ATH79_CLK_DDR 1
#define ATH79_CLK_AHB 2
+#define ATH79_CLK_REF 3
-#define ATH79_CLK_END 3
+#define ATH79_CLK_END 4
#endif /* __DT_BINDINGS_ATH79_CLK_H */

114
target/linux/ath79/patches-4.14/0022-MIPS-ath79-move-legacy-wdt-and-uart-clock-aliases-ou.patch
View File

@ -1,114 +0,0 @@
From 339c191a95e978353c9ba3aafab0261e14de109b Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:22:43 +0100
Subject: [PATCH 22/33] MIPS: ath79: move legacy "wdt" and "uart" clock aliases
out of soc init
Preparation for reusing functions for DT
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 38 +++++++++++++++++---------------------
1 file changed, 17 insertions(+), 21 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -110,9 +110,6 @@ static void __init ar71xx_clocks_init(vo
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ahb", NULL);
}
static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
@@ -140,9 +137,6 @@ static void __init ar724x_clocks_init(vo
ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
ar724x_clk_init(ref_clk, ath79_pll_base);
-
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ahb", NULL);
}
static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
@@ -218,9 +212,6 @@ static void __init ar933x_clocks_init(vo
ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
ar9330_clk_init(ref_clk, ath79_pll_base);
-
- clk_add_alias("wdt", NULL, "ahb", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
}
static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
@@ -353,9 +344,6 @@ static void __init ar934x_clocks_init(vo
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
-
iounmap(dpll_base);
}
@@ -439,9 +427,6 @@ static void __init qca953x_clocks_init(v
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
}
static void __init qca955x_clocks_init(void)
@@ -524,9 +509,6 @@ static void __init qca955x_clocks_init(v
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
}
static void __init qca956x_clocks_init(void)
@@ -628,13 +610,13 @@ static void __init qca956x_clocks_init(v
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
-
- clk_add_alias("wdt", NULL, "ref", NULL);
- clk_add_alias("uart", NULL, "ref", NULL);
}
void __init ath79_clocks_init(void)
{
+ const char *wdt;
+ const char *uart;
+
if (soc_is_ar71xx())
ar71xx_clocks_init();
else if (soc_is_ar724x() || soc_is_ar913x())
@@ -651,6 +633,20 @@ void __init ath79_clocks_init(void)
qca956x_clocks_init();
else
BUG();
+
+ if (soc_is_ar71xx() || soc_is_ar724x() || soc_is_ar913x()) {
+ wdt = "ahb";
+ uart = "ahb";
+ } else if (soc_is_ar933x()) {
+ wdt = "ahb";
+ uart = "ref";
+ } else {
+ wdt = "ref";
+ uart = "ref";
+ }
+
+ clk_add_alias("wdt", NULL, wdt, NULL);
+ clk_add_alias("uart", NULL, uart, NULL);
}
unsigned long __init

242
target/linux/ath79/patches-4.14/0023-MIPS-ath79-pass-PLL-base-to-clock-init-functions.patch
View File

@ -1,242 +0,0 @@
From 6350b2c36c522fecbc91a80b63f49319dafd2a72 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:23:20 +0100
Subject: [PATCH 23/33] MIPS: ath79: pass PLL base to clock init functions
Preparation for passing the mapped base via DT
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 60 ++++++++++++++++++++++++-------------------------
1 file changed, 30 insertions(+), 30 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -80,7 +80,7 @@ static struct clk * __init ath79_set_ff_
return clk;
}
-static void __init ar71xx_clocks_init(void)
+static void __init ar71xx_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -92,7 +92,7 @@ static void __init ar71xx_clocks_init(vo
ref_rate = AR71XX_BASE_FREQ;
- pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
+ pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
freq = div * ref_rate;
@@ -130,13 +130,13 @@ static void __init ar724x_clk_init(struc
ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
}
-static void __init ar724x_clocks_init(void)
+static void __init ar724x_clocks_init(void __iomem *pll_base)
{
struct clk *ref_clk;
ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
- ar724x_clk_init(ref_clk, ath79_pll_base);
+ ar724x_clk_init(ref_clk, pll_base);
}
static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
@@ -197,7 +197,7 @@ static void __init ar9330_clk_init(struc
ref_div * out_div * ahb_div);
}
-static void __init ar933x_clocks_init(void)
+static void __init ar933x_clocks_init(void __iomem *pll_base)
{
struct clk *ref_clk;
unsigned long ref_rate;
@@ -234,7 +234,7 @@ static u32 __init ar934x_get_pll_freq(u3
return ret;
}
-static void __init ar934x_clocks_init(void)
+static void __init ar934x_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -265,7 +265,7 @@ static void __init ar934x_clocks_init(vo
AR934X_SRIF_DPLL1_REFDIV_MASK;
frac = 1 << 18;
} else {
- pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
+ pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
@@ -292,7 +292,7 @@ static void __init ar934x_clocks_init(vo
AR934X_SRIF_DPLL1_REFDIV_MASK;
frac = 1 << 18;
} else {
- pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
+ pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
@@ -307,7 +307,7 @@ static void __init ar934x_clocks_init(vo
ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
nfrac, frac, out_div);
- clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -347,7 +347,7 @@ static void __init ar934x_clocks_init(vo
iounmap(dpll_base);
}
-static void __init qca953x_clocks_init(void)
+static void __init qca953x_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -363,7 +363,7 @@ static void __init qca953x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
- pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
@@ -377,7 +377,7 @@ static void __init qca953x_clocks_init(v
cpu_pll += frac * (ref_rate >> 6) / ref_div;
cpu_pll /= (1 << out_div);
- pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
@@ -391,7 +391,7 @@ static void __init qca953x_clocks_init(v
ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
ddr_pll /= (1 << out_div);
- clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
+ clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -429,7 +429,7 @@ static void __init qca953x_clocks_init(v
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
}
-static void __init qca955x_clocks_init(void)
+static void __init qca955x_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -445,7 +445,7 @@ static void __init qca955x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
- pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
@@ -459,7 +459,7 @@ static void __init qca955x_clocks_init(v
cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
cpu_pll /= (1 << out_div);
- pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
@@ -473,7 +473,7 @@ static void __init qca955x_clocks_init(v
ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
ddr_pll /= (1 << out_div);
- clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
+ clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -511,7 +511,7 @@ static void __init qca955x_clocks_init(v
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
}
-static void __init qca956x_clocks_init(void)
+static void __init qca956x_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
unsigned long cpu_rate;
@@ -537,13 +537,13 @@ static void __init qca956x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
- pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
+ pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
@@ -556,12 +556,12 @@ static void __init qca956x_clocks_init(v
cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
cpu_pll /= (1 << out_div);
- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
- pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
+ pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
@@ -574,7 +574,7 @@ static void __init qca956x_clocks_init(v
ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
ddr_pll /= (1 << out_div);
- clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
+ clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
@@ -618,19 +618,19 @@ void __init ath79_clocks_init(void)
const char *uart;
if (soc_is_ar71xx())
- ar71xx_clocks_init();
+ ar71xx_clocks_init(ath79_pll_base);
else if (soc_is_ar724x() || soc_is_ar913x())
- ar724x_clocks_init();
+ ar724x_clocks_init(ath79_pll_base);
else if (soc_is_ar933x())
- ar933x_clocks_init();
+ ar933x_clocks_init(ath79_pll_base);
else if (soc_is_ar934x())
- ar934x_clocks_init();
+ ar934x_clocks_init(ath79_pll_base);
else if (soc_is_qca953x())
- qca953x_clocks_init();
+ qca953x_clocks_init(ath79_pll_base);
else if (soc_is_qca955x())
- qca955x_clocks_init();
+ qca955x_clocks_init(ath79_pll_base);
else if (soc_is_qca956x() || soc_is_tp9343())
- qca956x_clocks_init();
+ qca956x_clocks_init(ath79_pll_base);
else
BUG();

229
target/linux/ath79/patches-4.14/0024-MIPS-ath79-make-specifying-the-reference-clock-in-DT.patch
View File

@ -1,229 +0,0 @@
From 5fadb2544ed0bb72ddddd846aa303bb9ed2d211c Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:24:07 +0100
Subject: [PATCH 24/33] MIPS: ath79: make specifying the reference clock in DT
optional
It can be autodetected for many SoCs using the strapping options.
If the clock is specified in DT, the autodetected value is ignored
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 84 +++++++++++++++++++++++--------------------------
1 file changed, 40 insertions(+), 44 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -80,6 +80,18 @@ static struct clk * __init ath79_set_ff_
return clk;
}
+static unsigned long __init ath79_setup_ref_clk(unsigned long rate)
+{
+ struct clk *clk = clks[ATH79_CLK_REF];
+
+ if (clk)
+ rate = clk_get_rate(clk);
+ else
+ clk = ath79_set_clk(ATH79_CLK_REF, rate);
+
+ return rate;
+}
+
static void __init ar71xx_clocks_init(void __iomem *pll_base)
{
unsigned long ref_rate;
@@ -90,7 +102,7 @@ static void __init ar71xx_clocks_init(vo
u32 freq;
u32 div;
- ref_rate = AR71XX_BASE_FREQ;
+ ref_rate = ath79_setup_ref_clk(AR71XX_BASE_FREQ);
pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
@@ -106,16 +118,17 @@ static void __init ar71xx_clocks_init(vo
div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
ahb_rate = cpu_rate / div;
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
}
-static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+static void __init ar724x_clocks_init(void __iomem *pll_base)
{
- u32 pll;
u32 mult, div, ddr_div, ahb_div;
+ u32 pll;
+
+ ath79_setup_ref_clk(AR71XX_BASE_FREQ);
pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
@@ -130,17 +143,9 @@ static void __init ar724x_clk_init(struc
ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
}
-static void __init ar724x_clocks_init(void __iomem *pll_base)
-{
- struct clk *ref_clk;
-
- ref_clk = ath79_set_clk(ATH79_CLK_REF, AR724X_BASE_FREQ);
-
- ar724x_clk_init(ref_clk, pll_base);
-}
-
-static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
+static void __init ar933x_clocks_init(void __iomem *pll_base)
{
+ unsigned long ref_rate;
u32 clock_ctrl;
u32 ref_div;
u32 ninit_mul;
@@ -149,6 +154,15 @@ static void __init ar9330_clk_init(struc
u32 cpu_div;
u32 ddr_div;
u32 ahb_div;
+ u32 t;
+
+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+ ref_rate = (40 * 1000 * 1000);
+ else
+ ref_rate = (25 * 1000 * 1000);
+
+ ath79_setup_ref_clk(ref_rate);
clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
@@ -197,23 +211,6 @@ static void __init ar9330_clk_init(struc
ref_div * out_div * ahb_div);
}
-static void __init ar933x_clocks_init(void __iomem *pll_base)
-{
- struct clk *ref_clk;
- unsigned long ref_rate;
- u32 t;
-
- t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
- if (t & AR933X_BOOTSTRAP_REF_CLK_40)
- ref_rate = (40 * 1000 * 1000);
- else
- ref_rate = (25 * 1000 * 1000);
-
- ref_clk = ath79_set_clk(ATH79_CLK_REF, ref_rate);
-
- ar9330_clk_init(ref_clk, ath79_pll_base);
-}
-
static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
u32 frac, u32 out_div)
{
@@ -253,6 +250,8 @@ static void __init ar934x_clocks_init(vo
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
@@ -339,7 +338,6 @@ static void __init ar934x_clocks_init(vo
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -363,6 +361,8 @@ static void __init qca953x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -423,7 +423,6 @@ static void __init qca953x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -445,6 +444,8 @@ static void __init qca955x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -505,7 +506,6 @@ static void __init qca955x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -537,6 +537,8 @@ static void __init qca956x_clocks_init(v
else
ref_rate = 25 * 1000 * 1000;
+ ref_rate = ath79_setup_ref_clk(ref_rate);
+
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
@@ -606,7 +608,6 @@ static void __init qca956x_clocks_init(v
else
ahb_rate = cpu_pll / (postdiv + 1);
- ath79_set_clk(ATH79_CLK_REF, ref_rate);
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
@@ -682,10 +683,8 @@ static void __init ath79_clocks_init_dt_
void __iomem *pll_base;
ref_clk = of_clk_get(np, 0);
- if (IS_ERR(ref_clk)) {
- pr_err("%pOF: of_clk_get failed\n", np);
- goto err;
- }
+ if (!IS_ERR(ref_clk))
+ clks[ATH79_CLK_REF] = ref_clk;
pll_base = of_iomap(np, 0);
if (!pll_base) {
@@ -694,9 +693,9 @@ static void __init ath79_clocks_init_dt_
}
if (of_device_is_compatible(np, "qca,ar9130-pll"))
- ar724x_clk_init(ref_clk, pll_base);
+ ar724x_clocks_init(pll_base);
else if (of_device_is_compatible(np, "qca,ar9330-pll"))
- ar9330_clk_init(ref_clk, pll_base);
+ ar933x_clocks_init(pll_base);
else {
pr_err("%pOF: could not find any appropriate clk_init()\n", np);
goto err_iounmap;
@@ -714,9 +713,6 @@ err_iounmap:
err_clk:
clk_put(ref_clk);
-
-err:
- return;
}
CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);

77
target/linux/ath79/patches-4.14/0025-MIPS-ath79-support-setting-up-clock-via-DT-on-all-So.patch
View File

@ -1,77 +0,0 @@
From 6325626de001df98aebe51f3008b1aca05798d19 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:26:27 +0100
Subject: [PATCH 25/33] MIPS: ath79: support setting up clock via DT on all SoC
types
Use the same functions as the legacy code
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -669,16 +669,6 @@ ath79_get_sys_clk_rate(const char *id)
#ifdef CONFIG_OF
static void __init ath79_clocks_init_dt(struct device_node *np)
{
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
-
-CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
-
-static void __init ath79_clocks_init_dt_ng(struct device_node *np)
-{
struct clk *ref_clk;
void __iomem *pll_base;
@@ -692,14 +682,21 @@ static void __init ath79_clocks_init_dt_
goto err_clk;
}
- if (of_device_is_compatible(np, "qca,ar9130-pll"))
+ if (of_device_is_compatible(np, "qca,ar7100-pll"))
+ ar71xx_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
+ of_device_is_compatible(np, "qca,ar9130-pll"))
ar724x_clocks_init(pll_base);
else if (of_device_is_compatible(np, "qca,ar9330-pll"))
ar933x_clocks_init(pll_base);
- else {
- pr_err("%pOF: could not find any appropriate clk_init()\n", np);
- goto err_iounmap;
- }
+ else if (of_device_is_compatible(np, "qca,ar9340-pll"))
+ ar934x_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,qca9530-pll"))
+ qca953x_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,qca9550-pll"))
+ qca955x_clocks_init(pll_base);
+ else if (of_device_is_compatible(np, "qca,qca9560-pll"))
+ qca956x_clocks_init(pll_base);
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
pr_err("%pOF: could not register clk provider\n", np);
@@ -714,6 +711,14 @@ err_iounmap:
err_clk:
clk_put(ref_clk);
}
-CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
-CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
+
+CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
+CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
+
#endif

59
target/linux/ath79/patches-4.14/0026-MIPS-ath79-export-switch-MDIO-reference-clock.patch
View File

@ -1,59 +0,0 @@
From 78538d673801902108797f2c813e70cfbce280c9 Mon Sep 17 00:00:00 2001
From: Felix Fietkau <nbd@nbd.name>
Date: Tue, 6 Mar 2018 13:27:28 +0100
Subject: [PATCH 26/33] MIPS: ath79: export switch MDIO reference clock
On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz
clock. If that feature is not used, it defaults to the main reference
clock, like on all other SoC.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: John Crispin <john@phrozen.org>
---
arch/mips/ath79/clock.c | 8 ++++++++
include/dt-bindings/clock/ath79-clk.h | 3 ++-
2 files changed, 10 insertions(+), 1 deletion(-)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -42,6 +42,7 @@ static const char * const clk_names[ATH7
[ATH79_CLK_DDR] = "ddr",
[ATH79_CLK_AHB] = "ahb",
[ATH79_CLK_REF] = "ref",
+ [ATH79_CLK_MDIO] = "mdio",
};
static const char * __init ath79_clk_name(int type)
@@ -342,6 +343,10 @@ static void __init ar934x_clocks_init(vo
ath79_set_clk(ATH79_CLK_DDR, ddr_rate);
ath79_set_clk(ATH79_CLK_AHB, ahb_rate);
+ clk_ctrl = __raw_readl(pll_base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
+ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL)
+ ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000);
+
iounmap(dpll_base);
}
@@ -698,6 +703,9 @@ static void __init ath79_clocks_init_dt(
else if (of_device_is_compatible(np, "qca,qca9560-pll"))
qca956x_clocks_init(pll_base);
+ if (!clks[ATH79_CLK_MDIO])
+ clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
+
if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
pr_err("%pOF: could not register clk provider\n", np);
goto err_iounmap;
--- a/include/dt-bindings/clock/ath79-clk.h
+++ b/include/dt-bindings/clock/ath79-clk.h
@@ -14,7 +14,8 @@
#define ATH79_CLK_DDR 1
#define ATH79_CLK_AHB 2
#define ATH79_CLK_REF 3
+#define ATH79_CLK_MDIO 4
-#define ATH79_CLK_END 4
+#define ATH79_CLK_END 5
#endif /* __DT_BINDINGS_ATH79_CLK_H */

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