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rockchip: overclock to 2.2/1.8 GHz for NanoPi4 devices

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It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
and for better performance.

Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Co-authored-by: gzelvis <gzelvis@gmail.com>
This commit is contained in:
Tianling Shen 2020-12-19 21:36:28 +08:00 committed by CN_SZTL
parent b1c482bfc0
commit 93512049e6
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1 changed files with 184 additions and 0 deletions
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target/linux/rockchip/patches-5.4/991-rockchip-rk3399-overclock-to-2.2-1.8-GHz-for-NanoPi4.patch Normal file
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@ -0,0 +1,184 @@
From 04202df5cb497b1934c95211cf43784ef62245a4 Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Sat, 19 Dec 2020 12:42:27 +0000
Subject: [PATCH] rockchip: rk3399: overclock to 2.2/1.8 GHz for NanoPi4 devices
It's stable enough to overclock cpu frequency to 2.2/1.8 GHz,
and for better performance.
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
Co-authored-by: gzelvis <gzelvis@gmail.com>
---
.../boot/dts/rockchip/rk3399-nanopi4-opp.dtsi | 153 ++++++++++++++++++
.../boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +-
2 files changed, 154 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4-opp.dtsi
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd
+ */
+
+/ {
+ cluster0_opp: opp-table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <850000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <925000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1150000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1512000000>;
+ opp-microvolt = <1200000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1250000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1300000>;
+ };
+ };
+
+ cluster1_opp: opp-table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <800000>;
+ clock-latency-ns = <40000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <950000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1100000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1250000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1350000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-microvolt = <1400000>;
+ };
+ };
+
+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <800000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <297000000>;
+ opp-microvolt = <800000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <825000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <875000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <925000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1100000>;
+ };
+ };
+};
+
+&cpu_l0 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l1 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l2 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_l3 {
+ operating-points-v2 = <&cluster0_opp>;
+};
+
+&cpu_b0 {
+ operating-points-v2 = <&cluster1_opp>;
+};
+
+&cpu_b1 {
+ operating-points-v2 = <&cluster1_opp>;
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
@@ -14,7 +14,7 @@
/dts-v1/;
#include <dt-bindings/input/linux-event-codes.h>
#include "rk3399.dtsi"
-#include "rk3399-opp.dtsi"
+#include "rk3399-nanopi4-opp.dtsi"
/ {
chosen {