Add IPQ4019 SD/MMC controller support
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From beae4078c07d3cdc90473a2b35eb0d2b4f3c922c Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 14 Sep 2019 23:13:17 +0200
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Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI VQMMC LDO regulator node
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IPQ4019 has a built in SD/eMMC controller which depends on
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VQMMC LDO regulator working.
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Since we have a driver for it lets add the appropriate node for it.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
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1 file changed, 10 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -216,6 +216,16 @@
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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};
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+ vqmmc: regulator@1948000 {
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+ compatible = "qcom,ipq4019-vqmmc-regulator";
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+ reg = <0x01948000 0x4>;
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+ regulator-name = "vqmmc";
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+ regulator-min-microvolt = <1500000>;
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+ regulator-max-microvolt = <3000000>;
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+ regulator-always-on;
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+ status = "disabled";
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+ };
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+
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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@ -0,0 +1,41 @@
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Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node
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Date: Thu, 15 Aug 2019 19:28:23 +0200
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Message-Id: <20190815172823.12028-1-robimarko@gmail.com>
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X-Mailer: git-send-email 2.21.0
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MIME-Version: 1.0
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Sender: linux-arm-msm-owner@vger.kernel.org
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Precedence: bulk
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List-ID: <linux-arm-msm.vger.kernel.org>
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X-Mailing-List: linux-arm-msm@vger.kernel.org
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X-Virus-Scanned: ClamAV using ClamSMTP
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IPQ4019 has a built in SD/eMMC controller which is supported by the
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SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding.
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So lets add the appropriate node for it.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -226,6 +226,18 @@
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status = "disabled";
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};
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+ sdhci: sdhci@7824900 {
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+ compatible = "qcom,sdhci-msm-v4";
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+ reg = <0x7824900 0x11c>, <0x7824000 0x800>;
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hc_irq", "pwr_irq";
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+ bus-width = <8>;
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+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
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+ <&gcc GCC_DCD_XO_CLK>;
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+ clock-names = "core", "iface", "xo";
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+ status = "disabled";
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+ };
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+
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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@ -0,0 +1,33 @@
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From beae4078c07d3cdc90473a2b35eb0d2b4f3c922c Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sat, 14 Sep 2019 23:13:17 +0200
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Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI VQMMC LDO regulator node
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IPQ4019 has a built in SD/eMMC controller which depends on
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VQMMC LDO regulator working.
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Since we have a driver for it lets add the appropriate node for it.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++++++++++
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1 file changed, 10 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -216,6 +216,16 @@
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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};
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+ vqmmc: regulator@1948000 {
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+ compatible = "qcom,ipq4019-vqmmc-regulator";
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+ reg = <0x01948000 0x4>;
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+ regulator-name = "vqmmc";
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+ regulator-min-microvolt = <1500000>;
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+ regulator-max-microvolt = <3000000>;
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+ regulator-always-on;
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+ status = "disabled";
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+ };
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+
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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@ -0,0 +1,41 @@
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Subject: [PATCH] ARM: dts: qcom: ipq4019: Add SDHCI controller node
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Date: Thu, 15 Aug 2019 19:28:23 +0200
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Message-Id: <20190815172823.12028-1-robimarko@gmail.com>
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X-Mailer: git-send-email 2.21.0
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MIME-Version: 1.0
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Sender: linux-arm-msm-owner@vger.kernel.org
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Precedence: bulk
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List-ID: <linux-arm-msm.vger.kernel.org>
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X-Mailing-List: linux-arm-msm@vger.kernel.org
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X-Virus-Scanned: ClamAV using ClamSMTP
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IPQ4019 has a built in SD/eMMC controller which is supported by the
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SDHCI MSM driver, by the "qcom,sdhci-msm-v4" binding.
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So lets add the appropriate node for it.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++++++++
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1 file changed, 12 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -226,6 +226,18 @@
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status = "disabled";
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};
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+ sdhci: sdhci@7824900 {
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+ compatible = "qcom,sdhci-msm-v4";
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+ reg = <0x7824900 0x11c>, <0x7824000 0x800>;
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hc_irq", "pwr_irq";
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+ bus-width = <8>;
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+ clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
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+ <&gcc GCC_DCD_XO_CLK>;
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+ clock-names = "core", "iface", "xo";
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+ status = "disabled";
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+ };
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+
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x23000>;
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@ -0,0 +1,56 @@
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From: Georgi Djakov <georgi.djakov@linaro.org>
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Date: Mon, 28 Nov 2016 19:39:20 +0200
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Subject: [PATCH v2] mmc: sdhci-msm: Add sdhci_reset() implementation
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Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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---
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drivers/mmc/host/sdhci-msm.c | 29 ++++++++++++++++++++++++++++-
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1 file changed, 28 insertions(+), 1 deletion(-)
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diff -urN a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
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--- a/drivers/mmc/host/sdhci-msm.c 2020-01-23 15:20:37.000000000 +0800
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+++ b/drivers/mmc/host/sdhci-msm.c 2020-02-10 13:37:03.577363800 +0800
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@@ -1117,6 +1117,33 @@
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__sdhci_msm_set_clock(host, clock);
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}
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+void sdhci_msm_reset(struct sdhci_host *host, u8 mask)
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+{
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+ unsigned long timeout = 100;
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+
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+ sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
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+
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+ if (mask & SDHCI_RESET_ALL) {
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+ host->clock = 0;
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+
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+ /*
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+ * SDHCI_RESET_ALL triggers the PWR IRQ
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+ * and we need to handle it here.
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+ */
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+ sdhci_msm_voltage_switch(host);
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+ }
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+
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+ while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
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+ if (timeout == 0) {
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+ pr_err("%s: Reset 0x%x never completed.\n",
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+ mmc_hostname(host->mmc), (int)mask);
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+ return;
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+ }
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+ timeout--;
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+ mdelay(1);
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+ }
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+}
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+
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static void sdhci_msm_write_w(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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@@ -1148,7 +1175,7 @@
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MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
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static const struct sdhci_ops sdhci_msm_ops = {
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- .reset = sdhci_reset,
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+ .reset = sdhci_msm_reset,
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.set_clock = sdhci_msm_set_clock,
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.get_min_clock = sdhci_msm_get_min_clock,
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.get_max_clock = sdhci_msm_get_max_clock,
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