This reverts the usage of the S-Tag for separating LAN and WAN port on
the embedded switch. Many users complained about not being able to
manage C-Tag addition / removal on the switch as well as degraded
performance.
Fixes: commit 9da2b56760 ("ipq40xx: fix ethernet vlan double tagging")
Signed-off-by: David Bauer <mail@david-bauer.net>
Since generic has the option set to y and other targets now inherit that
choice, there is no behaviour change
Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com>
The option was introduced in upstream linux commit a6484045 ("[TCP]: Do
not present confusing congestion control options by default.").
The option is set to y in generic config and to the moment does not
incur additional size increment. Make it y for all so that packages
such as kmod-tcp-bbr do not have to set it on every occasion
Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com>
original idea by chunkeey
The essedma driver has its own unique take on VLAN management
and its configuration. In the original SDK, each VLAN is
assigned one virtual ethernet netdev.
However, this is non-standard. So, this patch does away
with the default_vlan_tag property the driver is using
and therefore forces the user to use the kernel's vlan
feature.
Unfortunately, this change will cause the essedma driver
to leak LAN<->WAN during LEDE bootup.
Signed-off-by: Chen Minqiang <ptpt52@gmail.com>
This commit adds support for Qualcomm IPQ8062 SoC.
IPQ8062 is a lower clock variant of IPQ8064.
CPU and NSS clocks:
- CPU: 384 MHz - 1 GHz
- NSS: 110 MHz - 550 MHz
opp and l2 clock values are taken from WG2600HP3 GPL source code [1].
Due to a lack of devices, I didn't test the following features.
- SATA
- NAND flash memory controller
- SD
- USB
- GSBI2, GSBI7
- PCIE2
- GMAC0, GMAC3
Works properly:
- GSBI4 UART
- GSBI5 SPI
- GMAC1, GMAC2
- PCIE0, PCIE1
- MDIO0
Does not work properly:
- CPU SPC
- This can cause a system hang. Same as IPQ8065.
See 2336c2dbb1
[1] https://www.aterm.jp/function/wg2600hp3/appendix/opensource.html
Signed-off-by: Yanase Yuki <dev@zpc.sakura.ne.jp>
Lets use the generic upstream phy_print_status() instead of doing
something similar by hand.
Before:
ess_edma c080000.edma: eth1: GMAC Link is up with phy_speed=1000
After:
ess_edma c080000.edma eth1: Link is Up - 1Gbps/Full - flow control rx/tx
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Since we now have a proper PHY driver for QCA807x and AR803x has already
been supported properly there is no need for the driver to be poking
on PHY registers for ethtool ops.
So, lets simply use the generic
phy_ethtool_ksettings_get/phy_ethtool_ksettings_set functions.
This also has the advantage of properly populating stuff other than
speeds like, transceiver type, MDI-X etc.
ethtool before:
root@OpenWrt:/# ethtool eth1
Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Link partner advertised pause frame use: No
Link partner advertised auto-negotiation: No
Link partner advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Port: Twisted Pair
PHYAD: 4
Transceiver: internal
Auto-negotiation: on
MDI-X: Unknown
Supports Wake-on: d
Wake-on: d
Current message level: 0x00000000 (0)
Link detected: yes
ethtool after:
root@OpenWrt:/# ethtool eth1
Settings for eth1:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
1000baseX/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Full
Link partner advertised pause frame use: Symmetric Receive-only
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 1000Mb/s
Duplex: Full
Port: Twisted Pair
PHYAD: 4
Transceiver: external
Auto-negotiation: on
MDI-X: off (auto)
Supports Wake-on: d
Wake-on: d
Current message level: 0x00000000 (0)
Link detected: yes
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Since the new PHY driver manages each PHY individually and therefore
registers each PHY that is marked with gpio-controller; DT property as a
GPIO controller we need to convert old DT bindings to account for this.
Only 2 boards use this so its not much of an issue.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
Also adds the PSGMII PHY as it wont get probed otherwise.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
PHY needs to be soft reset before starting it from ethernet driver as
AR40xx calibration will leave it in unwanted state.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Since we now have proper PHY driver for the QCA807x PHY-s, lets remove
PHY handling from AR40xx.
This removes PHY driver, PHY GPIO driver and PHY init code.
AR40xx still needs to handle PSGMII calibration as that requires R/W
from the switch, so I am unable to move it into PHY driver.
This also converted the AR40xx driver to use OF_MDIO to find the MDIO
bus as it now cant be set through the PHY driver.
So lets depend on OF_MDIO in KConfig.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
They are 2 or 5 port IEEE 802.3 clause 22 compliant
10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s.
They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC,
while second one is SGMII for connection to MAC or fiber.
Both models have a combo port that supports 1000BASE-X and 100BASE-FX
fiber.
Each PHY inside of QCA807x series has 2 digitally controlled output only
pins that natively drive LED-s.
But some vendors used these to driver generic LED-s controlled by
user space, so lets enable registering each PHY as GPIO controller and
add driver for it.
This also adds the ability to specify DT properties so that 1000 Base-T
LED will also be lit up for 100 and 10 Base connections.
This is usually done by U-boot, but boards running mainline U-boot are
not configuring this yet.
These PHY-s are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x
boards.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
With the reworked MDIO driver, EDMA will fail to get the MII BUS as it
used the MII BUS stored inside the MDIO structure private data.
This obviously does not work with the modernized driver, so lets switch
to using a purpose build of_mdio_find_bus() which will return the MII
BUS and only requires the MDIO node to be passed.
This is easy as we already have the node parsed.
Also, since we now require OF_MDIO add that as dependency.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
IPQ40xx MDIO driver was upstreamed in kernel version 5.8.
So lets backport the upstream version and drop our local one.
This also refreshed the kernel config since the symbol name has changed.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
ELECOM WRC-1167GST2 is a 2.4/5 GHz band 11ac (Wi-Fi 5) router, based
on MT7621A.
Specification:
- SoC : MediaTek MT7621A
- RAM : DDR3 256 MiB
- Flash : SPI-NOR 32 MiB
- WLAN : 2.4/5 GHz 2T2R (MediaTek MT7615D)
- Ethernet : 10/100/1000 Mbps x5
- Switch : MediaTek MT7530 (SoC)
- LED/keys : 6x/6x (2x buttons, 1x slide-switch)
- UART : through-hole on PCB
- J4: 3.3V, GND, TX, RX from ethernet port side
- 57600n8
- Power : 12VDC, 1A
MAC addresses:
LAN : 04:AB:18:**:**:07 (Factory, 0xE000 (hex))
WAN : 04:AB:18:**:**:08 (Factory, 0xE006 (hex))
2.4 GHz : 04:AB:18:**:**:09 (none)
5 GHz : 04:AB:18:**:**:0A (none)
Flash instruction using factory image:
1. Boot WRC-1167GST2 normally
2. Access to "http://192.168.2.1/" and open firmware update page
("ファームウェア更新")
3. Select the OpenWrt factory image and click apply ("適用") button
4. Wait ~150 seconds to complete flashing
Notes:
- there is no way to configure the correct MAC address for secondary phy
(5GHz) on MT7615D
- Wi-Fi band on primary phy (2.4GHz) cannot be limitted by specifying
ieee80211-freq-limit
(fail to register secondary phy due to error)
- mtd-mac-address in the wifi node is required for using
mtd-mac-address-increment
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[rebase onto split DTSI]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
ELECOM WRC-1167GS2-B is a 2.4/5 GHz band 11ac (Wi-Fi 5) router, based
on MT7621A.
Specification:
- SoC : MediaTek MT7621A
- RAM : DDR3 128 MiB
- Flash : SPI-NOR 16 MiB
- WLAN : 2.4/5 GHz 2T2R (MediaTek MT7615D)
- Ethernet : 10/100/1000 Mbps x5
- Switch : MediaTek MT7530 (SoC)
- LED/keys : 6x/6x (2x buttons, 1x slide-switch)
- UART : through-hole on PCB
- J4: 3.3V, GND, TX, RX from ethernet port side
- 57600n8
- Power : 12VDC, 1A
MAC addresses:
LAN : 04:AB:18:**:**:13 (Factory, 0xFFF4 (hex))
WAN : 04:AB:18:**:**:14 (Factory, 0xFFFA (hex))
2.4 GHz : 04:AB:18:**:**:15 (none)
5 GHz : 04:AB:18:**:**:16 (Factory, 0x4 (hex))
Flash instruction using factory image:
1. Boot WRC-1167GS2-B normally
2. Access to "http://192.168.2.1/" and open firmware update page
("ファームウェア更新")
3. Select the OpenWrt factory image and click apply ("適用") button
4. Wait ~120 seconds to complete flashing
Notes:
- there is no way to configure the correct MAC address for secondary phy
(5GHz) on MT7615D
- Wi-Fi band on primary phy (2.4GHz) cannot be limitted by specifying
ieee80211-freq-limit
(fail to register secondary phy due to error)
- mtd-mac-address in the wifi node is required for using
mtd-mac-address-increment
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[rebase onto split DTSI patch]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This creates a dedicated DTSI for ELECOM WRC GS devices with 2 PCI
WiFi chips in preparation for the 1 chip - dual radio devices, so
the latter can reuse part of the common definitions.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Newer EnGenius software that still uses the tar.gz platform
instead of the custom header requires more checks for upgrading,
but their script includes a way to skip them...
the existence of a file in the tar.gz called failsafe.bin
Their upgrade script has these lines:
\#pass check when upload with full image file
[ "${errcode}" -eq "1" ] && [ -f failsafe.bin ] && errcode="0"
This overrides the script's "errcode" variable
which can be set if any of the following actions/checks fail:
- untarring of the upload
- magic number for kernel: "2705"
- magic num for rootfs: "7371" or "6873"
- md5sums for each file in the format
filename:md5
- existence of a file matching FWINFO*
that it has boardname in the name somewhere (grep)
that the 4th field of separator "-" is at least 3 (version)
Otherwise we would need to generate md5sums in this strange format
and touch a file with specific requirements in the name.
This does not effect boards where the advanced checks do not apply.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
[fixed SoB to match From:]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
FCC ID: A8J-ENSTAC
Engenius EnStationAC v1 is an outdoor wireless access point/bridge with
2 gigabit ethernet ports on 2 external ethernet switches,
5 GHz only wireless, internal antenna plates, and proprietery PoE.
Specification:
- QCA9557 SOC
- QCA9882 WLAN (PCI card, 5 GHz, 2x2, 26dBm)
- AR8035-A switch (RGMII GbE with PoE+ IN)
- AR8031 switch (SGMII GbE with PoE OUT)
- 40 MHz reference clock
- 16 MB FLASH MX25L12845EMI-10G
- 2x 64 MB RAM NT5TU32M16FG
- UART at J10 (unpopulated)
- internal antenna plates (19 dbi, directional)
- 7 LEDs, 1 button (power, eth, wlan, RSSI) (reset)
MAC addresses:
MAC addresses are labeled as ETH and 5GHz
Vendor MAC addresses in flash are duplicate
eth0 ETH *:d3 art 0x0/0x6
eth1 ---- *:d4 ---
phy0 5GHz *:d5 ---
Installation:
2 ways to flash factory.bin from OEM:
- if you get Failsafe Mode from failed flash:
only use it to flash Original firmware from Engenius
or risk kernel loop or halt which requires serial cable
Method 1: Firmware upgrade page:
OEM webpage at 192.168.1.1
username and password "admin"
Navigate to "Firmware" page from left pane
Click Browse and select the factory.bin image
Upload and verify checksum
Click Continue to confirm and wait 3 minutes
Method 2: Serial to load Failsafe webpage:
After connecting to serial console and rebooting...
Interrupt uboot with any key pressed rapidly
execute `run failsafe_boot` OR `bootm 0x9fd70000`
wait a minute
connect to ethernet and navigate to
"192.168.1.1/index.htm"
Select the factory.bin image and upload
wait about 3 minutes
Return to OEM:
If you have a serial cable, see Serial Failsafe instructions
otherwise, uboot-env can be used to make uboot load the failsafe image
*DISCLAIMER*
The Failsafe image is unique to Engenius boards.
If the failsafe image is missing or damaged this will not work
DO NOT downgrade to ar71xx this way, it can cause kernel loop or halt
ssh into openwrt and run
`fw_setenv rootfs_checksum 0`
reboot, wait 3 minutes
connect to ethernet and navigate to 192.168.1.1/index.htm
select OEM firmware image from Engenius and click upgrade
TFTP recovery:
rename initramfs to 'vmlinux-art-ramdisk'
make available on TFTP server at 192.168.1.101
power board
hold or press reset button repeatedly
NOTE: for some Engenius boards TFTP is not reliable
try setting MTU to 600 and try many times
Format of OEM firmware image:
The OEM software of EnStationAC is a heavily modified version
of Openwrt Altitude Adjustment 12.09. One of the many modifications
is to the sysupgrade program. Image verification is performed
simply by the successful ungzip and untar of the supplied file
and name check and header verification of the resulting contents.
To form a factory.bin that is accepted by OEM Openwrt build,
the kernel and rootfs must have specific names...
openwrt-ar71xx-enstationac-uImage-lzma.bin
openwrt-ar71xx-enstationac-root.squashfs
and begin with the respective headers (uImage, squashfs).
Then the files must be tarballed and gzipped.
The resulting binary is actually a tar.gz file in disguise.
This can be verified by using binwalk on the OEM firmware images,
ungzipping then untaring.
Newer EnGenius software requires more checks but their script
includes a way to skip them, otherwise the tar must include
a text file with the version and md5sums in a deprecated format.
The OEM upgrade script is at /etc/fwupgrade.sh.
OKLI kernel loader is required because the OEM software
expects the kernel to be no greater than 1536k
and the factory.bin upgrade procedure would otherwise
overwrite part of the kernel when writing rootfs.
Note on PLL-data cells:
The default PLL register values will not work
because of the external AR8033 switch between
the SOC and the ethernet PHY chips.
For QCA955x series, the PLL registers for eth0 and eth1
can be see in the DTSI as 0x28 and 0x48 respectively.
Therefore the PLL registers can be read from uboot
for each link speed after attempting tftpboot
or another network action using that link speed
with `md 0x18050028 1` and `md 0x18050048 1`.
For eth0 at 1000 speed, the value returned was
ae000000 but that didn't work, so following
the logical pattern from the rest of the values,
the guessed value of a3000000 works better.
later discovered that delay can be placed on the PHY end only
with phy-mode as 'rgmii-id' and set register to 0x82...
Tested from master, all link speeds functional
Signed-off-by: Michael Pratt <mcpratt@pm.me>
[fixed SoB to match From:]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Specifications:
- SoC: MediaTek MT7621AT
- RAM: 128 MB (DDR3)
- Flash: 16 MB (SPI NOR)
- WiFi: MediaTek MT7615N (x2)
- Switch: 1 WAN, 4 LAN (Gigabit)
- Ports: 1 USB 2.0, 1 USB 3.0
- Buttons: Reset, WiFi Toggle, WPS
- LEDs: Power, Internet, WiFi 2.4G WiFi 5G, USB 2.0, USB 3.0
The R1 revision is identical to the A1 revision except
- No Config2 Parition, therefore
- factory partition resized to 64k from 128K
- Firmware partition offset is 0x50000 not 0x60000
- Firmware partitions size increased by 64K
- Firmware partition type is "denx,uimage", not "sge,uimage"
- Padding of image creation "uimage-padhdr 96" removed
Installation:
- Older firmware versions: put the factory image on a USB stick, turn on
the telnet console, and flash using the following cmd
"fw_updater Linux /mnt/usb_X_X/firmware.bin"
- D-Link FailsafeUI:
Power down the router, press and hold the reset button, then
re-plug it. Keep the reset button pressed until the internet LED stops
flashing, then jack into any lan port and manually assign a static IP
address in 192.168.0.0/24 other than 192.168.0.0 (e.g. 192.168.0.2)
and go to http://192.168.0.1
Flash with the factory image.
Signed-off-by: Andrew Pikler <andrew.pikler@gmail.com>
Specifications:
* QCA9557, 16 MiB Flash, 128 MiB RAM, 802.11n 2T2R
* QCA9882, 802.11ac 2T2R
* Gigabit LAN Port (AR8035), 802.11af PoE
Installation:
* Factory Web UI is at 192.168.0.50
login with 'admin' and blank password, flash factory.bin
* Recovery Web UI is at 192.168.0.50
connect network cable, hold reset button during power-on and keep it
pressed until uploading has started (only required when checksum is ok,
e.g. for reverting back to oem firmware), flash factory.bin
After flashing factory.bin, additional free space can be reclaimed by
flashing sysupgrade.bin, since the factory image requires some padding
to be accepted for upgrading via OEM Web UI.
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
The Ubiquiti Network airCube AC is a cube shaped device supporting
2.4 GHz and 5 GHz with internal 2x2 MIMO antennas.
It can be powered with either one of:
- 24v power supply with 3.0mm x 1.0mm barrel plug
- 24v passive PoE on first LAN port
There are four 10/100/1000 Mbps ports (1 * WAN + 3 * LAN).
First LAN port have optional PoE passthrough to the WAN port.
SoC: Qualcomm / Atheros AR9342
RAM: 64 MB DDR2
Flash: 16 MB SPI NOR
Ethernet: 4x 10/100/1000 Mbps (1 WAN + 3 LAN)
LEDS: 1x via a SPI controller (not yet supported)
Buttons: 1x Reset
Serial: 1x (only RX and TX); 115200 baud, 8N1
Missing features:
- LED control is not supported
Physical to internal switch port mapping:
- physical port #1 (poe in) = switchport 2
- physical port #2 = switchport 3
- physical port #3 = switchport 5
- physical port #4 (wan/poe out) = switchport 4
Factory update is tested and is the same as for Ubiquiti AirCube ISP
hence the shared configuration between that devices.
Signed-off-by: Roman Kuzmitskii <damex.pp@icloud.com>
This patch adds support for the MikroTik RouterBOARD wAPR-2nD (wAP R)
router, a weatherproof 2.4 GHz access point with a miniPCI-e slot and
a SIM card slot.
Specifications:
- SoC: Qualcomm Atheros QCA9533
- Flash: 16 MB (SPI)
- RAM: 64 MB
- Ethernet: 1x 10/100 Mbps (PoE in)
- WiFi: AR9531 2T2R 2.4 GHz (SoC)
- miniPCI-e slot
- 4x green LEDs (1x WiFi, 3x RSSI)
- 1x reset button
See https://mikrotik.com/product/RBwAPR-2nD for more details.
Flashing:
TFTP boot initramfs image and then perform sysupgrade. Follow common
MikroTik procedure as in https://openwrt.org/toh/mikrotik/common.
Signed-off-by: Roger Pueyo Centelles <roger.pueyo@guifi.net>
Commit 5fc28ef479 ("ath79: Add support for Plasma Cloud PA300")
added the IMAGE/sysupgrade.bin/squashfs definition, which leaks into
other devices, resulting in sysupgrade.bin images that are actually
tarballs and do not boot when directly written to flash.
We can use the normal sysupgrade.bin command variable for this device.
Signed-off-by: Sven Wegener <sven.wegener@stealer.net>
[fix format, spelling]
Signed-off-by: David Bauer <mail@david-bauer.net>
