135 lines
3.5 KiB
Diff
135 lines
3.5 KiB
Diff
From 154292ae52bf21c77aa1b81035bd85343b416001 Mon Sep 17 00:00:00 2001
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From: Finley Xiao <finley.xiao@rock-chips.com>
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Date: Thu, 12 Nov 2020 16:24:14 +0800
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Subject: [PATCH] nvmem: rockchip-otp: Add support for rk3568-otp
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This adds the necessary data for handling efuse on the rk3568.
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: Ia74d77b68a6303223eaccdc08e882851a917f50f
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---
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drivers/nvmem/rockchip-otp.c | 90 ++++++++++++++++++++++++++++++++++++
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1 file changed, 90 insertions(+)
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--- a/drivers/nvmem/rockchip-otp.c
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+++ b/drivers/nvmem/rockchip-otp.c
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@@ -27,6 +27,7 @@
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#define OTPC_USER_CTRL 0x0100
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#define OTPC_USER_ADDR 0x0104
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#define OTPC_USER_ENABLE 0x0108
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+#define OTPC_USER_QP 0x0120
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#define OTPC_USER_Q 0x0124
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#define OTPC_INT_STATUS 0x0304
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#define OTPC_SBPI_CMD0_OFFSET 0x1000
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@@ -53,6 +54,7 @@
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#define SBPI_ENABLE_MASK GENMASK(16, 16)
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#define OTPC_TIMEOUT 10000
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+#define RK3568_NBYTES 2
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/* RK3588 Register */
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#define RK3588_OTPC_AUTO_CTRL 0x04
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@@ -184,6 +186,73 @@ read_end:
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return ret;
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}
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+static int rk3568_otp_read(void *context, unsigned int offset, void *val,
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+ size_t bytes)
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+{
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+ struct rockchip_otp *otp = context;
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+ unsigned int addr_start, addr_end, addr_offset, addr_len;
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+ unsigned int otp_qp;
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+ u32 data;
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+ u8 *buf;
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+ int ret, i = 0;
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+
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+ addr_start = rounddown(offset, RK3568_NBYTES) / RK3568_NBYTES;
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+ addr_end = roundup(offset + bytes, RK3568_NBYTES) / RK3568_NBYTES;
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+ addr_offset = offset % RK3568_NBYTES;
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+ addr_len = addr_end - addr_start;
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+
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+ buf = kzalloc(array3_size(addr_len, RK3568_NBYTES, sizeof(*buf)),
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+ GFP_KERNEL);
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+ if (!buf)
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+ return -ENOMEM;
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+
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+ ret = rockchip_otp_reset(otp);
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+ if (ret) {
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+ dev_err(otp->dev, "failed to reset otp phy\n");
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+ return ret;
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+ }
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+
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+ ret = rockchip_otp_ecc_enable(otp, true);
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+ if (ret < 0) {
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+ dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
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+ return ret;
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+ }
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+
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+ writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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+ udelay(5);
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+ while (addr_len--) {
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+ writel(addr_start++ | OTPC_USER_ADDR_MASK,
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+ otp->base + OTPC_USER_ADDR);
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+ writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
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+ otp->base + OTPC_USER_ENABLE);
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+
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+ ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE);
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+ if (ret < 0) {
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+ dev_err(otp->dev, "timeout during read setup\n");
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+ goto read_end;
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+ }
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+
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+ otp_qp = readl(otp->base + OTPC_USER_QP);
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+ if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) {
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+ ret = -EIO;
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+ dev_err(otp->dev, "ecc check error during read setup\n");
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+ goto read_end;
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+ }
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+
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+ data = readl(otp->base + OTPC_USER_Q);
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+ memcpy(&buf[i], &data, RK3568_NBYTES);
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+
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+ i += RK3568_NBYTES;
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+ }
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+
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+ memcpy(val, buf + addr_offset, bytes);
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+
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+read_end:
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+ writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
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+
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+ return ret;
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+}
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+
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static int rk3588_otp_read(void *context, unsigned int offset,
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void *val, size_t bytes)
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{
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@@ -274,6 +343,17 @@ static const struct rockchip_data px30_d
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.reg_read = px30_otp_read,
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};
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+static const char * const rk3568_otp_clocks[] = {
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+ "usr", "sbpi", "apb", "phy",
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+};
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+
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+static const struct rockchip_data rk3568_data = {
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+ .size = 0x80,
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+ .clks = rk3568_otp_clocks,
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+ .num_clks = ARRAY_SIZE(rk3568_otp_clocks),
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+ .reg_read = rk3568_otp_read,
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+};
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+
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static const char * const rk3588_otp_clocks[] = {
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"otp", "apb_pclk", "phy", "arb",
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};
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@@ -295,6 +375,10 @@ static const struct of_device_id rockchi
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.data = &px30_data,
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},
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{
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+ .compatible = "rockchip,rk3568-otp",
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+ .data = &rk3568_data,
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+ },
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+ {
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.compatible = "rockchip,rk3588-otp",
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.data = &rk3588_data,
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},
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