62 lines
1.5 KiB
Diff
62 lines
1.5 KiB
Diff
From e8c0448b695911c5a0cc37cadaacaf71d16b04d2 Mon Sep 17 00:00:00 2001
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From: Finley Xiao <finley.xiao@rock-chips.com>
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Date: Thu, 12 Nov 2020 15:43:28 +0800
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Subject: [PATCH] arm64: dts: rockchip: rk3568: Add otp device node
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Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
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Change-Id: I4ec51ba8d4e1381f787c0137cb475a21e546789d
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 29 ++++++++++++++++++++++++
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1 file changed, 29 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -840,6 +840,47 @@
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};
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};
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+ otp: otp@fe38c000 {
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+ compatible = "rockchip,rk3568-otp";
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+ reg = <0x0 0xfe38c000 0x0 0x4000>;
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+ clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>,
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+ <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>;
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+ clock-names = "usr", "sbpi", "apb", "phy";
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+ resets = <&cru SRST_OTPPHY>;
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+ reset-names = "otp_phy";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ cpu_code: cpu-code@2 {
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+ reg = <0x02 0x2>;
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+ };
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+
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+ otp_cpu_version: cpu-version@8 {
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+ reg = <0x08 0x1>;
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+ bits = <3 3>;
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+ };
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+
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+ otp_id: id@a {
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+ reg = <0x0a 0x10>;
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+ };
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+
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+ cpu_leakage: cpu-leakage@1a {
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+ reg = <0x1a 0x1>;
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+ };
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+
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+ log_leakage: log-leakage@1b {
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+ reg = <0x1b 0x1>;
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+ };
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+
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+ npu_leakage: npu-leakage@1c {
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+ reg = <0x1c 0x1>;
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+ };
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+
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+ gpu_leakage: gpu-leakage@1d {
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+ reg = <0x1d 0x1>;
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+ };
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+ };
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+
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qos_gpu: qos@fe128000 {
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compatible = "rockchip,rk3568-qos", "syscon";
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reg = <0x0 0xfe128000 0x0 0x20>;
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