rockchip: refresh patches
Drop upstreamed patches, refresh remaining patches. Signed-off-by: ZiMing Mo <msylgj@immortalwrt.org> [rebased upon HEAD] Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
ZiMing Mo
Tianling Shen
parent
4d5fe0a362
commit
35dc676ba3
@ -1,407 +0,0 @@
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From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001
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From: Chukun Pan <amadeus@jmu.edu.cn>
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Date: Sat, 3 Dec 2022 15:41:49 +0800
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Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus
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Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
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This device is similar to the NanoPi R2S, and has a 16MB
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SPI NOR (mx25l12805d). The reset button is changed to
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directly reset the power supply, another detail is that
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both network ports have independent MAC addresses.
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Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
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Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/Makefile | 1 +
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.../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
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2 files changed, 374 insertions(+)
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create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
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--- a/arch/arm64/boot/dts/rockchip/Makefile
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
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@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
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+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
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--- /dev/null
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+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
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@@ -0,0 +1,373 @@
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+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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+/*
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+ * Based on rk3328-nanopi-r2s.dts, which is:
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+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
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+ */
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/leds/common.h>
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+#include "rk3328.dtsi"
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+
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+/ {
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+ model = "Xunlong Orange Pi R1 Plus";
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+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
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+
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+ aliases {
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+ ethernet1 = &rtl8153;
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+ mmc0 = &sdmmc;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial2:1500000n8";
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+ };
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+
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+ gmac_clk: gmac-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "gmac_clkin";
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+ #clock-cells = <0>;
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
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+ pinctrl-names = "default";
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+
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+ led-0 {
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+ function = LED_FUNCTION_LAN;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
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+ };
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+
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+ led-1 {
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+ function = LED_FUNCTION_STATUS;
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+ color = <LED_COLOR_ID_RED>;
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+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
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+ linux,default-trigger = "heartbeat";
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+ };
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+
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+ led-2 {
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+ function = LED_FUNCTION_WAN;
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+ color = <LED_COLOR_ID_GREEN>;
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+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+
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+ vcc_sd: sdmmc-regulator {
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+ compatible = "regulator-fixed";
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+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
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+ pinctrl-0 = <&sdmmc0m1_pin>;
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+ pinctrl-names = "default";
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+ regulator-name = "vcc_sd";
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+ regulator-boot-on;
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+ vin-supply = <&vcc_io>;
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+ };
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+
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+ vcc_sys: vcc-sys-regulator {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vcc_sys";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ };
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+
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+ vdd_5v_lan: vdd-5v-lan-regulator {
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+ compatible = "regulator-fixed";
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+ enable-active-high;
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+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
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+ pinctrl-0 = <&lan_vdd_pin>;
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+ pinctrl-names = "default";
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+ regulator-name = "vdd_5v_lan";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ vin-supply = <&vcc_sys>;
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+ };
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+};
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+
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+&cpu0 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu1 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu2 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&cpu3 {
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+ cpu-supply = <&vdd_arm>;
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+};
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+
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+&display_subsystem {
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+ status = "disabled";
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+};
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+
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+&gmac2io {
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+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
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+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
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+ clock_in_out = "input";
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+ phy-handle = <&rtl8211e>;
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+ phy-mode = "rgmii";
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+ phy-supply = <&vcc_io>;
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+ pinctrl-0 = <&rgmiim1_pins>;
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+ pinctrl-names = "default";
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+ snps,aal;
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+ rx_delay = <0x18>;
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+ tx_delay = <0x24>;
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+ status = "okay";
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+
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+ mdio {
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+ compatible = "snps,dwmac-mdio";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ rtl8211e: ethernet-phy@1 {
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+ reg = <1>;
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+ pinctrl-0 = <ð_phy_reset_pin>;
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+ pinctrl-names = "default";
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+ reset-assert-us = <10000>;
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+ reset-deassert-us = <50000>;
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+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+};
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+
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+&i2c1 {
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+ status = "okay";
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+
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+ rk805: pmic@18 {
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+ compatible = "rockchip,rk805";
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+ reg = <0x18>;
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+ interrupt-parent = <&gpio1>;
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+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
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+ #clock-cells = <1>;
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+ clock-output-names = "xin32k", "rk805-clkout2";
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ pinctrl-0 = <&pmic_int_l>;
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+ pinctrl-names = "default";
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+ rockchip,system-power-controller;
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+ wakeup-source;
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+
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+ vcc1-supply = <&vcc_sys>;
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+ vcc2-supply = <&vcc_sys>;
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+ vcc3-supply = <&vcc_sys>;
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+ vcc4-supply = <&vcc_sys>;
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+ vcc5-supply = <&vcc_io>;
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+ vcc6-supply = <&vcc_sys>;
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+
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+ regulators {
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+ vdd_log: DCDC_REG1 {
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+ regulator-name = "vdd_log";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <712500>;
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+ regulator-max-microvolt = <1450000>;
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+ regulator-ramp-delay = <12500>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+
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+ vdd_arm: DCDC_REG2 {
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+ regulator-name = "vdd_arm";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <712500>;
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+ regulator-max-microvolt = <1450000>;
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+ regulator-ramp-delay = <12500>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <950000>;
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+ };
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+ };
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+
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+ vcc_ddr: DCDC_REG3 {
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+ regulator-name = "vcc_ddr";
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+ regulator-always-on;
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+ regulator-boot-on;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ };
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+ };
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+
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+ vcc_io: DCDC_REG4 {
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+ regulator-name = "vcc_io";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <3300000>;
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+ };
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+ };
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+
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+ vcc_18: LDO_REG1 {
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+ regulator-name = "vcc_18";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vcc18_emmc: LDO_REG2 {
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+ regulator-name = "vcc18_emmc";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1800000>;
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+ };
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+ };
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+
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+ vdd_10: LDO_REG3 {
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+ regulator-name = "vdd_10";
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+ regulator-always-on;
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+ regulator-boot-on;
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+ regulator-min-microvolt = <1000000>;
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+ regulator-max-microvolt = <1000000>;
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+
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+ regulator-state-mem {
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+ regulator-on-in-suspend;
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+ regulator-suspend-microvolt = <1000000>;
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+ };
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+ };
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+ };
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+ };
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+};
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+
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+&io_domains {
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+ pmuio-supply = <&vcc_io>;
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+ vccio1-supply = <&vcc_io>;
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+ vccio2-supply = <&vcc18_emmc>;
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+ vccio3-supply = <&vcc_io>;
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+ vccio4-supply = <&vcc_io>;
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+ vccio5-supply = <&vcc_io>;
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+ vccio6-supply = <&vcc_io>;
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+ status = "okay";
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+};
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+
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+&pinctrl {
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+ gmac2io {
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+ eth_phy_reset_pin: eth-phy-reset-pin {
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+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
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+ };
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+ };
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+
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+ leds {
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+ lan_led_pin: lan-led-pin {
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+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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+ sys_led_pin: sys-led-pin {
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+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+
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+ wan_led_pin: wan-led-pin {
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+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ lan {
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+ lan_vdd_pin: lan-vdd-pin {
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+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
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+ };
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+ };
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+
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+ pmic {
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+ pmic_int_l: pmic-int-l {
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+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
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+ };
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+ };
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+};
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+
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+&pwm2 {
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+ status = "okay";
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+};
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+
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+&sdmmc {
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+ bus-width = <4>;
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+ cap-sd-highspeed;
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+ disable-wp;
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+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
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+ pinctrl-names = "default";
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+ vmmc-supply = <&vcc_sd>;
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+ status = "okay";
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+};
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+
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+&spi0 {
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <50000000>;
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+ };
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+};
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+
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+&tsadc {
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+ rockchip,hw-tshut-mode = <0>;
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+ rockchip,hw-tshut-polarity = <0>;
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+ status = "okay";
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+};
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+
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+&u2phy {
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+ status = "okay";
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+};
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+
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+&u2phy_host {
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+ status = "okay";
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+};
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+
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+&u2phy_otg {
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+ status = "okay";
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+};
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+
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+&uart2 {
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+ status = "okay";
|
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+};
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+
|
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+&usb20_otg {
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+ dr_mode = "host";
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+ status = "okay";
|
||||
+};
|
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+
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+&usbdrd3 {
|
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+ dr_mode = "host";
|
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+ status = "okay";
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ /* Second port is for USB 3.0 */
|
||||
+ rtl8153: device@2 {
|
||||
+ compatible = "usbbda,8153";
|
||||
+ reg = <2>;
|
||||
+ };
|
||||
+};
|
||||
+
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+&usb_host0_ehci {
|
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+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
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+ status = "okay";
|
||||
+};
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@ -1,71 +0,0 @@
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From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
|
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From: Tianling Shen <cnsztl@gmail.com>
|
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Date: Sat, 25 Mar 2023 15:40:22 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
|
||||
|
||||
The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
|
||||
the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
|
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identical to OrangePi R1 Plus.
|
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|
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Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
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Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++
|
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2 files changed, 41 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
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+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
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@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
@@ -0,0 +1,40 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
|
||||
+ * (http://www.orangepi.org)
|
||||
+ *
|
||||
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3328-orangepi-r1-plus.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Xunlong Orange Pi R1 Plus LTS";
|
||||
+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8531c>;
|
||||
+ tx_delay = <0x19>;
|
||||
+ rx_delay = <0x05>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8531c: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+
|
||||
+ motorcomm,clk-out-frequency-hz = <125000000>;
|
||||
+ motorcomm,keep-pll-enabled;
|
||||
+ motorcomm,auto-sleep-disabled;
|
||||
+
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <15000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -1,33 +0,0 @@
|
||||
From fc5a80a432607d05e85bba37971712405f75c546 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 16 Dec 2023 12:07:23 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: configure eth pad driver strength
|
||||
for orangepi r1 plus lts
|
||||
|
||||
The default strength is not enough to provide stable connection
|
||||
under 3.3v LDO voltage.
|
||||
|
||||
Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS")
|
||||
Cc: stable@vger.kernel.org # 6.6+
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20231216040723.17864-1-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
|
||||
@@ -26,9 +26,11 @@
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <0>;
|
||||
|
||||
+ motorcomm,auto-sleep-disabled;
|
||||
motorcomm,clk-out-frequency-hz = <125000000>;
|
||||
motorcomm,keep-pll-enabled;
|
||||
- motorcomm,auto-sleep-disabled;
|
||||
+ motorcomm,rx-clk-drv-microamp = <5020>;
|
||||
+ motorcomm,rx-data-drv-microamp = <5020>;
|
||||
|
||||
pinctrl-0 = <ð_phy_reset_pin>;
|
||||
pinctrl-names = "default";
|
||||
@ -1,754 +0,0 @@
|
||||
From c6629b9a6738a64507478527da6c7b83c10a6d2c Mon Sep 17 00:00:00 2001
|
||||
From: Vasily Khoruzhick <anarsoul@gmail.com>
|
||||
Date: Tue, 7 Mar 2023 22:32:40 -0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S
|
||||
|
||||
FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
|
||||
|
||||
Board Specifications
|
||||
- Rockchip RK3568
|
||||
- 2 or 4GB LPDDR4X
|
||||
- 8GB or 16GB eMMC, SD card slot
|
||||
- GbE LAN (Native)
|
||||
- 2x 2.5G LAN (PCIe)
|
||||
- M.2 Connector
|
||||
- HDMI 2.0, MIPI DSI/CSI
|
||||
- 2xUSB 3.0 Host
|
||||
- USB Type C PD, 5V/9V/12V
|
||||
- GPIO: 12-pin 0.5mm FPC connector
|
||||
|
||||
Based on Tianling Shen's <cnsztl@gmail.com> work.
|
||||
|
||||
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 713 ++++++++++++++++++
|
||||
2 files changed, 714 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -73,4 +73,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
@@ -0,0 +1,713 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyelec.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R5S";
|
||||
+ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac0;
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ hdmi-con {
|
||||
+ compatible = "hdmi-connector";
|
||||
+ type = "a";
|
||||
+
|
||||
+ port {
|
||||
+ hdmi_con_in: endpoint {
|
||||
+ remote-endpoint = <&hdmi_out_con>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
|
||||
+
|
||||
+ led-lan1 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_LAN;
|
||||
+ function-enumerator = <1>;
|
||||
+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-lan2 {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_LAN;
|
||||
+ function-enumerator = <2>;
|
||||
+ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ power_led: led-power {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = LED_FUNCTION_POWER;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-wan {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_WAN;
|
||||
+ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_usbc: vdd-usbc-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vdd_usbc";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vdd_usbc>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vdd_usbc>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_pcie";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ startup-delay-us = <200000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb: vcc5v0-usb-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vdd_usbc>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_host_en>;
|
||||
+ regulator-name = "vcc5v0_usb_host";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
+ regulator-name = "vcc5v0_usb_otg";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&gmac0 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
|
||||
+ assigned-clock-rates = <0>, <125000000>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&rgmii_phy0>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac0_miim
|
||||
+ &gmac0_tx_bus2
|
||||
+ &gmac0_rx_bus2
|
||||
+ &gmac0_rgmii_clk
|
||||
+ &gmac0_rgmii_bus>;
|
||||
+ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 15ms, 50ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 15000 50000>;
|
||||
+ tx_delay = <0x3c>;
|
||||
+ rx_delay = <0x2f>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ avdd-0v9-supply = <&vdda0v9_image>;
|
||||
+ avdd-1v8-supply = <&vcca1v8_image>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_in {
|
||||
+ hdmi_in_vp0: endpoint {
|
||||
+ remote-endpoint = <&vp0_out_hdmi>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_out {
|
||||
+ hdmi_out_con: endpoint {
|
||||
+ remote-endpoint = <&hdmi_con_in>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <950000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2c5 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ hym8563: rtc@51 {
|
||||
+ compatible = "haoyu,hym8563";
|
||||
+ reg = <0x51>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <0>;
|
||||
+ clock-output-names = "rtcic_32kout";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&hym8563_int>;
|
||||
+ wakeup-source;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s0_8ch {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2s1_8ch {
|
||||
+ rockchip,trcm-sync-tx-only;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio0 {
|
||||
+ rgmii_phy0: ethernet-phy@1 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <1>;
|
||||
+ pinctrl-0 = <ð_phy0_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ data-lanes = <1 2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ num-lanes = <1>;
|
||||
+ num-ib-windows = <8>;
|
||||
+ num-ob-windows = <8>;
|
||||
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gmac0 {
|
||||
+ eth_phy0_reset_pin: eth-phy0-reset-pin {
|
||||
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ lan1_led_pin: lan1-led-pin {
|
||||
+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ lan2_led_pin: lan2-led-pin {
|
||||
+ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ power_led_pin: power-led-pin {
|
||||
+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ hym8563 {
|
||||
+ hym8563_int: hym8563-int {
|
||||
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic-int {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ max-frequency = <150000000>;
|
||||
+ no-sdio;
|
||||
+ no-mmc;
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ extcon = <&usb2phy0>;
|
||||
+ dr_mode = "host";
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_usb_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_host {
|
||||
+ phy-supply = <&vcc5v0_usb_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vp0 {
|
||||
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
+ remote-endpoint = <&hdmi_in_vp0>;
|
||||
+ };
|
||||
+};
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,152 +0,0 @@
|
||||
From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 18 Mar 2023 16:37:43 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C
|
||||
|
||||
FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
|
||||
|
||||
Specification:
|
||||
- Rockchip RK3568
|
||||
- 1/4GB LPDDR4X RAM
|
||||
- 8/32GB eMMC
|
||||
- SD card slot
|
||||
- M.2 Connector
|
||||
- 2x USB 3.0 Port
|
||||
- 2x 2500 Base-T (PCIe, r8125)
|
||||
- HDMI 2.0
|
||||
- MIPI DSI/CSI
|
||||
- USB Type C 5V
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++++++++++++++++
|
||||
2 files changed, 113 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -73,5 +73,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
@@ -0,0 +1,112 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyelec.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3568-nanopi-r5s.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R5C";
|
||||
+ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+
|
||||
+ button-reset {
|
||||
+ debounce-interval = <50>;
|
||||
+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ label = "reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
|
||||
+
|
||||
+ led-lan {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_LAN;
|
||||
+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ power_led: led-power {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ function = LED_FUNCTION_POWER;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-wan {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_WAN;
|
||||
+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ led-wlan {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_WLAN;
|
||||
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2x1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie20_reset_pin>;
|
||||
+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gpio-leds {
|
||||
+ lan_led_pin: lan-led-pin {
|
||||
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ power_led_pin: power-led-pin {
|
||||
+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wan_led_pin: wan-led-pin {
|
||||
+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wlan_led_pin: wlan-led-pin {
|
||||
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie {
|
||||
+ pcie20_reset_pin: pcie20-reset-pin {
|
||||
+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -1,49 +0,0 @@
|
||||
From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 18 Mar 2023 16:37:44 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix gmac support for NanoPi R5S
|
||||
|
||||
- Changed phy-mode to rgmii.
|
||||
|
||||
- Fixed pull type in pinctrl for gmac0.
|
||||
|
||||
- Removed duplicate properties in mdio node.
|
||||
These properties are defined in the gmac0 node already.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
|
||||
1 file changed, 2 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
@@ -57,7 +57,7 @@
|
||||
assigned-clock-rates = <0>, <125000000>;
|
||||
clock_in_out = "output";
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
- phy-mode = "rgmii-id";
|
||||
+ phy-mode = "rgmii";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac0_miim
|
||||
&gmac0_tx_bus2
|
||||
@@ -79,9 +79,6 @@
|
||||
reg = <1>;
|
||||
pinctrl-0 = <ð_phy0_reset_pin>;
|
||||
pinctrl-names = "default";
|
||||
- reset-assert-us = <10000>;
|
||||
- reset-deassert-us = <50000>;
|
||||
- reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -115,7 +112,7 @@
|
||||
&pinctrl {
|
||||
gmac0 {
|
||||
eth_phy0_reset_pin: eth-phy0-reset-pin {
|
||||
- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,39 +0,0 @@
|
||||
From 975e9bbad11950fc8276f1fa260d8bf2c341aa41 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 18 Mar 2023 16:37:45 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: remove I2S1 TDM node for the NanoPi R5
|
||||
series
|
||||
|
||||
This is for the audio output which does not exist on the boards.
|
||||
Also disable regulator-always-on for vccio_acodec since it's only
|
||||
used by the audio output.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------
|
||||
1 file changed, 6 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
|
||||
@@ -330,7 +330,6 @@
|
||||
|
||||
vccio_acodec: LDO_REG4 {
|
||||
regulator-name = "vccio_acodec";
|
||||
- regulator-always-on;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
@@ -441,11 +440,6 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
-&i2s1_8ch {
|
||||
- rockchip,trcm-sync-tx-only;
|
||||
- status = "okay";
|
||||
-};
|
||||
-
|
||||
&pcie30phy {
|
||||
data-lanes = <1 2>;
|
||||
status = "okay";
|
||||
@ -1,37 +0,0 @@
|
||||
From 5325593377f07de31f7e473a9677a28a04c891f3 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Thu, 11 May 2023 00:18:50 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix button reset pin for nanopi r5c
|
||||
|
||||
The reset pin was wrongly assigned due to a copy/paste error,
|
||||
fix it to match actual gpio pin.
|
||||
|
||||
While at it, remove a blank line from nanopi r5s dts.
|
||||
|
||||
Fixes: 05620031408a ("arm64: dts: rockchip: Add FriendlyARM NanoPi R5C")
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230510161850.4866-1-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +-
|
||||
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 -
|
||||
2 files changed, 1 insertion(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
|
||||
@@ -106,7 +106,7 @@
|
||||
|
||||
rockchip-key {
|
||||
reset_button_pin: reset-button-pin {
|
||||
- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
};
|
||||
};
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
|
||||
@@ -134,4 +134,3 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
-
|
||||
@ -1,70 +0,0 @@
|
||||
From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 25 Mar 2023 15:40:20 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C
|
||||
|
||||
The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
|
||||
chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++
|
||||
2 files changed, 41 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
|
||||
@@ -0,0 +1,40 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3328-nanopi-r2s.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R2C";
|
||||
+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
|
||||
+};
|
||||
+
|
||||
+&gmac2io {
|
||||
+ phy-handle = <&yt8521s>;
|
||||
+ tx_delay = <0x22>;
|
||||
+ rx_delay = <0x12>;
|
||||
+
|
||||
+ mdio {
|
||||
+ /delete-node/ ethernet-phy@1;
|
||||
+
|
||||
+ yt8521s: ethernet-phy@3 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <3>;
|
||||
+
|
||||
+ motorcomm,clk-out-frequency-hz = <125000000>;
|
||||
+ motorcomm,keep-pll-enabled;
|
||||
+ motorcomm,auto-sleep-disabled;
|
||||
+
|
||||
+ pinctrl-0 = <ð_phy_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ reset-assert-us = <10000>;
|
||||
+ reset-deassert-us = <50000>;
|
||||
+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
@ -1,63 +0,0 @@
|
||||
From d211665c5a833873ee37e501af58adbf028e6b5f Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 13 May 2023 21:53:07 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus
|
||||
|
||||
The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
|
||||
eMMC flash (8G) included.
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230513135307.26554-2-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts | 33 ++++++++++++++++++++++
|
||||
2 files changed, 34 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
|
||||
@@ -0,0 +1,33 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+/*
|
||||
+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
|
||||
+ * (http://www.friendlyarm.com)
|
||||
+ *
|
||||
+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3328-nanopi-r2c.dts"
|
||||
+
|
||||
+/ {
|
||||
+ model = "FriendlyElec NanoPi R2C Plus";
|
||||
+ compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc1 = &emmc;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&emmc {
|
||||
+ bus-width = <8>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ max-frequency = <150000000>;
|
||||
+ mmc-ddr-1_8v;
|
||||
+ mmc-hs200-1_8v;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
+ vmmc-supply = <&vcc_io_33>;
|
||||
+ vqmmc-supply = <&vcc18_emmc>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -1,553 +0,0 @@
|
||||
From ddb6cde1cf59eb57820a6c277b8b5cff45e68d68 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 6 May 2023 14:11:07 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Lunzn Fastrhino R66S
|
||||
|
||||
Lunzn Fastrhino R66S is a high-performance mini router.
|
||||
|
||||
Specification:
|
||||
- Rockchip RK3568
|
||||
- 1/2GB LPDDR4 RAM
|
||||
- SD card slot
|
||||
- 2x USB 3.0 Port
|
||||
- 2x 2500 Base-T (PCIe, r8125b)
|
||||
- 12v DC Jack
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230506061108.17658-2-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-fastrhino-r66s.dts | 27 ++
|
||||
.../boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi | 484 +++++++++++++++++++++
|
||||
3 files changed, 512 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
|
||||
@@ -0,0 +1,27 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+
|
||||
+#include "rk3568-fastrhino-r66s.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Lunzn FastRhino R66S";
|
||||
+ compatible = "lunzn,fastrhino-r66s", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ max-frequency = <150000000>;
|
||||
+ no-sdio;
|
||||
+ no-mmc;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
|
||||
@@ -0,0 +1,484 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/input/input.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ gpio-keys {
|
||||
+ compatible = "gpio-keys";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&reset_button_pin>;
|
||||
+
|
||||
+ button-reset {
|
||||
+ debounce-interval = <50>;
|
||||
+ gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
|
||||
+ label = "reset";
|
||||
+ linux,code = <KEY_RESTART>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&status_led_pin>;
|
||||
+
|
||||
+ status_led: led-status {
|
||||
+ color = <LED_COLOR_ID_BLUE>;
|
||||
+ function = LED_FUNCTION_STATUS;
|
||||
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ dc_12v: dc-12v-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "dc_12v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <12000000>;
|
||||
+ regulator-max-microvolt = <12000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_pcie";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb_host";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
|
||||
+ regulator-name = "vcc5v0_usb_otg";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <950000>;
|
||||
+ regulator-max-microvolt = <950000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-init-microvolt = <950000>;
|
||||
+ regulator-min-microvolt = <950000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ regulator-suspend-microvolt = <950000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ data-lanes = <1 2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ num-lanes = <1>;
|
||||
+ reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gpio-leds {
|
||||
+ status_led_pin: status-led-pin {
|
||||
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic-int {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rockchip-key {
|
||||
+ reset_button_pin: reset-button-pin {
|
||||
+ rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ dr_mode = "host";
|
||||
+ extcon = <&usb2phy0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_usb_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ phy-supply = <&vcc5v0_usb_otg>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -1,146 +0,0 @@
|
||||
From 5a9447fd17668c34449052e4f77eebc7a98eccf3 Mon Sep 17 00:00:00 2001
|
||||
From: Tianling Shen <cnsztl@gmail.com>
|
||||
Date: Sat, 6 May 2023 14:11:08 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Lunzn Fastrhino R68S
|
||||
|
||||
It's similar to Fastrhino R66S with the following changes:
|
||||
+ 2/4GB LPDDR4 RAM
|
||||
+ 2x 1000 Base-T (native, RTL8211f)
|
||||
+ ADC button
|
||||
+ 16GB eMMC on-board
|
||||
- No SD card slot
|
||||
|
||||
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230506061108.17658-3-cnsztl@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-fastrhino-r68s.dts | 112 +++++++++++++++++++++
|
||||
2 files changed, 113 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
|
||||
@@ -0,0 +1,112 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
+
|
||||
+#include "rk3568-fastrhino-r66s.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Lunzn FastRhino R68S";
|
||||
+ compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac0;
|
||||
+ ethernet1 = &gmac1;
|
||||
+ mmc0 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ adc-keys {
|
||||
+ compatible = "adc-keys";
|
||||
+ io-channels = <&saradc 0>;
|
||||
+ io-channel-names = "buttons";
|
||||
+ keyup-threshold-microvolt = <1800000>;
|
||||
+
|
||||
+ button-recovery {
|
||||
+ label = "Recovery";
|
||||
+ linux,code = <KEY_VENDOR>;
|
||||
+ press-threshold-microvolt = <1750>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&gmac0 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
|
||||
+ assigned-clock-rates = <0>, <125000000>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&rgmii_phy0>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac0_miim
|
||||
+ &gmac0_tx_bus2
|
||||
+ &gmac0_rx_bus2
|
||||
+ &gmac0_rgmii_clk
|
||||
+ &gmac0_rgmii_bus>;
|
||||
+ snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 15ms, 50ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 15000 50000>;
|
||||
+ tx_delay = <0x3c>;
|
||||
+ rx_delay = <0x2f>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
+ assigned-clock-rates = <0>, <125000000>;
|
||||
+ clock_in_out = "output";
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii-id";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m1_miim
|
||||
+ &gmac1m1_tx_bus2
|
||||
+ &gmac1m1_rx_bus2
|
||||
+ &gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_rgmii_bus>;
|
||||
+ snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 15ms, 50ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 15000 50000>;
|
||||
+ tx_delay = <0x4f>;
|
||||
+ rx_delay = <0x26>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio0 {
|
||||
+ rgmii_phy0: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-0 = <ð_phy0_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0>;
|
||||
+ pinctrl-0 = <ð_phy1_reset_pin>;
|
||||
+ pinctrl-names = "default";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ gmac0 {
|
||||
+ eth_phy0_reset_pin: eth-phy0-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gmac1 {
|
||||
+ eth_phy1_reset_pin: eth-phy1-reset-pin {
|
||||
+ rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -1,680 +0,0 @@
|
||||
From 007b4bb47f44ad1f2290b3bebfd1fac3822c9b23 Mon Sep 17 00:00:00 2001
|
||||
From: Furkan Kardame <f.kardame@manjaro.org>
|
||||
Date: Tue, 20 Jun 2023 21:47:46 +0300
|
||||
Subject: [PATCH] arm64: dts: rockchip: add dts for Firefly Station P2 aka
|
||||
rk3568-roc-pc
|
||||
|
||||
Add dts for Firefly Station P2.
|
||||
Working IO:
|
||||
* eMMC
|
||||
* HDMI
|
||||
* LAN
|
||||
* LED
|
||||
* SD Card
|
||||
* UART
|
||||
* USB2
|
||||
* USB3
|
||||
|
||||
Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
|
||||
Link: https://lore.kernel.org/r/20230620184746.55391-3-f.kardame@manjaro.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../arm64/boot/dts/rockchip/rk3568-roc-pc.dts | 643 ++++++++++++++++++
|
||||
2 files changed, 644 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -79,4 +79,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fa
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-roc-pc.dts
|
||||
@@ -0,0 +1,643 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Firefly Station P2";
|
||||
+ compatible = "firefly,rk3568-roc-pc", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ ethernet0 = &gmac0;
|
||||
+ ethernet1 = &gmac1;
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ dc_12v: dc-12v-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "dc_12v";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <12000000>;
|
||||
+ regulator-max-microvolt = <12000000>;
|
||||
+ };
|
||||
+
|
||||
+ gmac0_clkin: external-gmac0-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac0_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1_clkin: external-gmac1-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac1_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led-user {
|
||||
+ label = "user-led";
|
||||
+ default-state = "on";
|
||||
+ gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&user_led_enable_h>;
|
||||
+ retain-state-suspended;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ hdmi-con {
|
||||
+ compatible = "hdmi-connector";
|
||||
+ type = "a";
|
||||
+
|
||||
+ port {
|
||||
+ hdmi_con_in: endpoint {
|
||||
+ remote-endpoint = <&hdmi_out_con>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_pcie";
|
||||
+ enable-active-high;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc3v3_pcie_en_pin>;
|
||||
+ gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
|
||||
+ startup-delay-us = <5000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&dc_12v>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb: vcc5v0-usb-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_host: vcc5v0-host-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_host";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_host_en>;
|
||||
+ regulator-always-on;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_otg: vcc5v0-otg-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_otg";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_otg_en>;
|
||||
+ vin-supply = <&vcc5v0_usb>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0 {
|
||||
+ /* used for USB3 */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ /* used for USB3 */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy2 {
|
||||
+ /* used for SATA */
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac0 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
|
||||
+ clock_in_out = "input";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac0_miim
|
||||
+ &gmac0_tx_bus2
|
||||
+ &gmac0_rx_bus2
|
||||
+ &gmac0_rgmii_clk
|
||||
+ &gmac0_rgmii_bus
|
||||
+ &gmac0_clkinout>;
|
||||
+ phy-handle = <&rgmii_phy0>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 20ms, 100ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 20000 100000>;
|
||||
+ tx_delay = <0x3c>;
|
||||
+ rx_delay = <0x2f>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
|
||||
+ clock_in_out = "input";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m1_miim
|
||||
+ &gmac1m1_tx_bus2
|
||||
+ &gmac1m1_rx_bus2
|
||||
+ &gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_rgmii_bus
|
||||
+ &gmac1m1_clkinout>;
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 20ms, 100ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 20000 100000>;
|
||||
+ tx_delay = <0x4f>;
|
||||
+ rx_delay = <0x26>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ avdd-0v9-supply = <&vdda0v9_image>;
|
||||
+ avdd-1v8-supply = <&vcca1v8_image>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_in {
|
||||
+ hdmi_in_vp0: endpoint {
|
||||
+ remote-endpoint = <&vp0_out_hdmi>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_out {
|
||||
+ hdmi_out_con: endpoint {
|
||||
+ remote-endpoint = <&hdmi_con_in>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&i2s0_8ch {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&mdio0 {
|
||||
+ rgmii_phy0: phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0x0>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: phy@0 {
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0x0>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_reset_pin>;
|
||||
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ leds {
|
||||
+ user_led_enable_h: user-led-enable-h {
|
||||
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_host_en: vcc5v0-host-en {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_otg_en: vcc5v0-otg-en {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie {
|
||||
+ pcie_reset_pin: pcie-reset-pin {
|
||||
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
|
||||
+ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic-int {
|
||||
+ rockchip,pins =
|
||||
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio2-supply = <&vcc_1v8>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sata2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
+ disable-wp;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_host {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_otg {
|
||||
+ phy-supply = <&vcc5v0_host>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vp0 {
|
||||
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
+ remote-endpoint = <&hdmi_in_vp0>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -1,233 +0,0 @@
|
||||
From 096ebfb74b19f2d4bdcbc33ae02e857ff4b3e0a0 Mon Sep 17 00:00:00 2001
|
||||
From: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Date: Thu, 12 Jan 2023 16:29:02 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Radxa Compute Module 3 IO board
|
||||
|
||||
Radxa Compute Module 3(CM3) IO board is an application board from Radxa
|
||||
and is compatible with Raspberry Pi CM4 IO form factor.
|
||||
|
||||
Specification:
|
||||
- 1x HDMI,
|
||||
- 2x MIPI DSI
|
||||
- 2x MIPI CSI2
|
||||
- 1x eDP
|
||||
- 1x PCIe card
|
||||
- 2x SATA
|
||||
- 2x USB 2.0 Host
|
||||
- 1x USB 3.0
|
||||
- 1x USB 2.0 OTG
|
||||
- Phone jack
|
||||
- microSD slot
|
||||
- 40-pin GPIO expansion header
|
||||
- 12V DC
|
||||
|
||||
Radxa CM3 needs to mount on top of this IO board in order to create
|
||||
complete Radxa CM3 IO board platform.
|
||||
|
||||
Add support for Radxa CM3 IO Board.
|
||||
|
||||
Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
|
||||
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230112105902.192852-3-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 179 ++++++++++++++++++
|
||||
2 files changed, 180 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
@@ -0,0 +1,179 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2022 Radxa Limited
|
||||
+ * Copyright (c) 2022 Amarula Solutions(India)
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include <dt-bindings/soc/rockchip,vop2.h>
|
||||
+#include "rk3566.dtsi"
|
||||
+#include "rk3566-radxa-cm3.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa Compute Module 3(CM3) IO Board";
|
||||
+ compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc1 = &sdmmc0;
|
||||
+ };
|
||||
+
|
||||
+ chosen: chosen {
|
||||
+ stdout-path = "serial2:1500000n8";
|
||||
+ };
|
||||
+
|
||||
+ hdmi-con {
|
||||
+ compatible = "hdmi-connector";
|
||||
+ type = "a";
|
||||
+
|
||||
+ port {
|
||||
+ hdmi_con_in: endpoint {
|
||||
+ remote-endpoint = <&hdmi_out_con>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led-1 {
|
||||
+ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_ACTIVITY;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pi_nled_activity>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_usb30: vcc5v0-usb30-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_usb30";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vcc5v0_usb30_en_h>;
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: vcca1v8-image-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc_1v8_p>;
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: vdda0v9-image-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcca0v9_image";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ vin-supply = <&vdda_0v9>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi {
|
||||
+ avdd-0v9-supply = <&vdda0v9_image>;
|
||||
+ avdd-1v8-supply = <&vcca1v8_image>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&hdmi_in {
|
||||
+ hdmi_in_vp0: endpoint {
|
||||
+ remote-endpoint = <&vp0_out_hdmi>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_out {
|
||||
+ hdmi_out_con: endpoint {
|
||||
+ remote-endpoint = <&hdmi_con_in>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&hdmi_sound {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ leds {
|
||||
+ pi_nled_activity: pi-nled-activity {
|
||||
+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdcard {
|
||||
+ sdmmc_pwren: sdmmc-pwren {
|
||||
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ vcc5v0_usb30_en_h: vcc5v0-host-en-h {
|
||||
+ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-mmc-highspeed;
|
||||
+ cap-sd-highspeed;
|
||||
+ disable-wp;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_host {
|
||||
+ phy-supply = <&vcc5v0_usb30>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_host {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop {
|
||||
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vop_mmu {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&vp0 {
|
||||
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
|
||||
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
|
||||
+ remote-endpoint = <&hdmi_in_vp0>;
|
||||
+ };
|
||||
+};
|
||||
@ -1,131 +0,0 @@
|
||||
From cc52bfc04726a574fc4440bbbe0c710890e7040a Mon Sep 17 00:00:00 2001
|
||||
From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
|
||||
Date: Wed, 25 Jan 2023 21:40:22 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Enable Ethernet for Radxa CM3 IO
|
||||
|
||||
Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board.
|
||||
|
||||
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230125161023.12115-1-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++
|
||||
1 file changed, 93 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
@@ -21,6 +21,13 @@
|
||||
stdout-path = "serial2:1500000n8";
|
||||
};
|
||||
|
||||
+ gmac1_clkin: external-gmac1-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac1_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
hdmi-con {
|
||||
compatible = "hdmi-connector";
|
||||
type = "a";
|
||||
@@ -83,6 +90,29 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&gmac1 {
|
||||
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
|
||||
+ assigned-clock-rates = <0>, <125000000>;
|
||||
+ clock_in_out = "input";
|
||||
+ phy-handle = <&rgmii_phy1>;
|
||||
+ phy-mode = "rgmii";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&gmac1m0_miim
|
||||
+ &gmac1m0_tx_bus2
|
||||
+ &gmac1m0_rx_bus2
|
||||
+ &gmac1m0_rgmii_clk
|
||||
+ &gmac1m0_rgmii_bus
|
||||
+ &gmac1m0_clkinout>;
|
||||
+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
|
||||
+ snps,reset-active-low;
|
||||
+ /* Reset time is 20ms, 100ms for rtl8211f */
|
||||
+ snps,reset-delays-us = <0 20000 100000>;
|
||||
+ tx_delay = <0x46>;
|
||||
+ rx_delay = <0x2e>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&hdmi {
|
||||
avdd-0v9-supply = <&vdda0v9_image>;
|
||||
avdd-1v8-supply = <&vcca1v8_image>;
|
||||
@@ -105,7 +135,70 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&mdio1 {
|
||||
+ rgmii_phy1: ethernet-phy@0 {
|
||||
+ compatible="ethernet-phy-ieee802.3-c22";
|
||||
+ reg= <0x0>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&pinctrl {
|
||||
+ gmac1 {
|
||||
+ gmac1m0_miim: gmac1m0-miim {
|
||||
+ rockchip,pins =
|
||||
+ /* gmac1_mdcm0 */
|
||||
+ <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
|
||||
+ /* gmac1_mdiom0 */
|
||||
+ <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
|
||||
+ rockchip,pins =
|
||||
+ /* gmac1_rxd0m0 */
|
||||
+ <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
|
||||
+ /* gmac1_rxd1m0 */
|
||||
+ <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
|
||||
+ /* gmac1_rxdvcrsm0 */
|
||||
+ <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
|
||||
+ rockchip,pins =
|
||||
+ /* gmac1_txd0m0 */
|
||||
+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
|
||||
+ /* gmac1_txd1m0 */
|
||||
+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
|
||||
+ /* gmac1_txenm0 */
|
||||
+ <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
|
||||
+ rockchip,pins =
|
||||
+ /* gmac1_rxclkm0 */
|
||||
+ <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
|
||||
+ /* gmac1_txclkm0 */
|
||||
+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
|
||||
+ rockchip,pins =
|
||||
+ /* gmac1_rxd2m0 */
|
||||
+ <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
|
||||
+ /* gmac1_rxd3m0 */
|
||||
+ <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
|
||||
+ /* gmac1_txd2m0 */
|
||||
+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
|
||||
+ /* gmac1_txd3m0 */
|
||||
+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
|
||||
+ };
|
||||
+
|
||||
+ gmac1m0_clkinout: gmac1m0-clkinout {
|
||||
+ rockchip,pins =
|
||||
+ /* gmac1_mclkinoutm0 */
|
||||
+ <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
pi_nled_activity: pi-nled-activity {
|
||||
rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
@ -1,386 +0,0 @@
|
||||
From 7469ab529bcad50490f6ff651c3e4f03bfa88fe0 Mon Sep 17 00:00:00 2001
|
||||
From: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Date: Thu, 12 Jan 2023 16:29:01 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Radxa Compute Module 3(CM3) is one of the modules from a series
|
||||
System On Module based on the Radxa ROCK 3 series and is compatible
|
||||
with Raspberry Pi CM4 pinout and form factor.
|
||||
|
||||
Specification:
|
||||
- Rockchip RK3566
|
||||
- up to 8GB LPDDR4
|
||||
- up to 128GB high performance eMMC
|
||||
- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
|
||||
BT 5.0, BLE with onboard and external antenna.
|
||||
- Gigabit Ethernet PHY
|
||||
|
||||
Radxa CM3 needs to mount on top of this IO board in order to create
|
||||
complete Radxa CM3 IO board platform.
|
||||
|
||||
Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
|
||||
possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.
|
||||
|
||||
Add support for Radxa CM3.
|
||||
|
||||
Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230112105902.192852-2-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 345 ++++++++++++++++++
|
||||
1 file changed, 345 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
|
||||
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
|
||||
@@ -0,0 +1,345 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+/*
|
||||
+ * Copyright (c) 2022 Radxa Limited
|
||||
+ * Copyright (c) 2022 Amarula Solutions(India)
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+
|
||||
+/ {
|
||||
+ compatible = "radxa,radxa-cm3", "rockchip,rk3566";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led-0 {
|
||||
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ function = LED_FUNCTION_STATUS;
|
||||
+ linux,default-trigger = "timer";
|
||||
+ default-state = "on";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&user_led2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_sys: vcc-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: vcc-1v8-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc_1v8_p>;
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: vcc-3v3-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: vcca-1v8-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc_1v8_p>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu_npu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <712500>;
|
||||
+ regulator-max-microvolt = <1390000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk817: pmic@20 {
|
||||
+ compatible = "rockchip,rk817";
|
||||
+ reg = <0x20>;
|
||||
+ #clock-cells = <1>;
|
||||
+ clock-output-names = "rk817-clkout1", "rk817-clkout2";
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int_l>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc_sys>;
|
||||
+ vcc2-supply = <&vcc_sys>;
|
||||
+ vcc3-supply = <&vcc_sys>;
|
||||
+ vcc4-supply = <&vcc_sys>;
|
||||
+ vcc5-supply = <&vcc_sys>;
|
||||
+ vcc6-supply = <&vcc_sys>;
|
||||
+ vcc7-supply = <&vcc_sys>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu_npu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu_npu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: DCDC_REG4 {
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG1 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8_p: LDO_REG7 {
|
||||
+ regulator-name = "vcc_1v8_p";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc1v8_dvp: LDO_REG8 {
|
||||
+ regulator-name = "vcc1v8_dvp";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc2v8_dvp: LDO_REG9 {
|
||||
+ regulator-name = "vcc2v8_dvp";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <2800000>;
|
||||
+ regulator-max-microvolt = <2800000>;
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ pmic {
|
||||
+ pmic_int_l: pmic-int-l {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ leds {
|
||||
+ user_led2: user-led2 {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc_3v3>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio2-supply = <&vcc_1v8>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_3v3>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ mmc-hs200-1_8v;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ vmmc-supply = <&vcc_3v3>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -1,134 +0,0 @@
|
||||
From af5a803bf212e077e5fb7a1d4cf6be02f74a74ca Mon Sep 17 00:00:00 2001
|
||||
From: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Date: Wed, 25 Jan 2023 21:40:23 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: rk3566: Enable WiFi, BT support for
|
||||
Radxa CM3
|
||||
|
||||
Radxa Compute Module 3 has an onboard AW_CM256SM WiFi/BT module.
|
||||
|
||||
Add nodes for enabling it.
|
||||
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230125161023.12115-2-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 80 +++++++++++++++++++
|
||||
1 file changed, 80 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
|
||||
@@ -66,6 +66,15 @@
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&vcc_1v8_p>;
|
||||
};
|
||||
+
|
||||
+ sdio_pwrseq: pwrseq-sdio {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk817 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_reg_on_h>;
|
||||
+ reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
@@ -287,6 +296,20 @@
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
+ bluetooth {
|
||||
+ bt_host_wake_h: bt-host-wake-h {
|
||||
+ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_reg_on_h: bt-reg-on-h {
|
||||
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_wake_host_h: bt-wake-host-h {
|
||||
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
pmic {
|
||||
pmic_int_l: pmic-int-l {
|
||||
rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
@@ -298,6 +321,16 @@
|
||||
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ wifi {
|
||||
+ wifi_reg_on_h: wifi-reg-on-h {
|
||||
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ wifi_host_wake_h: wifi-host-wake-h {
|
||||
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
@@ -318,6 +351,34 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&sdmmc1 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ bus-width = <4>;
|
||||
+ disable-wp;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc_3v3>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ wifi@1 {
|
||||
+ compatible = "brcm,bcm43455-fmac";
|
||||
+ reg = <1>;
|
||||
+ interrupt-parent = <&gpio2>;
|
||||
+ interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-names = "host-wake";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_host_wake_h>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&sdhci {
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
@@ -330,6 +391,25 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&uart1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ bluetooth {
|
||||
+ compatible = "brcm,bcm4345c5";
|
||||
+ clocks = <&rk817 1>;
|
||||
+ clock-names = "lpo";
|
||||
+ device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
+ host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
+ reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
|
||||
+ vbat-supply = <&vcc_3v3>;
|
||||
+ vddio-supply = <&vcc_1v8>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&usb2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -1,32 +0,0 @@
|
||||
From 477ed3ade6a46e445b4e2348b710c51df4f6f4b1 Mon Sep 17 00:00:00 2001
|
||||
From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
|
||||
Date: Thu, 23 Feb 2023 19:29:29 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Enable USB OTG for rk3566 Radxa CM3
|
||||
|
||||
Enable USB OTG support for Radxa Compute Module 3 IO Board
|
||||
|
||||
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230223135929.630787-1-abbaraju.manojsai@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
@@ -254,6 +254,14 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&usb2phy0_otg {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&vop {
|
||||
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
|
||||
assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
||||
@ -1,45 +0,0 @@
|
||||
From 8f19828844f20b22182719cf53be64f8c955aee8 Mon Sep 17 00:00:00 2001
|
||||
From: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Date: Mon, 23 Jan 2023 12:46:50 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Fix compatible for Radxa CM3
|
||||
|
||||
The compatible string "radxa,radxa-cm3" referring the product name
|
||||
as "Radxa Radxa CM3" but the actual product name is "Radxa CM3".
|
||||
|
||||
Fix the compatible strings.
|
||||
|
||||
Fixes: 24a28d3eb07d ("dt-bindings: arm: rockchip: Add Radxa Compute Module 3")
|
||||
Fixes: 7469ab529bca ("arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3")
|
||||
Fixes: 096ebfb74b19 ("arm64: dts: rockchip: Add Radxa Compute Module 3 IO board")
|
||||
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230123071654.73139-1-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 2 +-
|
||||
arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 2 +-
|
||||
2 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
@@ -11,7 +11,7 @@
|
||||
|
||||
/ {
|
||||
model = "Radxa Compute Module 3(CM3) IO Board";
|
||||
- compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
|
||||
+ compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
|
||||
|
||||
aliases {
|
||||
mmc1 = &sdmmc0;
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
|
||||
@@ -8,7 +8,7 @@
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
- compatible = "radxa,radxa-cm3", "rockchip,rk3566";
|
||||
+ compatible = "radxa,cm3", "rockchip,rk3566";
|
||||
|
||||
aliases {
|
||||
mmc0 = &sdhci;
|
||||
@ -1,28 +0,0 @@
|
||||
From f99a75f11f46a24dabb33e90893eebf61dca0566 Mon Sep 17 00:00:00 2001
|
||||
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Date: Sun, 2 Jul 2023 20:52:42 +0200
|
||||
Subject: [PATCH] arm64: dts: rockchip: minor whitespace cleanup around '='
|
||||
|
||||
The DTS code coding style expects exactly one space before and after '='
|
||||
sign.
|
||||
|
||||
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230702185242.44421-1-krzysztof.kozlowski@linaro.org
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 4 ++--
|
||||
1 files changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
|
||||
@@ -137,8 +137,8 @@
|
||||
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
- compatible="ethernet-phy-ieee802.3-c22";
|
||||
- reg= <0x0>;
|
||||
+ compatible = "ethernet-phy-ieee802.3-c22";
|
||||
+ reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,32 +0,0 @@
|
||||
From 64b69474edf3b885c19a89bb165f978ba1b4be00 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Tue, 10 Jan 2023 22:55:50 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x
|
||||
|
||||
clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
|
||||
and not to 32 kHz on RK356x.
|
||||
|
||||
Fix this by assigning clk_rtc_32k a rate of 32768, also assign the parent
|
||||
to clk_rtc32k_frac.
|
||||
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20230110225547.1563119-2-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++--
|
||||
1 file changed, 3 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -422,8 +422,9 @@
|
||||
clock-names = "xin24m";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
- assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
- assigned-clock-rates = <1200000000>, <200000000>;
|
||||
+ assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
|
||||
+ assigned-clock-rates = <32768>, <1200000000>, <200000000>;
|
||||
+ assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
|
||||
rockchip,grf = <&grf>;
|
||||
};
|
||||
|
||||
@ -1,81 +0,0 @@
|
||||
From 49665ab0ed5eed4fa7b8a6b236ff2df681c89673 Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Thu, 6 Oct 2022 23:25:23 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add regulator suffix to rock-3a
|
||||
|
||||
Add -regulator suffix to regulator names on Radxa ROCK3 Model A
|
||||
board. This makes the naming more consistent.
|
||||
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Acked-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20221006152524.502445-2-amadeus@jmu.edu.cn
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 14 +++++++-------
|
||||
1 file changed, 7 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
@@ -60,7 +60,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
- vcc12v_dcin: vcc12v-dcin {
|
||||
+ vcc12v_dcin: vcc12v-dcin-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
regulator-always-on;
|
||||
@@ -79,7 +79,7 @@
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
- vcc3v3_sys: vcc3v3-sys {
|
||||
+ vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_sys";
|
||||
regulator-always-on;
|
||||
@@ -89,7 +89,7 @@
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
- vcc5v0_sys: vcc5v0-sys {
|
||||
+ vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_sys";
|
||||
regulator-always-on;
|
||||
@@ -99,7 +99,7 @@
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
- vcc5v0_usb: vcc5v0-usb {
|
||||
+ vcc5v0_usb: vcc5v0-usb-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_usb";
|
||||
regulator-always-on;
|
||||
@@ -109,7 +109,7 @@
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
- vcc5v0_usb_host: vcc5v0-usb-host {
|
||||
+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
@@ -144,7 +144,7 @@
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
};
|
||||
|
||||
- vcc_cam: vcc-cam {
|
||||
+ vcc_cam: vcc-cam-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
|
||||
@@ -160,7 +160,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
- vcc_mipi: vcc-mipi {
|
||||
+ vcc_mipi: vcc-mipi-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
|
||||
@ -1,75 +0,0 @@
|
||||
From 0522cd8112204d124d714eee7e9f0cac6de999d9 Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Thu, 6 Oct 2022 23:25:24 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add PCIe v3 nodes to rock-3a
|
||||
|
||||
Add Nodes to Radxa ROCK3 Model A board to support PCIe v3.
|
||||
|
||||
Tested-by: Anand Moon <linux.amoon@gmail.com>
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Link: https://lore.kernel.org/r/20221006152524.502445-3-amadeus@jmu.edu.cn
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3568-rock-3a.dts | 44 +++++++++++++++++++
|
||||
1 file changed, 44 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
@@ -67,6 +67,37 @@
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ /* pi6c pcie clock generator */
|
||||
+ vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_pi6c_03";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
vcc3v3_pcie: vcc3v3-pcie-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
@@ -546,6 +577,19 @@
|
||||
vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
status = "okay";
|
||||
};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ phy-supply = <&vcc3v3_pi6c_03>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie30x2m1_pins>;
|
||||
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
|
||||
&pinctrl {
|
||||
cam {
|
||||
@ -1,45 +0,0 @@
|
||||
From 755f37010f3eac0bdfa41bdf2308e8380a93f10c Mon Sep 17 00:00:00 2001
|
||||
From: Shengyu Qu <wiagn233@outlook.com>
|
||||
Date: Sun, 30 Oct 2022 01:09:04 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: RK356x: Add I2S2 device node
|
||||
|
||||
This patch adds I2S2 device tree node for RK3566/RK3568.
|
||||
|
||||
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
|
||||
Link: https://lore.kernel.org/r/OS3P286MB259771C12F2B15A4DDF435FE98359@OS3P286MB2597.JPNP286.PROD.OUTLOOK.COM
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 22 ++++++++++++++++++++++
|
||||
1 file changed, 22 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -1108,6 +1108,28 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
+ i2s2_2ch: i2s@fe420000 {
|
||||
+ compatible = "rockchip,rk3568-i2s-tdm";
|
||||
+ reg = <0x0 0xfe420000 0x0 0x1000>;
|
||||
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
|
||||
+ assigned-clock-rates = <1188000000>;
|
||||
+ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
|
||||
+ clock-names = "mclk_tx", "mclk_rx", "hclk";
|
||||
+ dmas = <&dmac1 4>, <&dmac1 5>;
|
||||
+ dma-names = "tx", "rx";
|
||||
+ resets = <&cru SRST_M_I2S2_2CH>;
|
||||
+ reset-names = "m";
|
||||
+ rockchip,grf = <&grf>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&i2s2m0_sclktx
|
||||
+ &i2s2m0_lrcktx
|
||||
+ &i2s2m0_sdi
|
||||
+ &i2s2m0_sdo>;
|
||||
+ #sound-dai-cells = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
i2s3_2ch: i2s@fe430000 {
|
||||
compatible = "rockchip,rk3568-i2s-tdm";
|
||||
reg = <0x0 0xfe430000 0x0 0x1000>;
|
||||
@ -1,39 +0,0 @@
|
||||
From 0fc19ab75acde78558bd0f6fe3e5f63cf8ee88b0 Mon Sep 17 00:00:00 2001
|
||||
From: Heiko Stuebner <heiko@sntech.de>
|
||||
Date: Tue, 27 Feb 2024 18:35:26 +0100
|
||||
Subject: [PATCH] arm64: dts: rockchip: fix reset-names for rk356x i2s2
|
||||
controller
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
The dtbscheck reports a warning for a wrong reset-names property for
|
||||
the i2s2 controller on rk356x socs.
|
||||
|
||||
The other controllers on the soc provide tx and rx directions and hence
|
||||
two resets and separate clocks for each direction, while i2s2 only
|
||||
provides one reset. This was so far named just "m" which isn't part of
|
||||
the binding.
|
||||
|
||||
The clock-names the controller uses all end in "tx", so use the matching
|
||||
"tx-m" reset-name for the i2s controller.
|
||||
|
||||
Fixes: 755f37010f3e ("arm64: dts: rockchip: RK356x: Add I2S2 device node")
|
||||
Acked-by: Uwe Kleine-König <ukleinek@debian.org>
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20240227173526.710056-2-heiko@sntech.de
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
|
||||
@@ -1119,7 +1119,7 @@
|
||||
dmas = <&dmac1 4>, <&dmac1 5>;
|
||||
dma-names = "tx", "rx";
|
||||
resets = <&cru SRST_M_I2S2_2CH>;
|
||||
- reset-names = "m";
|
||||
+ reset-names = "tx-m";
|
||||
rockchip,grf = <&grf>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2s2m0_sclktx
|
||||
@ -1,30 +0,0 @@
|
||||
From 3a6dcf61d542fb1f4fbd546a9df91938440ece3a Mon Sep 17 00:00:00 2001
|
||||
From: Shengyu Qu <wiagn233@outlook.com>
|
||||
Date: Sun, 30 Oct 2022 01:09:06 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add I2S2 node for RADXA Rock 3A
|
||||
|
||||
This patch adds I2S2 node for Radxa Rock 3A's M.2 E key slot for
|
||||
Bluetooth PCM input. I2S2 is not used now, but could be configured
|
||||
for Bluetooth HFP over PCM in future patches.
|
||||
|
||||
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
|
||||
Link: https://lore.kernel.org/r/OS3P286MB259791E603F96942F51332D098359@OS3P286MB2597.JPNP286.PROD.OUTLOOK.COM
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
@@ -558,6 +558,11 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&i2s2_2ch {
|
||||
+ rockchip,trcm-sync-tx-only;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&mdio1 {
|
||||
rgmii_phy1: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
@ -1,115 +0,0 @@
|
||||
From 8cf890aabd45664b8f27a5581c8d2a51a8ce2e17 Mon Sep 17 00:00:00 2001
|
||||
From: Shengyu Qu <wiagn233@outlook.com>
|
||||
Date: Sun, 30 Oct 2022 01:09:08 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add nodes for SDIO/UART Wi-Fi/Bluetooth
|
||||
modules to Radxa Rock 3A
|
||||
|
||||
This patch adds related bus/pinctrl/power nodes to enable support for
|
||||
Radxa's Wi-Fi Bluetooth combo module.
|
||||
Tested with RADXA A6 module, which uses AP6275S (BCM43752A2)
|
||||
|
||||
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
|
||||
Link: https://lore.kernel.org/r/OS3P286MB25972313C916A68698B1CD8698359@OS3P286MB2597.JPNP286.PROD.OUTLOOK.COM
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../boot/dts/rockchip/rk3568-rock-3a.dts | 69 +++++++++++++++++++
|
||||
1 file changed, 69 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
@@ -60,6 +60,17 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ sdio_pwrseq: sdio-pwrseq {
|
||||
+ compatible = "mmc-pwrseq-simple";
|
||||
+ clocks = <&rk809 1>;
|
||||
+ clock-names = "ext_clock";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&wifi_enable>;
|
||||
+ post-power-on-delay-ms = <100>;
|
||||
+ power-off-delay-us = <5000000>;
|
||||
+ reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
|
||||
+ };
|
||||
+
|
||||
vcc12v_dcin: vcc12v-dcin-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc12v_dcin";
|
||||
@@ -655,6 +666,26 @@
|
||||
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
+
|
||||
+ bt {
|
||||
+ bt_enable: bt-enable {
|
||||
+ rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ bt_host_wake: bt-host-wake {
|
||||
+ rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
|
||||
+ };
|
||||
+
|
||||
+ bt_wake: bt-wake {
|
||||
+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ sdio-pwrseq {
|
||||
+ wifi_enable: wifi-enable {
|
||||
+ rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
|
||||
&pmu_io_domains {
|
||||
@@ -699,12 +730,50 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&sdmmc2 {
|
||||
+ supports-sdio;
|
||||
+ bus-width = <4>;
|
||||
+ disable-wp;
|
||||
+ cap-sd-highspeed;
|
||||
+ cap-sdio-irq;
|
||||
+ keep-power-in-suspend;
|
||||
+ mmc-pwrseq = <&sdio_pwrseq>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc3v3_sys>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&tsadc {
|
||||
rockchip,hw-tshut-mode = <1>;
|
||||
rockchip,hw-tshut-polarity = <0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&uart1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
|
||||
+ uart-has-rtscts;
|
||||
+ status = "okay";
|
||||
+
|
||||
+ bluetooth {
|
||||
+ compatible = "brcm,bcm43438-bt";
|
||||
+ clocks = <&rk809 1>;
|
||||
+ clock-names = "lpo";
|
||||
+ device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
|
||||
+ host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
|
||||
+ shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
|
||||
+ vbat-supply = <&vcc3v3_sys>;
|
||||
+ vddio-supply = <&vcc_1v8>;
|
||||
+ /* vddio comes from regulator on module, use IO bank voltage instead */
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -1,54 +0,0 @@
|
||||
From ef9f4b4a50206bedd931f45dd9fd57fd4c1714a6 Mon Sep 17 00:00:00 2001
|
||||
From: Anand Moon <linux.amoon@gmail.com>
|
||||
Date: Wed, 16 Nov 2022 20:01:44 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add support of external clock to
|
||||
ethernet node on Rock 3A SBC
|
||||
|
||||
Add support of external clock gmac1_clkin which is used as input clock
|
||||
to ethernet node.
|
||||
|
||||
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
|
||||
Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20221116200150.4657-3-linux.amoon@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 13 ++++++++++---
|
||||
1 file changed, 10 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
@@ -32,6 +32,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
+ gmac1_clkin: external-gmac1-clock {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <125000000>;
|
||||
+ clock-output-names = "gmac1_clkin";
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
@@ -249,9 +256,8 @@
|
||||
|
||||
&gmac1 {
|
||||
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
|
||||
- assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
|
||||
- assigned-clock-rates = <0>, <125000000>;
|
||||
- clock_in_out = "output";
|
||||
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
|
||||
+ clock_in_out = "input";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
@@ -259,6 +265,7 @@
|
||||
&gmac1m1_tx_bus2
|
||||
&gmac1m1_rx_bus2
|
||||
&gmac1m1_rgmii_clk
|
||||
+ &gmac1m1_clkinout
|
||||
&gmac1m1_rgmii_bus>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -1,30 +0,0 @@
|
||||
From 79aa02ddc682558edb9bd56522ad841759c99201 Mon Sep 17 00:00:00 2001
|
||||
From: Anand Moon <linux.amoon@gmail.com>
|
||||
Date: Wed, 16 Nov 2022 20:01:45 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add support of regulator for ethernet
|
||||
node on Rock 3A SBC
|
||||
|
||||
Add regulator support for ethernet node
|
||||
|
||||
Fix following warning.
|
||||
[ 7.365199] rk_gmac-dwmac fe010000.ethernet: no regulator found
|
||||
|
||||
Signed-off-by: Anand Moon <linux.amoon@gmail.com>
|
||||
Acked-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
|
||||
Link: https://lore.kernel.org/r/20221116200150.4657-4-linux.amoon@gmail.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
@@ -260,6 +260,7 @@
|
||||
clock_in_out = "input";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
+ phy-supply = <&vcc_3v3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gmac1m1_miim
|
||||
&gmac1m1_tx_bus2
|
||||
@ -1,26 +0,0 @@
|
||||
From 0b693c8f8b88d50114caaa4d2337932d4d172631 Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Mon, 19 Dec 2022 18:10:52 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: remove unsupported property from sdmmc2
|
||||
for rock-3a
|
||||
|
||||
'supports-sdio' is not part of the DT binding
|
||||
and not supported by the Linux driver.
|
||||
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Link: https://lore.kernel.org/r/20221219101052.7899-1-amadeus@jmu.edu.cn
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
@@ -739,7 +739,6 @@
|
||||
};
|
||||
|
||||
&sdmmc2 {
|
||||
- supports-sdio;
|
||||
bus-width = <4>;
|
||||
disable-wp;
|
||||
cap-sd-highspeed;
|
||||
@ -1,61 +0,0 @@
|
||||
From d268da063b99cf1c4d8304a33c27bbed0763a474 Mon Sep 17 00:00:00 2001
|
||||
From: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Date: Wed, 18 Jan 2023 13:34:54 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Update eMMC, SD aliases for Radxa SBC
|
||||
boards
|
||||
|
||||
Radxa SBC boards like ROCK 3A/4 models do support eMMC and SDcard
|
||||
via external connector slots.
|
||||
|
||||
Mark, the eMMC has mmc0 by considering the Rockchip boot order priority
|
||||
as both MMC devices are connected externally.
|
||||
|
||||
Reported-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230118080454.11643-2-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 4 ++--
|
||||
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi | 4 ++--
|
||||
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 4 ++--
|
||||
3 files changed, 6 insertions(+), 6 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
|
||||
@@ -15,8 +15,8 @@
|
||||
compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
|
||||
|
||||
aliases {
|
||||
- mmc0 = &sdmmc;
|
||||
- mmc1 = &sdhci;
|
||||
+ mmc0 = &sdhci;
|
||||
+ mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
|
||||
@@ -13,8 +13,8 @@
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
- mmc0 = &sdmmc;
|
||||
- mmc1 = &sdhci;
|
||||
+ mmc0 = &sdhci;
|
||||
+ mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
|
||||
@@ -13,8 +13,8 @@
|
||||
|
||||
aliases {
|
||||
ethernet0 = &gmac1;
|
||||
- mmc0 = &sdmmc0;
|
||||
- mmc1 = &sdhci;
|
||||
+ mmc0 = &sdhci;
|
||||
+ mmc1 = &sdmmc0;
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
@ -27,7 +27,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
};
|
||||
|
||||
chosen: chosen {
|
||||
@@ -748,6 +749,9 @@
|
||||
@@ -747,6 +748,9 @@
|
||||
non-removable;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
|
||||
|
||||
@ -1,690 +0,0 @@
|
||||
From 2bf2f4d9f673013a58109626b87329310537a611 Mon Sep 17 00:00:00 2001
|
||||
From: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Date: Fri, 9 Dec 2022 18:25:24 +0800
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add Radxa CM3I E25
|
||||
|
||||
Radxa E25 is a network application carrier board for the Radxa CM3
|
||||
Industrial (CM3I) SoM, which is based on the Rockchip RK3568 SoC.
|
||||
|
||||
It has the following features:
|
||||
|
||||
- MicroSD card socket, on board eMMC flash
|
||||
- 2x 2.5GbE Realtek RTL8125B Ethernet transceiver
|
||||
- 1x USB Type-C port (Power and Serial console)
|
||||
- 1x USB 3.0 OTG port
|
||||
- mini PCIe socket (USB or PCIe)
|
||||
- ngff PCIe socket (USB or SATA)
|
||||
- 1x User LED and 16x RGB LEDs
|
||||
- 26-pin expansion header
|
||||
|
||||
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Link: https://lore.kernel.org/r/20221209102524.129367-3-amadeus@jmu.edu.cn
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/Makefile | 1 +
|
||||
.../boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 416 ++++++++++++++++++
|
||||
.../boot/dts/rockchip/rk3568-radxa-e25.dts | 229 ++++++++++
|
||||
3 files changed, 646 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
|
||||
create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/Makefile
|
||||
+++ b/arch/arm64/boot/dts/rockchip/Makefile
|
||||
@@ -80,5 +80,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fa
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
|
||||
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-roc-pc.dtb
|
||||
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
|
||||
@@ -0,0 +1,416 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+#include <dt-bindings/gpio/gpio.h>
|
||||
+#include <dt-bindings/leds/common.h>
|
||||
+#include <dt-bindings/pinctrl/rockchip.h>
|
||||
+#include "rk3568.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa CM3 Industrial Board";
|
||||
+ compatible = "radxa,cm3i", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial2:115200n8";
|
||||
+ };
|
||||
+
|
||||
+ gpio-leds {
|
||||
+ compatible = "gpio-leds";
|
||||
+
|
||||
+ led_user: led-0 {
|
||||
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
|
||||
+ function = LED_FUNCTION_HEARTBEAT;
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ linux,default-trigger = "heartbeat";
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&led_user_en>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "pcie30_avdd1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+ vin-supply = <&vcc3v3_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sys: vcc3v3-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc3v3_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v_input>;
|
||||
+ };
|
||||
+
|
||||
+ vcc5v0_sys: vcc5v0-sys-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v0_sys";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v_input>;
|
||||
+ };
|
||||
+
|
||||
+ /* labeled +5v_input in schematic */
|
||||
+ vcc5v_input: vcc5v-input-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ regulator-name = "vcc5v_input";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&combphy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&combphy2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&cpu0 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu1 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu2 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&cpu3 {
|
||||
+ cpu-supply = <&vdd_cpu>;
|
||||
+};
|
||||
+
|
||||
+&display_subsystem {
|
||||
+ status = "disabled";
|
||||
+};
|
||||
+
|
||||
+&gpu {
|
||||
+ mali-supply = <&vdd_gpu>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&i2c0 {
|
||||
+ status = "okay";
|
||||
+
|
||||
+ vdd_cpu: regulator@1c {
|
||||
+ compatible = "tcs,tcs4525";
|
||||
+ reg = <0x1c>;
|
||||
+ fcs,suspend-voltage-selector = <1>;
|
||||
+ regulator-name = "vdd_cpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <800000>;
|
||||
+ regulator-max-microvolt = <1150000>;
|
||||
+ regulator-ramp-delay = <2300>;
|
||||
+ vin-supply = <&vcc5v_input>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ rk809: pmic@20 {
|
||||
+ compatible = "rockchip,rk809";
|
||||
+ reg = <0x20>;
|
||||
+ interrupt-parent = <&gpio0>;
|
||||
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
|
||||
+ #clock-cells = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pmic_int>;
|
||||
+ rockchip,system-power-controller;
|
||||
+ wakeup-source;
|
||||
+
|
||||
+ vcc1-supply = <&vcc3v3_sys>;
|
||||
+ vcc2-supply = <&vcc3v3_sys>;
|
||||
+ vcc3-supply = <&vcc3v3_sys>;
|
||||
+ vcc4-supply = <&vcc3v3_sys>;
|
||||
+ vcc5-supply = <&vcc3v3_sys>;
|
||||
+ vcc6-supply = <&vcc3v3_sys>;
|
||||
+ vcc7-supply = <&vcc3v3_sys>;
|
||||
+ vcc8-supply = <&vcc3v3_sys>;
|
||||
+ vcc9-supply = <&vcc3v3_sys>;
|
||||
+
|
||||
+ regulators {
|
||||
+ vdd_logic: DCDC_REG1 {
|
||||
+ regulator-name = "vdd_logic";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_gpu: DCDC_REG2 {
|
||||
+ regulator-name = "vdd_gpu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_ddr: DCDC_REG3 {
|
||||
+ regulator-name = "vcc_ddr";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdd_npu: DCDC_REG4 {
|
||||
+ regulator-name = "vdd_npu";
|
||||
+ regulator-init-microvolt = <900000>;
|
||||
+ regulator-initial-mode = <0x2>;
|
||||
+ regulator-min-microvolt = <500000>;
|
||||
+ regulator-max-microvolt = <1350000>;
|
||||
+ regulator-ramp-delay = <6001>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_1v8: DCDC_REG5 {
|
||||
+ regulator-name = "vcc_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_image: LDO_REG1 {
|
||||
+ regulator-name = "vdda0v9_image";
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda_0v9: LDO_REG2 {
|
||||
+ regulator-name = "vdda_0v9";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vdda0v9_pmu: LDO_REG3 {
|
||||
+ regulator-name = "vdda0v9_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <900000>;
|
||||
+ regulator-max-microvolt = <900000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <900000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_acodec: LDO_REG4 {
|
||||
+ regulator-name = "vccio_acodec";
|
||||
+ regulator-always-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vccio_sd: LDO_REG5 {
|
||||
+ regulator-name = "vccio_sd";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pmu: LDO_REG6 {
|
||||
+ regulator-name = "vcc3v3_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <3300000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca_1v8: LDO_REG7 {
|
||||
+ regulator-name = "vcca_1v8";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_pmu: LDO_REG8 {
|
||||
+ regulator-name = "vcca1v8_pmu";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-on-in-suspend;
|
||||
+ regulator-suspend-microvolt = <1800000>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcca1v8_image: LDO_REG9 {
|
||||
+ regulator-name = "vcca1v8_image";
|
||||
+ regulator-min-microvolt = <1800000>;
|
||||
+ regulator-max-microvolt = <1800000>;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc_3v3: SWITCH_REG1 {
|
||||
+ regulator-name = "vcc_3v3";
|
||||
+ regulator-always-on;
|
||||
+ regulator-boot-on;
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_sd: SWITCH_REG2 {
|
||||
+ regulator-name = "vcc3v3_sd";
|
||||
+
|
||||
+ regulator-state-mem {
|
||||
+ regulator-off-in-suspend;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ leds {
|
||||
+ led_user_en: led_user_en {
|
||||
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmic {
|
||||
+ pmic_int: pmic_int {
|
||||
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pmu_io_domains {
|
||||
+ pmuio1-supply = <&vcc3v3_pmu>;
|
||||
+ pmuio2-supply = <&vcc3v3_pmu>;
|
||||
+ vccio1-supply = <&vccio_acodec>;
|
||||
+ vccio2-supply = <&vcc_1v8>;
|
||||
+ vccio3-supply = <&vccio_sd>;
|
||||
+ vccio4-supply = <&vcc_1v8>;
|
||||
+ vccio5-supply = <&vcc_3v3>;
|
||||
+ vccio6-supply = <&vcc_1v8>;
|
||||
+ vccio7-supply = <&vcc_3v3>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&saradc {
|
||||
+ vref-supply = <&vcca_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdhci {
|
||||
+ bus-width = <8>;
|
||||
+ max-frequency = <200000000>;
|
||||
+ non-removable;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
|
||||
+ vmmc-supply = <&vcc_3v3>;
|
||||
+ vqmmc-supply = <&vcc_1v8>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&tsadc {
|
||||
+ rockchip,hw-tshut-mode = <1>;
|
||||
+ rockchip,hw-tshut-polarity = <0>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&uart2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ extcon = <&usb2phy0>;
|
||||
+};
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
@@ -0,0 +1,229 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
+
|
||||
+/dts-v1/;
|
||||
+#include "rk3568-radxa-cm3i.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Radxa E25";
|
||||
+ compatible = "radxa,e25", "rockchip,rk3568";
|
||||
+
|
||||
+ aliases {
|
||||
+ mmc0 = &sdmmc0;
|
||||
+ mmc1 = &sdhci;
|
||||
+ };
|
||||
+
|
||||
+ pwm-leds {
|
||||
+ compatible = "pwm-leds-multicolor";
|
||||
+
|
||||
+ multi-led {
|
||||
+ color = <LED_COLOR_ID_RGB>;
|
||||
+ max-brightness = <255>;
|
||||
+
|
||||
+ led-red {
|
||||
+ color = <LED_COLOR_ID_RED>;
|
||||
+ pwms = <&pwm1 0 1000000 0>;
|
||||
+ };
|
||||
+
|
||||
+ led-green {
|
||||
+ color = <LED_COLOR_ID_GREEN>;
|
||||
+ pwms = <&pwm2 0 1000000 0>;
|
||||
+ };
|
||||
+
|
||||
+ led-blue {
|
||||
+ color = <LED_COLOR_ID_BLUE>;
|
||||
+ pwms = <&pwm12 0 1000000 0>;
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ vbus_typec: vbus-typec-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&vbus_typec_en>;
|
||||
+ regulator-name = "vbus_typec";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_minipcie: vcc3v3-minipcie-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&minipcie_enable_h>;
|
||||
+ regulator-name = "vcc3v3_minipcie";
|
||||
+ regulator-min-microvolt = <5000000>;
|
||||
+ regulator-max-microvolt = <5000000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_ngff: vcc3v3-ngff-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&ngffpcie_enable_h>;
|
||||
+ regulator-name = "vcc3v3_ngff";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+
|
||||
+ /* actually fed by vcc5v0_sys, dependent
|
||||
+ * on pi6c clock generator
|
||||
+ */
|
||||
+ vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie30x1_enable_h>;
|
||||
+ regulator-name = "vcc3v3_pcie30x1";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc3v3_pi6c_05>;
|
||||
+ };
|
||||
+
|
||||
+ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
|
||||
+ compatible = "regulator-fixed";
|
||||
+ enable-active-high;
|
||||
+ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie_enable_h>;
|
||||
+ regulator-name = "vcc3v3_pcie";
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pcie2x1 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie20_reset_h>;
|
||||
+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie30phy {
|
||||
+ data-lanes = <1 2>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x1 {
|
||||
+ num-lanes = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie30x1m0_pins>;
|
||||
+ reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pcie30x1>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pcie3x2 {
|
||||
+ num-lanes = <1>;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pcie30x2_reset_h>;
|
||||
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pinctrl {
|
||||
+ pcie {
|
||||
+ pcie20_reset_h: pcie20-reset-h {
|
||||
+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30x1_enable_h: pcie30x1-enable-h {
|
||||
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ pcie30x2_reset_h: pcie30x2-reset-h {
|
||||
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ pcie_enable_h: pcie-enable-h {
|
||||
+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ usb {
|
||||
+ minipcie_enable_h: minipcie-enable-h {
|
||||
+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ ngffpcie_enable_h: ngffpcie-enable-h {
|
||||
+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+
|
||||
+ vbus_typec_en: vbus_typec_en {
|
||||
+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&pwm1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm2 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&pwm12 {
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&pwm12m1_pins>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&sdmmc0 {
|
||||
+ bus-width = <4>;
|
||||
+ cap-sd-highspeed;
|
||||
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
+ /* Also used in pcie30x1_clkreqnm0 */
|
||||
+ disable-wp;
|
||||
+ pinctrl-names = "default";
|
||||
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
|
||||
+ sd-uhs-sdr104;
|
||||
+ vmmc-supply = <&vcc3v3_sd>;
|
||||
+ vqmmc-supply = <&vccio_sd>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host0_xhci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ehci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb_host1_ohci {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy0_otg {
|
||||
+ phy-supply = <&vbus_typec>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_host {
|
||||
+ phy-supply = <&vcc3v3_minipcie>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
+&usb2phy1_otg {
|
||||
+ phy-supply = <&vcc3v3_ngff>;
|
||||
+ status = "okay";
|
||||
+};
|
||||
@ -1,48 +0,0 @@
|
||||
From c80992abd2877590059e9cb254213c16824e2106 Mon Sep 17 00:00:00 2001
|
||||
From: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Date: Wed, 18 Jan 2023 13:34:53 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Update eMMC, SD aliases for Radxa SoM
|
||||
boards
|
||||
|
||||
Radxa has produced Compute Modules like RK3399pro VMARC and CM3i with
|
||||
onboarding eMMC flash, so the eMMC is the primary MMC device.
|
||||
|
||||
On the other hand, Rockchip boot orders start from eMMC from an MMC
|
||||
device perspective.
|
||||
|
||||
Mark, the eMMC has mmc0 to satisfy the above two conditions.
|
||||
|
||||
Reported-by: FUKAUMI Naoki <naoki@radxa.com>
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230118080454.11643-1-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 4 ++--
|
||||
arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 3 +--
|
||||
2 files changed, 3 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
|
||||
@@ -13,8 +13,8 @@
|
||||
compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
|
||||
|
||||
aliases {
|
||||
- mmc0 = &sdmmc;
|
||||
- mmc1 = &sdhci;
|
||||
+ mmc0 = &sdhci;
|
||||
+ mmc1 = &sdmmc;
|
||||
};
|
||||
|
||||
vcc3v3_pcie: vcc-pcie-regulator {
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
@@ -8,8 +8,7 @@
|
||||
compatible = "radxa,e25", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
- mmc0 = &sdmmc0;
|
||||
- mmc1 = &sdhci;
|
||||
+ mmc1 = &sdmmc0;
|
||||
};
|
||||
|
||||
pwm-leds {
|
||||
@ -1,35 +0,0 @@
|
||||
From c4d2b02d63ee38b381fbc886c02eecfec4f981cc Mon Sep 17 00:00:00 2001
|
||||
From: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Date: Mon, 23 Jan 2023 12:46:51 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Add missing CM3i fallback compatible
|
||||
for Radxa E25
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
In order to function the Radxa E25 Carrier board, it is mandatory to
|
||||
mount the Radxa CM3i module.
|
||||
|
||||
Add Radxa CM3i compatible as fallback compatible to string to satisfy
|
||||
the Module and Carrier board topology.
|
||||
|
||||
Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
|
||||
Cc: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230123071654.73139-2-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
@@ -5,7 +5,7 @@
|
||||
|
||||
/ {
|
||||
model = "Radxa E25";
|
||||
- compatible = "radxa,e25", "rockchip,rk3568";
|
||||
+ compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
mmc1 = &sdmmc0;
|
||||
@ -1,37 +0,0 @@
|
||||
From 421c059d413812444318d27c1b4d6e71f1c1134c Mon Sep 17 00:00:00 2001
|
||||
From: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Date: Mon, 23 Jan 2023 12:46:52 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Drop unneeded model for Radxa CM3i
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
With module and carrier board topology, carrier board dts will include
|
||||
module dtsi files for creating complete platform.
|
||||
|
||||
The carrier board dts will have final model name and compatible string
|
||||
so any model name added in module dtsi will eventually replaced.
|
||||
|
||||
This happened for any devicetree property if the same property is updated
|
||||
or added twice.
|
||||
|
||||
So, drop this unneeded model name from module dtsi.
|
||||
|
||||
Cc: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230123071654.73139-3-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
|
||||
@@ -6,7 +6,6 @@
|
||||
#include "rk3568.dtsi"
|
||||
|
||||
/ {
|
||||
- model = "Radxa CM3 Industrial Board";
|
||||
compatible = "radxa,cm3i", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
@ -1,28 +0,0 @@
|
||||
From ef9134d9bbce071c9e4ebdcbb6f8fb1a5dd0a67e Mon Sep 17 00:00:00 2001
|
||||
From: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Date: Mon, 23 Jan 2023 12:46:53 +0530
|
||||
Subject: [PATCH] arm64: dts: rockchip: Correct the model name for Radxa E25
|
||||
|
||||
Radxa E25 is a Carrier board, so update the model name for Radxa E25
|
||||
as suggested by the Radxa website.
|
||||
|
||||
Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
|
||||
Cc: Chukun Pan <amadeus@jmu.edu.cn>
|
||||
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
|
||||
Link: https://lore.kernel.org/r/20230123071654.73139-4-jagan@amarulasolutions.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
@@ -4,7 +4,7 @@
|
||||
#include "rk3568-radxa-cm3i.dtsi"
|
||||
|
||||
/ {
|
||||
- model = "Radxa E25";
|
||||
+ model = "Radxa E25 Carrier Board";
|
||||
compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
|
||||
|
||||
aliases {
|
||||
@ -1,79 +0,0 @@
|
||||
From a87852e37f782257ebc57cc44a0d3fbf806471f6 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 24 Jul 2023 14:52:16 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Fix PCIe regulators on Radxa E25
|
||||
|
||||
Despite its name, the regulator vcc3v3_pcie30x1 has nothing to do with
|
||||
pcie30x1. Instead, it supply power to VBAT1-5 on the M.2 KEY B port as
|
||||
seen on page 8 of the schematic [1].
|
||||
|
||||
pcie30x1 is used for the mini PCIe slot, and as seen on page 9 the
|
||||
vcc3v3_minipcie regulator is instead related to pcie30x1.
|
||||
|
||||
The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives.
|
||||
|
||||
Use correct regulator vcc3v3_minipcie for pcie30x1.
|
||||
|
||||
[1] https://dl.radxa.com/cm3p/e25/radxa-e25-v1.4-sch.pdf
|
||||
|
||||
Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 16 ++++++++--------
|
||||
1 file changed, 8 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
@@ -47,6 +47,9 @@
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
+ /* actually fed by vcc5v0_sys, dependent
|
||||
+ * on pi6c clock generator
|
||||
+ */
|
||||
vcc3v3_minipcie: vcc3v3-minipcie-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
@@ -54,9 +57,9 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&minipcie_enable_h>;
|
||||
regulator-name = "vcc3v3_minipcie";
|
||||
- regulator-min-microvolt = <5000000>;
|
||||
- regulator-max-microvolt = <5000000>;
|
||||
- vin-supply = <&vcc5v0_sys>;
|
||||
+ regulator-min-microvolt = <3300000>;
|
||||
+ regulator-max-microvolt = <3300000>;
|
||||
+ vin-supply = <&vcc3v3_pi6c_05>;
|
||||
};
|
||||
|
||||
vcc3v3_ngff: vcc3v3-ngff-regulator {
|
||||
@@ -71,9 +74,6 @@
|
||||
vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
- /* actually fed by vcc5v0_sys, dependent
|
||||
- * on pi6c clock generator
|
||||
- */
|
||||
vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
@@ -83,7 +83,7 @@
|
||||
regulator-name = "vcc3v3_pcie30x1";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
- vin-supply = <&vcc3v3_pi6c_05>;
|
||||
+ vin-supply = <&vcc5v0_sys>;
|
||||
};
|
||||
|
||||
vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
|
||||
@@ -117,7 +117,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie30x1m0_pins>;
|
||||
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
- vpcie3v3-supply = <&vcc3v3_pcie30x1>;
|
||||
+ vpcie3v3-supply = <&vcc3v3_minipcie>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -1,41 +0,0 @@
|
||||
From 2bdfe84fbd57a4ed9fd65a67210442559ce078f0 Mon Sep 17 00:00:00 2001
|
||||
From: Jonas Karlman <jonas@kwiboo.se>
|
||||
Date: Mon, 24 Jul 2023 14:52:16 +0000
|
||||
Subject: [PATCH] arm64: dts: rockchip: Enable SATA on Radxa E25
|
||||
|
||||
The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives.
|
||||
|
||||
Enable sata1 node to fix use of SATA drives on the M.2 slot.
|
||||
|
||||
Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
|
||||
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
|
||||
Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 8 ++++++++
|
||||
1 file changed, 8 insertions(+)
|
||||
|
||||
--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
|
||||
@@ -99,6 +99,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
+&combphy1 {
|
||||
+ phy-supply = <&vcc3v3_pcie30x1>;
|
||||
+};
|
||||
+
|
||||
&pcie2x1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie20_reset_h>;
|
||||
@@ -178,6 +182,10 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
+&sata1 {
|
||||
+ status = "okay";
|
||||
+};
|
||||
+
|
||||
&sdmmc0 {
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
@ -1,792 +0,0 @@
|
||||
From f204a60e545ccd4bc28939054389690fd194cb5e Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 18 Oct 2022 17:13:59 +0200
|
||||
Subject: [PATCH] dt-bindings: clock: add rk3588 clock definitions
|
||||
|
||||
Add clock ID defines for rk3588.
|
||||
|
||||
Compared to the downstream bindings written by Elaine, this uses
|
||||
continous gapless clock IDs starting at 0. Thus all numbers are
|
||||
different between downstream and upstream, but I kept exactly the
|
||||
same names.
|
||||
|
||||
Co-Developed-by: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Acked-by: Rob Herring <robh@kernel.org>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221018151407.63395-2-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../dt-bindings/clock/rockchip,rk3588-cru.h | 766 ++++++++++++++++++
|
||||
1 file changed, 766 insertions(+)
|
||||
create mode 100644 include/dt-bindings/clock/rockchip,rk3588-cru.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
|
||||
@@ -0,0 +1,766 @@
|
||||
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
|
||||
+/*
|
||||
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
+ * Copyright (c) 2022 Collabora Ltd.
|
||||
+ *
|
||||
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
+ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
+ */
|
||||
+
|
||||
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
|
||||
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
|
||||
+
|
||||
+/* cru-clocks indices */
|
||||
+
|
||||
+#define PLL_B0PLL 0
|
||||
+#define PLL_B1PLL 1
|
||||
+#define PLL_LPLL 2
|
||||
+#define PLL_V0PLL 3
|
||||
+#define PLL_AUPLL 4
|
||||
+#define PLL_CPLL 5
|
||||
+#define PLL_GPLL 6
|
||||
+#define PLL_NPLL 7
|
||||
+#define PLL_PPLL 8
|
||||
+#define ARMCLK_L 9
|
||||
+#define ARMCLK_B01 10
|
||||
+#define ARMCLK_B23 11
|
||||
+#define PCLK_BIGCORE0_ROOT 12
|
||||
+#define PCLK_BIGCORE0_PVTM 13
|
||||
+#define PCLK_BIGCORE1_ROOT 14
|
||||
+#define PCLK_BIGCORE1_PVTM 15
|
||||
+#define PCLK_DSU_S_ROOT 16
|
||||
+#define PCLK_DSU_ROOT 17
|
||||
+#define PCLK_DSU_NS_ROOT 18
|
||||
+#define PCLK_LITCORE_PVTM 19
|
||||
+#define PCLK_DBG 20
|
||||
+#define PCLK_DSU 21
|
||||
+#define PCLK_S_DAPLITE 22
|
||||
+#define PCLK_M_DAPLITE 23
|
||||
+#define MBIST_MCLK_PDM1 24
|
||||
+#define MBIST_CLK_ACDCDIG 25
|
||||
+#define HCLK_I2S2_2CH 26
|
||||
+#define HCLK_I2S3_2CH 27
|
||||
+#define CLK_I2S2_2CH_SRC 28
|
||||
+#define CLK_I2S2_2CH_FRAC 29
|
||||
+#define CLK_I2S2_2CH 30
|
||||
+#define MCLK_I2S2_2CH 31
|
||||
+#define I2S2_2CH_MCLKOUT 32
|
||||
+#define CLK_DAC_ACDCDIG 33
|
||||
+#define CLK_I2S3_2CH_SRC 34
|
||||
+#define CLK_I2S3_2CH_FRAC 35
|
||||
+#define CLK_I2S3_2CH 36
|
||||
+#define MCLK_I2S3_2CH 37
|
||||
+#define I2S3_2CH_MCLKOUT 38
|
||||
+#define PCLK_ACDCDIG 39
|
||||
+#define HCLK_I2S0_8CH 40
|
||||
+#define CLK_I2S0_8CH_TX_SRC 41
|
||||
+#define CLK_I2S0_8CH_TX_FRAC 42
|
||||
+#define MCLK_I2S0_8CH_TX 43
|
||||
+#define CLK_I2S0_8CH_TX 44
|
||||
+#define CLK_I2S0_8CH_RX_SRC 45
|
||||
+#define CLK_I2S0_8CH_RX_FRAC 46
|
||||
+#define MCLK_I2S0_8CH_RX 47
|
||||
+#define CLK_I2S0_8CH_RX 48
|
||||
+#define I2S0_8CH_MCLKOUT 49
|
||||
+#define HCLK_PDM1 50
|
||||
+#define MCLK_PDM1 51
|
||||
+#define HCLK_AUDIO_ROOT 52
|
||||
+#define PCLK_AUDIO_ROOT 53
|
||||
+#define HCLK_SPDIF0 54
|
||||
+#define CLK_SPDIF0_SRC 55
|
||||
+#define CLK_SPDIF0_FRAC 56
|
||||
+#define MCLK_SPDIF0 57
|
||||
+#define CLK_SPDIF0 58
|
||||
+#define CLK_SPDIF1 59
|
||||
+#define HCLK_SPDIF1 60
|
||||
+#define CLK_SPDIF1_SRC 61
|
||||
+#define CLK_SPDIF1_FRAC 62
|
||||
+#define MCLK_SPDIF1 63
|
||||
+#define ACLK_AV1_ROOT 64
|
||||
+#define ACLK_AV1 65
|
||||
+#define PCLK_AV1_ROOT 66
|
||||
+#define PCLK_AV1 67
|
||||
+#define PCLK_MAILBOX0 68
|
||||
+#define PCLK_MAILBOX1 69
|
||||
+#define PCLK_MAILBOX2 70
|
||||
+#define PCLK_PMU2 71
|
||||
+#define PCLK_PMUCM0_INTMUX 72
|
||||
+#define PCLK_DDRCM0_INTMUX 73
|
||||
+#define PCLK_TOP 74
|
||||
+#define PCLK_PWM1 75
|
||||
+#define CLK_PWM1 76
|
||||
+#define CLK_PWM1_CAPTURE 77
|
||||
+#define PCLK_PWM2 78
|
||||
+#define CLK_PWM2 79
|
||||
+#define CLK_PWM2_CAPTURE 80
|
||||
+#define PCLK_PWM3 81
|
||||
+#define CLK_PWM3 82
|
||||
+#define CLK_PWM3_CAPTURE 83
|
||||
+#define PCLK_BUSTIMER0 84
|
||||
+#define PCLK_BUSTIMER1 85
|
||||
+#define CLK_BUS_TIMER_ROOT 86
|
||||
+#define CLK_BUSTIMER0 87
|
||||
+#define CLK_BUSTIMER1 88
|
||||
+#define CLK_BUSTIMER2 89
|
||||
+#define CLK_BUSTIMER3 90
|
||||
+#define CLK_BUSTIMER4 91
|
||||
+#define CLK_BUSTIMER5 92
|
||||
+#define CLK_BUSTIMER6 93
|
||||
+#define CLK_BUSTIMER7 94
|
||||
+#define CLK_BUSTIMER8 95
|
||||
+#define CLK_BUSTIMER9 96
|
||||
+#define CLK_BUSTIMER10 97
|
||||
+#define CLK_BUSTIMER11 98
|
||||
+#define PCLK_WDT0 99
|
||||
+#define TCLK_WDT0 100
|
||||
+#define PCLK_CAN0 101
|
||||
+#define CLK_CAN0 102
|
||||
+#define PCLK_CAN1 103
|
||||
+#define CLK_CAN1 104
|
||||
+#define PCLK_CAN2 105
|
||||
+#define CLK_CAN2 106
|
||||
+#define ACLK_DECOM 107
|
||||
+#define PCLK_DECOM 108
|
||||
+#define DCLK_DECOM 109
|
||||
+#define ACLK_DMAC0 110
|
||||
+#define ACLK_DMAC1 111
|
||||
+#define ACLK_DMAC2 112
|
||||
+#define ACLK_BUS_ROOT 113
|
||||
+#define ACLK_GIC 114
|
||||
+#define PCLK_GPIO1 115
|
||||
+#define DBCLK_GPIO1 116
|
||||
+#define PCLK_GPIO2 117
|
||||
+#define DBCLK_GPIO2 118
|
||||
+#define PCLK_GPIO3 119
|
||||
+#define DBCLK_GPIO3 120
|
||||
+#define PCLK_GPIO4 121
|
||||
+#define DBCLK_GPIO4 122
|
||||
+#define PCLK_I2C1 123
|
||||
+#define PCLK_I2C2 124
|
||||
+#define PCLK_I2C3 125
|
||||
+#define PCLK_I2C4 126
|
||||
+#define PCLK_I2C5 127
|
||||
+#define PCLK_I2C6 128
|
||||
+#define PCLK_I2C7 129
|
||||
+#define PCLK_I2C8 130
|
||||
+#define CLK_I2C1 131
|
||||
+#define CLK_I2C2 132
|
||||
+#define CLK_I2C3 133
|
||||
+#define CLK_I2C4 134
|
||||
+#define CLK_I2C5 135
|
||||
+#define CLK_I2C6 136
|
||||
+#define CLK_I2C7 137
|
||||
+#define CLK_I2C8 138
|
||||
+#define PCLK_OTPC_NS 139
|
||||
+#define CLK_OTPC_NS 140
|
||||
+#define CLK_OTPC_ARB 141
|
||||
+#define CLK_OTPC_AUTO_RD_G 142
|
||||
+#define CLK_OTP_PHY_G 143
|
||||
+#define PCLK_SARADC 144
|
||||
+#define CLK_SARADC 145
|
||||
+#define PCLK_SPI0 146
|
||||
+#define PCLK_SPI1 147
|
||||
+#define PCLK_SPI2 148
|
||||
+#define PCLK_SPI3 149
|
||||
+#define PCLK_SPI4 150
|
||||
+#define CLK_SPI0 151
|
||||
+#define CLK_SPI1 152
|
||||
+#define CLK_SPI2 153
|
||||
+#define CLK_SPI3 154
|
||||
+#define CLK_SPI4 155
|
||||
+#define ACLK_SPINLOCK 156
|
||||
+#define PCLK_TSADC 157
|
||||
+#define CLK_TSADC 158
|
||||
+#define PCLK_UART1 159
|
||||
+#define PCLK_UART2 160
|
||||
+#define PCLK_UART3 161
|
||||
+#define PCLK_UART4 162
|
||||
+#define PCLK_UART5 163
|
||||
+#define PCLK_UART6 164
|
||||
+#define PCLK_UART7 165
|
||||
+#define PCLK_UART8 166
|
||||
+#define PCLK_UART9 167
|
||||
+#define CLK_UART1_SRC 168
|
||||
+#define CLK_UART1_FRAC 169
|
||||
+#define CLK_UART1 170
|
||||
+#define SCLK_UART1 171
|
||||
+#define CLK_UART2_SRC 172
|
||||
+#define CLK_UART2_FRAC 173
|
||||
+#define CLK_UART2 174
|
||||
+#define SCLK_UART2 175
|
||||
+#define CLK_UART3_SRC 176
|
||||
+#define CLK_UART3_FRAC 177
|
||||
+#define CLK_UART3 178
|
||||
+#define SCLK_UART3 179
|
||||
+#define CLK_UART4_SRC 180
|
||||
+#define CLK_UART4_FRAC 181
|
||||
+#define CLK_UART4 182
|
||||
+#define SCLK_UART4 183
|
||||
+#define CLK_UART5_SRC 184
|
||||
+#define CLK_UART5_FRAC 185
|
||||
+#define CLK_UART5 186
|
||||
+#define SCLK_UART5 187
|
||||
+#define CLK_UART6_SRC 188
|
||||
+#define CLK_UART6_FRAC 189
|
||||
+#define CLK_UART6 190
|
||||
+#define SCLK_UART6 191
|
||||
+#define CLK_UART7_SRC 192
|
||||
+#define CLK_UART7_FRAC 193
|
||||
+#define CLK_UART7 194
|
||||
+#define SCLK_UART7 195
|
||||
+#define CLK_UART8_SRC 196
|
||||
+#define CLK_UART8_FRAC 197
|
||||
+#define CLK_UART8 198
|
||||
+#define SCLK_UART8 199
|
||||
+#define CLK_UART9_SRC 200
|
||||
+#define CLK_UART9_FRAC 201
|
||||
+#define CLK_UART9 202
|
||||
+#define SCLK_UART9 203
|
||||
+#define ACLK_CENTER_ROOT 204
|
||||
+#define ACLK_CENTER_LOW_ROOT 205
|
||||
+#define HCLK_CENTER_ROOT 206
|
||||
+#define PCLK_CENTER_ROOT 207
|
||||
+#define ACLK_DMA2DDR 208
|
||||
+#define ACLK_DDR_SHAREMEM 209
|
||||
+#define ACLK_CENTER_S200_ROOT 210
|
||||
+#define ACLK_CENTER_S400_ROOT 211
|
||||
+#define FCLK_DDR_CM0_CORE 212
|
||||
+#define CLK_DDR_TIMER_ROOT 213
|
||||
+#define CLK_DDR_TIMER0 214
|
||||
+#define CLK_DDR_TIMER1 215
|
||||
+#define TCLK_WDT_DDR 216
|
||||
+#define CLK_DDR_CM0_RTC 217
|
||||
+#define PCLK_WDT 218
|
||||
+#define PCLK_TIMER 219
|
||||
+#define PCLK_DMA2DDR 220
|
||||
+#define PCLK_SHAREMEM 221
|
||||
+#define CLK_50M_SRC 222
|
||||
+#define CLK_100M_SRC 223
|
||||
+#define CLK_150M_SRC 224
|
||||
+#define CLK_200M_SRC 225
|
||||
+#define CLK_250M_SRC 226
|
||||
+#define CLK_300M_SRC 227
|
||||
+#define CLK_350M_SRC 228
|
||||
+#define CLK_400M_SRC 229
|
||||
+#define CLK_450M_SRC 230
|
||||
+#define CLK_500M_SRC 231
|
||||
+#define CLK_600M_SRC 232
|
||||
+#define CLK_650M_SRC 233
|
||||
+#define CLK_700M_SRC 234
|
||||
+#define CLK_800M_SRC 235
|
||||
+#define CLK_1000M_SRC 236
|
||||
+#define CLK_1200M_SRC 237
|
||||
+#define ACLK_TOP_M300_ROOT 238
|
||||
+#define ACLK_TOP_M500_ROOT 239
|
||||
+#define ACLK_TOP_M400_ROOT 240
|
||||
+#define ACLK_TOP_S200_ROOT 241
|
||||
+#define ACLK_TOP_S400_ROOT 242
|
||||
+#define CLK_MIPI_CAMARAOUT_M0 243
|
||||
+#define CLK_MIPI_CAMARAOUT_M1 244
|
||||
+#define CLK_MIPI_CAMARAOUT_M2 245
|
||||
+#define CLK_MIPI_CAMARAOUT_M3 246
|
||||
+#define CLK_MIPI_CAMARAOUT_M4 247
|
||||
+#define MCLK_GMAC0_OUT 248
|
||||
+#define REFCLKO25M_ETH0_OUT 249
|
||||
+#define REFCLKO25M_ETH1_OUT 250
|
||||
+#define CLK_CIFOUT_OUT 251
|
||||
+#define PCLK_MIPI_DCPHY0 252
|
||||
+#define PCLK_MIPI_DCPHY1 253
|
||||
+#define PCLK_CSIPHY0 254
|
||||
+#define PCLK_CSIPHY1 255
|
||||
+#define ACLK_TOP_ROOT 256
|
||||
+#define PCLK_TOP_ROOT 257
|
||||
+#define ACLK_LOW_TOP_ROOT 258
|
||||
+#define PCLK_CRU 259
|
||||
+#define PCLK_GPU_ROOT 260
|
||||
+#define CLK_GPU_SRC 261
|
||||
+#define CLK_GPU 262
|
||||
+#define CLK_GPU_COREGROUP 263
|
||||
+#define CLK_GPU_STACKS 264
|
||||
+#define PCLK_GPU_PVTM 265
|
||||
+#define CLK_GPU_PVTM 266
|
||||
+#define CLK_CORE_GPU_PVTM 267
|
||||
+#define PCLK_GPU_GRF 268
|
||||
+#define ACLK_ISP1_ROOT 269
|
||||
+#define HCLK_ISP1_ROOT 270
|
||||
+#define CLK_ISP1_CORE 271
|
||||
+#define CLK_ISP1_CORE_MARVIN 272
|
||||
+#define CLK_ISP1_CORE_VICAP 273
|
||||
+#define ACLK_ISP1 274
|
||||
+#define HCLK_ISP1 275
|
||||
+#define ACLK_NPU1 276
|
||||
+#define HCLK_NPU1 277
|
||||
+#define ACLK_NPU2 278
|
||||
+#define HCLK_NPU2 279
|
||||
+#define HCLK_NPU_CM0_ROOT 280
|
||||
+#define FCLK_NPU_CM0_CORE 281
|
||||
+#define CLK_NPU_CM0_RTC 282
|
||||
+#define PCLK_NPU_PVTM 283
|
||||
+#define PCLK_NPU_GRF 284
|
||||
+#define CLK_NPU_PVTM 285
|
||||
+#define CLK_CORE_NPU_PVTM 286
|
||||
+#define ACLK_NPU0 287
|
||||
+#define HCLK_NPU0 288
|
||||
+#define HCLK_NPU_ROOT 289
|
||||
+#define CLK_NPU_DSU0 290
|
||||
+#define PCLK_NPU_ROOT 291
|
||||
+#define PCLK_NPU_TIMER 292
|
||||
+#define CLK_NPUTIMER_ROOT 293
|
||||
+#define CLK_NPUTIMER0 294
|
||||
+#define CLK_NPUTIMER1 295
|
||||
+#define PCLK_NPU_WDT 296
|
||||
+#define TCLK_NPU_WDT 297
|
||||
+#define HCLK_EMMC 298
|
||||
+#define ACLK_EMMC 299
|
||||
+#define CCLK_EMMC 300
|
||||
+#define BCLK_EMMC 301
|
||||
+#define TMCLK_EMMC 302
|
||||
+#define SCLK_SFC 303
|
||||
+#define HCLK_SFC 304
|
||||
+#define HCLK_SFC_XIP 305
|
||||
+#define HCLK_NVM_ROOT 306
|
||||
+#define ACLK_NVM_ROOT 307
|
||||
+#define CLK_GMAC0_PTP_REF 308
|
||||
+#define CLK_GMAC1_PTP_REF 309
|
||||
+#define CLK_GMAC_125M 310
|
||||
+#define CLK_GMAC_50M 311
|
||||
+#define ACLK_PHP_GIC_ITS 312
|
||||
+#define ACLK_MMU_PCIE 313
|
||||
+#define ACLK_MMU_PHP 314
|
||||
+#define ACLK_PCIE_4L_DBI 315
|
||||
+#define ACLK_PCIE_2L_DBI 316
|
||||
+#define ACLK_PCIE_1L0_DBI 317
|
||||
+#define ACLK_PCIE_1L1_DBI 318
|
||||
+#define ACLK_PCIE_1L2_DBI 319
|
||||
+#define ACLK_PCIE_4L_MSTR 320
|
||||
+#define ACLK_PCIE_2L_MSTR 321
|
||||
+#define ACLK_PCIE_1L0_MSTR 322
|
||||
+#define ACLK_PCIE_1L1_MSTR 323
|
||||
+#define ACLK_PCIE_1L2_MSTR 324
|
||||
+#define ACLK_PCIE_4L_SLV 325
|
||||
+#define ACLK_PCIE_2L_SLV 326
|
||||
+#define ACLK_PCIE_1L0_SLV 327
|
||||
+#define ACLK_PCIE_1L1_SLV 328
|
||||
+#define ACLK_PCIE_1L2_SLV 329
|
||||
+#define PCLK_PCIE_4L 330
|
||||
+#define PCLK_PCIE_2L 331
|
||||
+#define PCLK_PCIE_1L0 332
|
||||
+#define PCLK_PCIE_1L1 333
|
||||
+#define PCLK_PCIE_1L2 334
|
||||
+#define CLK_PCIE_AUX0 335
|
||||
+#define CLK_PCIE_AUX1 336
|
||||
+#define CLK_PCIE_AUX2 337
|
||||
+#define CLK_PCIE_AUX3 338
|
||||
+#define CLK_PCIE_AUX4 339
|
||||
+#define CLK_PIPEPHY0_REF 340
|
||||
+#define CLK_PIPEPHY1_REF 341
|
||||
+#define CLK_PIPEPHY2_REF 342
|
||||
+#define PCLK_PHP_ROOT 343
|
||||
+#define PCLK_GMAC0 344
|
||||
+#define PCLK_GMAC1 345
|
||||
+#define ACLK_PCIE_ROOT 346
|
||||
+#define ACLK_PHP_ROOT 347
|
||||
+#define ACLK_PCIE_BRIDGE 348
|
||||
+#define ACLK_GMAC0 349
|
||||
+#define ACLK_GMAC1 350
|
||||
+#define CLK_PMALIVE0 351
|
||||
+#define CLK_PMALIVE1 352
|
||||
+#define CLK_PMALIVE2 353
|
||||
+#define ACLK_SATA0 354
|
||||
+#define ACLK_SATA1 355
|
||||
+#define ACLK_SATA2 356
|
||||
+#define CLK_RXOOB0 357
|
||||
+#define CLK_RXOOB1 358
|
||||
+#define CLK_RXOOB2 359
|
||||
+#define ACLK_USB3OTG2 360
|
||||
+#define SUSPEND_CLK_USB3OTG2 361
|
||||
+#define REF_CLK_USB3OTG2 362
|
||||
+#define CLK_UTMI_OTG2 363
|
||||
+#define CLK_PIPEPHY0_PIPE_G 364
|
||||
+#define CLK_PIPEPHY1_PIPE_G 365
|
||||
+#define CLK_PIPEPHY2_PIPE_G 366
|
||||
+#define CLK_PIPEPHY0_PIPE_ASIC_G 367
|
||||
+#define CLK_PIPEPHY1_PIPE_ASIC_G 368
|
||||
+#define CLK_PIPEPHY2_PIPE_ASIC_G 369
|
||||
+#define CLK_PIPEPHY2_PIPE_U3_G 370
|
||||
+#define CLK_PCIE1L2_PIPE 371
|
||||
+#define CLK_PCIE4L_PIPE 372
|
||||
+#define CLK_PCIE2L_PIPE 373
|
||||
+#define PCLK_PCIE_COMBO_PIPE_PHY0 374
|
||||
+#define PCLK_PCIE_COMBO_PIPE_PHY1 375
|
||||
+#define PCLK_PCIE_COMBO_PIPE_PHY2 376
|
||||
+#define PCLK_PCIE_COMBO_PIPE_PHY 377
|
||||
+#define HCLK_RGA3_1 378
|
||||
+#define ACLK_RGA3_1 379
|
||||
+#define CLK_RGA3_1_CORE 380
|
||||
+#define ACLK_RGA3_ROOT 381
|
||||
+#define HCLK_RGA3_ROOT 382
|
||||
+#define ACLK_RKVDEC_CCU 383
|
||||
+#define HCLK_RKVDEC0 384
|
||||
+#define ACLK_RKVDEC0 385
|
||||
+#define CLK_RKVDEC0_CA 386
|
||||
+#define CLK_RKVDEC0_HEVC_CA 387
|
||||
+#define CLK_RKVDEC0_CORE 388
|
||||
+#define HCLK_RKVDEC1 389
|
||||
+#define ACLK_RKVDEC1 390
|
||||
+#define CLK_RKVDEC1_CA 391
|
||||
+#define CLK_RKVDEC1_HEVC_CA 392
|
||||
+#define CLK_RKVDEC1_CORE 393
|
||||
+#define HCLK_SDIO 394
|
||||
+#define CCLK_SRC_SDIO 395
|
||||
+#define ACLK_USB_ROOT 396
|
||||
+#define HCLK_USB_ROOT 397
|
||||
+#define HCLK_HOST0 398
|
||||
+#define HCLK_HOST_ARB0 399
|
||||
+#define HCLK_HOST1 400
|
||||
+#define HCLK_HOST_ARB1 401
|
||||
+#define ACLK_USB3OTG0 402
|
||||
+#define SUSPEND_CLK_USB3OTG0 403
|
||||
+#define REF_CLK_USB3OTG0 404
|
||||
+#define ACLK_USB3OTG1 405
|
||||
+#define SUSPEND_CLK_USB3OTG1 406
|
||||
+#define REF_CLK_USB3OTG1 407
|
||||
+#define UTMI_OHCI_CLK48_HOST0 408
|
||||
+#define UTMI_OHCI_CLK48_HOST1 409
|
||||
+#define HCLK_IEP2P0 410
|
||||
+#define ACLK_IEP2P0 411
|
||||
+#define CLK_IEP2P0_CORE 412
|
||||
+#define ACLK_JPEG_ENCODER0 413
|
||||
+#define HCLK_JPEG_ENCODER0 414
|
||||
+#define ACLK_JPEG_ENCODER1 415
|
||||
+#define HCLK_JPEG_ENCODER1 416
|
||||
+#define ACLK_JPEG_ENCODER2 417
|
||||
+#define HCLK_JPEG_ENCODER2 418
|
||||
+#define ACLK_JPEG_ENCODER3 419
|
||||
+#define HCLK_JPEG_ENCODER3 420
|
||||
+#define ACLK_JPEG_DECODER 421
|
||||
+#define HCLK_JPEG_DECODER 422
|
||||
+#define HCLK_RGA2 423
|
||||
+#define ACLK_RGA2 424
|
||||
+#define CLK_RGA2_CORE 425
|
||||
+#define HCLK_RGA3_0 426
|
||||
+#define ACLK_RGA3_0 427
|
||||
+#define CLK_RGA3_0_CORE 428
|
||||
+#define ACLK_VDPU_ROOT 429
|
||||
+#define ACLK_VDPU_LOW_ROOT 430
|
||||
+#define HCLK_VDPU_ROOT 431
|
||||
+#define ACLK_JPEG_DECODER_ROOT 432
|
||||
+#define ACLK_VPU 433
|
||||
+#define HCLK_VPU 434
|
||||
+#define HCLK_RKVENC0_ROOT 435
|
||||
+#define ACLK_RKVENC0_ROOT 436
|
||||
+#define HCLK_RKVENC0 437
|
||||
+#define ACLK_RKVENC0 438
|
||||
+#define CLK_RKVENC0_CORE 439
|
||||
+#define HCLK_RKVENC1_ROOT 440
|
||||
+#define ACLK_RKVENC1_ROOT 441
|
||||
+#define HCLK_RKVENC1 442
|
||||
+#define ACLK_RKVENC1 443
|
||||
+#define CLK_RKVENC1_CORE 444
|
||||
+#define ICLK_CSIHOST01 445
|
||||
+#define ICLK_CSIHOST0 446
|
||||
+#define ICLK_CSIHOST1 447
|
||||
+#define PCLK_CSI_HOST_0 448
|
||||
+#define PCLK_CSI_HOST_1 449
|
||||
+#define PCLK_CSI_HOST_2 450
|
||||
+#define PCLK_CSI_HOST_3 451
|
||||
+#define PCLK_CSI_HOST_4 452
|
||||
+#define PCLK_CSI_HOST_5 453
|
||||
+#define ACLK_FISHEYE0 454
|
||||
+#define HCLK_FISHEYE0 455
|
||||
+#define CLK_FISHEYE0_CORE 456
|
||||
+#define ACLK_FISHEYE1 457
|
||||
+#define HCLK_FISHEYE1 458
|
||||
+#define CLK_FISHEYE1_CORE 459
|
||||
+#define CLK_ISP0_CORE 460
|
||||
+#define CLK_ISP0_CORE_MARVIN 461
|
||||
+#define CLK_ISP0_CORE_VICAP 462
|
||||
+#define ACLK_ISP0 463
|
||||
+#define HCLK_ISP0 464
|
||||
+#define ACLK_VI_ROOT 465
|
||||
+#define HCLK_VI_ROOT 466
|
||||
+#define PCLK_VI_ROOT 467
|
||||
+#define DCLK_VICAP 468
|
||||
+#define ACLK_VICAP 469
|
||||
+#define HCLK_VICAP 470
|
||||
+#define PCLK_DP0 471
|
||||
+#define PCLK_DP1 472
|
||||
+#define PCLK_S_DP0 473
|
||||
+#define PCLK_S_DP1 474
|
||||
+#define CLK_DP0 475
|
||||
+#define CLK_DP1 476
|
||||
+#define HCLK_HDCP_KEY0 477
|
||||
+#define ACLK_HDCP0 478
|
||||
+#define HCLK_HDCP0 479
|
||||
+#define PCLK_HDCP0 480
|
||||
+#define HCLK_I2S4_8CH 481
|
||||
+#define ACLK_TRNG0 482
|
||||
+#define PCLK_TRNG0 483
|
||||
+#define ACLK_VO0_ROOT 484
|
||||
+#define HCLK_VO0_ROOT 485
|
||||
+#define HCLK_VO0_S_ROOT 486
|
||||
+#define PCLK_VO0_ROOT 487
|
||||
+#define PCLK_VO0_S_ROOT 488
|
||||
+#define PCLK_VO0GRF 489
|
||||
+#define CLK_I2S4_8CH_TX_SRC 490
|
||||
+#define CLK_I2S4_8CH_TX_FRAC 491
|
||||
+#define MCLK_I2S4_8CH_TX 492
|
||||
+#define CLK_I2S4_8CH_TX 493
|
||||
+#define HCLK_I2S8_8CH 494
|
||||
+#define CLK_I2S8_8CH_TX_SRC 495
|
||||
+#define CLK_I2S8_8CH_TX_FRAC 496
|
||||
+#define MCLK_I2S8_8CH_TX 497
|
||||
+#define CLK_I2S8_8CH_TX 498
|
||||
+#define HCLK_SPDIF2_DP0 499
|
||||
+#define CLK_SPDIF2_DP0_SRC 500
|
||||
+#define CLK_SPDIF2_DP0_FRAC 501
|
||||
+#define MCLK_SPDIF2_DP0 502
|
||||
+#define CLK_SPDIF2_DP0 503
|
||||
+#define MCLK_SPDIF2 504
|
||||
+#define HCLK_SPDIF5_DP1 505
|
||||
+#define CLK_SPDIF5_DP1_SRC 506
|
||||
+#define CLK_SPDIF5_DP1_FRAC 507
|
||||
+#define MCLK_SPDIF5_DP1 508
|
||||
+#define CLK_SPDIF5_DP1 509
|
||||
+#define MCLK_SPDIF5 510
|
||||
+#define PCLK_EDP0 511
|
||||
+#define CLK_EDP0_24M 512
|
||||
+#define CLK_EDP0_200M 513
|
||||
+#define PCLK_EDP1 514
|
||||
+#define CLK_EDP1_24M 515
|
||||
+#define CLK_EDP1_200M 516
|
||||
+#define HCLK_HDCP_KEY1 517
|
||||
+#define ACLK_HDCP1 518
|
||||
+#define HCLK_HDCP1 519
|
||||
+#define PCLK_HDCP1 520
|
||||
+#define ACLK_HDMIRX 521
|
||||
+#define PCLK_HDMIRX 522
|
||||
+#define CLK_HDMIRX_REF 523
|
||||
+#define CLK_HDMIRX_AUD_SRC 524
|
||||
+#define CLK_HDMIRX_AUD_FRAC 525
|
||||
+#define CLK_HDMIRX_AUD 526
|
||||
+#define CLK_HDMIRX_AUD_P_MUX 527
|
||||
+#define PCLK_HDMITX0 528
|
||||
+#define CLK_HDMITX0_EARC 529
|
||||
+#define CLK_HDMITX0_REF 530
|
||||
+#define PCLK_HDMITX1 531
|
||||
+#define CLK_HDMITX1_EARC 532
|
||||
+#define CLK_HDMITX1_REF 533
|
||||
+#define CLK_HDMITRX_REFSRC 534
|
||||
+#define ACLK_TRNG1 535
|
||||
+#define PCLK_TRNG1 536
|
||||
+#define ACLK_HDCP1_ROOT 537
|
||||
+#define ACLK_HDMIRX_ROOT 538
|
||||
+#define HCLK_VO1_ROOT 539
|
||||
+#define HCLK_VO1_S_ROOT 540
|
||||
+#define PCLK_VO1_ROOT 541
|
||||
+#define PCLK_VO1_S_ROOT 542
|
||||
+#define PCLK_S_EDP0 543
|
||||
+#define PCLK_S_EDP1 544
|
||||
+#define PCLK_S_HDMIRX 545
|
||||
+#define HCLK_I2S10_8CH 546
|
||||
+#define CLK_I2S10_8CH_RX_SRC 547
|
||||
+#define CLK_I2S10_8CH_RX_FRAC 548
|
||||
+#define CLK_I2S10_8CH_RX 549
|
||||
+#define MCLK_I2S10_8CH_RX 550
|
||||
+#define HCLK_I2S7_8CH 551
|
||||
+#define CLK_I2S7_8CH_RX_SRC 552
|
||||
+#define CLK_I2S7_8CH_RX_FRAC 553
|
||||
+#define CLK_I2S7_8CH_RX 554
|
||||
+#define MCLK_I2S7_8CH_RX 555
|
||||
+#define HCLK_I2S9_8CH 556
|
||||
+#define CLK_I2S9_8CH_RX_SRC 557
|
||||
+#define CLK_I2S9_8CH_RX_FRAC 558
|
||||
+#define CLK_I2S9_8CH_RX 559
|
||||
+#define MCLK_I2S9_8CH_RX 560
|
||||
+#define CLK_I2S5_8CH_TX_SRC 561
|
||||
+#define CLK_I2S5_8CH_TX_FRAC 562
|
||||
+#define CLK_I2S5_8CH_TX 563
|
||||
+#define MCLK_I2S5_8CH_TX 564
|
||||
+#define HCLK_I2S5_8CH 565
|
||||
+#define CLK_I2S6_8CH_TX_SRC 566
|
||||
+#define CLK_I2S6_8CH_TX_FRAC 567
|
||||
+#define CLK_I2S6_8CH_TX 568
|
||||
+#define MCLK_I2S6_8CH_TX 569
|
||||
+#define CLK_I2S6_8CH_RX_SRC 570
|
||||
+#define CLK_I2S6_8CH_RX_FRAC 571
|
||||
+#define CLK_I2S6_8CH_RX 572
|
||||
+#define MCLK_I2S6_8CH_RX 573
|
||||
+#define I2S6_8CH_MCLKOUT 574
|
||||
+#define HCLK_I2S6_8CH 575
|
||||
+#define HCLK_SPDIF3 576
|
||||
+#define CLK_SPDIF3_SRC 577
|
||||
+#define CLK_SPDIF3_FRAC 578
|
||||
+#define CLK_SPDIF3 579
|
||||
+#define MCLK_SPDIF3 580
|
||||
+#define HCLK_SPDIF4 581
|
||||
+#define CLK_SPDIF4_SRC 582
|
||||
+#define CLK_SPDIF4_FRAC 583
|
||||
+#define CLK_SPDIF4 584
|
||||
+#define MCLK_SPDIF4 585
|
||||
+#define HCLK_SPDIFRX0 586
|
||||
+#define MCLK_SPDIFRX0 587
|
||||
+#define HCLK_SPDIFRX1 588
|
||||
+#define MCLK_SPDIFRX1 589
|
||||
+#define HCLK_SPDIFRX2 590
|
||||
+#define MCLK_SPDIFRX2 591
|
||||
+#define ACLK_VO1USB_TOP_ROOT 592
|
||||
+#define HCLK_VO1USB_TOP_ROOT 593
|
||||
+#define CLK_HDMIHDP0 594
|
||||
+#define CLK_HDMIHDP1 595
|
||||
+#define PCLK_HDPTX0 596
|
||||
+#define PCLK_HDPTX1 597
|
||||
+#define PCLK_USBDPPHY0 598
|
||||
+#define PCLK_USBDPPHY1 599
|
||||
+#define ACLK_VOP_ROOT 600
|
||||
+#define ACLK_VOP_LOW_ROOT 601
|
||||
+#define HCLK_VOP_ROOT 602
|
||||
+#define PCLK_VOP_ROOT 603
|
||||
+#define HCLK_VOP 604
|
||||
+#define ACLK_VOP 605
|
||||
+#define DCLK_VOP0_SRC 606
|
||||
+#define DCLK_VOP1_SRC 607
|
||||
+#define DCLK_VOP2_SRC 608
|
||||
+#define DCLK_VOP0 609
|
||||
+#define DCLK_VOP1 610
|
||||
+#define DCLK_VOP2 611
|
||||
+#define DCLK_VOP3 612
|
||||
+#define PCLK_DSIHOST0 613
|
||||
+#define PCLK_DSIHOST1 614
|
||||
+#define CLK_DSIHOST0 615
|
||||
+#define CLK_DSIHOST1 616
|
||||
+#define CLK_VOP_PMU 617
|
||||
+#define ACLK_VOP_DOBY 618
|
||||
+#define ACLK_VOP_SUB_SRC 619
|
||||
+#define CLK_USBDP_PHY0_IMMORTAL 620
|
||||
+#define CLK_USBDP_PHY1_IMMORTAL 621
|
||||
+#define CLK_PMU0 622
|
||||
+#define PCLK_PMU0 623
|
||||
+#define PCLK_PMU0IOC 624
|
||||
+#define PCLK_GPIO0 625
|
||||
+#define DBCLK_GPIO0 626
|
||||
+#define PCLK_I2C0 627
|
||||
+#define CLK_I2C0 628
|
||||
+#define HCLK_I2S1_8CH 629
|
||||
+#define CLK_I2S1_8CH_TX_SRC 630
|
||||
+#define CLK_I2S1_8CH_TX_FRAC 631
|
||||
+#define CLK_I2S1_8CH_TX 632
|
||||
+#define MCLK_I2S1_8CH_TX 633
|
||||
+#define CLK_I2S1_8CH_RX_SRC 634
|
||||
+#define CLK_I2S1_8CH_RX_FRAC 635
|
||||
+#define CLK_I2S1_8CH_RX 636
|
||||
+#define MCLK_I2S1_8CH_RX 637
|
||||
+#define I2S1_8CH_MCLKOUT 638
|
||||
+#define CLK_PMU1_50M_SRC 639
|
||||
+#define CLK_PMU1_100M_SRC 640
|
||||
+#define CLK_PMU1_200M_SRC 641
|
||||
+#define CLK_PMU1_300M_SRC 642
|
||||
+#define CLK_PMU1_400M_SRC 643
|
||||
+#define HCLK_PMU1_ROOT 644
|
||||
+#define PCLK_PMU1_ROOT 645
|
||||
+#define PCLK_PMU0_ROOT 646
|
||||
+#define HCLK_PMU_CM0_ROOT 647
|
||||
+#define PCLK_PMU1 648
|
||||
+#define CLK_DDR_FAIL_SAFE 649
|
||||
+#define CLK_PMU1 650
|
||||
+#define HCLK_PDM0 651
|
||||
+#define MCLK_PDM0 652
|
||||
+#define HCLK_VAD 653
|
||||
+#define FCLK_PMU_CM0_CORE 654
|
||||
+#define CLK_PMU_CM0_RTC 655
|
||||
+#define PCLK_PMU1_IOC 656
|
||||
+#define PCLK_PMU1PWM 657
|
||||
+#define CLK_PMU1PWM 658
|
||||
+#define CLK_PMU1PWM_CAPTURE 659
|
||||
+#define PCLK_PMU1TIMER 660
|
||||
+#define CLK_PMU1TIMER_ROOT 661
|
||||
+#define CLK_PMU1TIMER0 662
|
||||
+#define CLK_PMU1TIMER1 663
|
||||
+#define CLK_UART0_SRC 664
|
||||
+#define CLK_UART0_FRAC 665
|
||||
+#define CLK_UART0 666
|
||||
+#define SCLK_UART0 667
|
||||
+#define PCLK_UART0 668
|
||||
+#define PCLK_PMU1WDT 669
|
||||
+#define TCLK_PMU1WDT 670
|
||||
+#define CLK_CR_PARA 671
|
||||
+#define CLK_USB2PHY_HDPTXRXPHY_REF 672
|
||||
+#define CLK_USBDPPHY_MIPIDCPPHY_REF 673
|
||||
+#define CLK_REF_PIPE_PHY0_OSC_SRC 674
|
||||
+#define CLK_REF_PIPE_PHY1_OSC_SRC 675
|
||||
+#define CLK_REF_PIPE_PHY2_OSC_SRC 676
|
||||
+#define CLK_REF_PIPE_PHY0_PLL_SRC 677
|
||||
+#define CLK_REF_PIPE_PHY1_PLL_SRC 678
|
||||
+#define CLK_REF_PIPE_PHY2_PLL_SRC 679
|
||||
+#define CLK_REF_PIPE_PHY0 680
|
||||
+#define CLK_REF_PIPE_PHY1 681
|
||||
+#define CLK_REF_PIPE_PHY2 682
|
||||
+#define SCLK_SDIO_DRV 683
|
||||
+#define SCLK_SDIO_SAMPLE 684
|
||||
+#define SCLK_SDMMC_DRV 685
|
||||
+#define SCLK_SDMMC_SAMPLE 686
|
||||
+#define CLK_PCIE1L0_PIPE 687
|
||||
+#define CLK_PCIE1L1_PIPE 688
|
||||
+#define CLK_BIGCORE0_PVTM 689
|
||||
+#define CLK_CORE_BIGCORE0_PVTM 690
|
||||
+#define CLK_BIGCORE1_PVTM 691
|
||||
+#define CLK_CORE_BIGCORE1_PVTM 692
|
||||
+#define CLK_LITCORE_PVTM 693
|
||||
+#define CLK_CORE_LITCORE_PVTM 694
|
||||
+#define CLK_AUX16M_0 695
|
||||
+#define CLK_AUX16M_1 696
|
||||
+#define CLK_PHY0_REF_ALT_P 697
|
||||
+#define CLK_PHY0_REF_ALT_M 698
|
||||
+#define CLK_PHY1_REF_ALT_P 699
|
||||
+#define CLK_PHY1_REF_ALT_M 700
|
||||
+#define ACLK_ISP1_PRE 701
|
||||
+#define HCLK_ISP1_PRE 702
|
||||
+#define HCLK_NVM 703
|
||||
+#define ACLK_USB 704
|
||||
+#define HCLK_USB 705
|
||||
+#define ACLK_JPEG_DECODER_PRE 706
|
||||
+#define ACLK_VDPU_LOW_PRE 707
|
||||
+#define ACLK_RKVENC1_PRE 708
|
||||
+#define HCLK_RKVENC1_PRE 709
|
||||
+#define HCLK_RKVDEC0_PRE 710
|
||||
+#define ACLK_RKVDEC0_PRE 711
|
||||
+#define HCLK_RKVDEC1_PRE 712
|
||||
+#define ACLK_RKVDEC1_PRE 713
|
||||
+#define ACLK_HDCP0_PRE 714
|
||||
+#define HCLK_VO0 715
|
||||
+#define ACLK_HDCP1_PRE 716
|
||||
+#define HCLK_VO1 717
|
||||
+#define ACLK_AV1_PRE 718
|
||||
+#define PCLK_AV1_PRE 719
|
||||
+#define HCLK_SDIO_PRE 720
|
||||
+
|
||||
+#define CLK_NR_CLKS (HCLK_SDIO_PRE + 1)
|
||||
+
|
||||
+/* scmi-clocks indices */
|
||||
+
|
||||
+#define SCMI_CLK_CPUL 0
|
||||
+#define SCMI_CLK_DSU 1
|
||||
+#define SCMI_CLK_CPUB01 2
|
||||
+#define SCMI_CLK_CPUB23 3
|
||||
+#define SCMI_CLK_DDR 4
|
||||
+#define SCMI_CLK_GPU 5
|
||||
+#define SCMI_CLK_NPU 6
|
||||
+#define SCMI_CLK_SBUS 7
|
||||
+#define SCMI_PCLK_SBUS 8
|
||||
+#define SCMI_CCLK_SD 9
|
||||
+#define SCMI_DCLK_SD 10
|
||||
+#define SCMI_ACLK_SECURE_NS 11
|
||||
+#define SCMI_HCLK_SECURE_NS 12
|
||||
+#define SCMI_TCLK_WDT 13
|
||||
+#define SCMI_KEYLADDER_CORE 14
|
||||
+#define SCMI_KEYLADDER_RNG 15
|
||||
+#define SCMI_ACLK_SECURE_S 16
|
||||
+#define SCMI_HCLK_SECURE_S 17
|
||||
+#define SCMI_PCLK_SECURE_S 18
|
||||
+#define SCMI_CRYPTO_RNG 19
|
||||
+#define SCMI_CRYPTO_CORE 20
|
||||
+#define SCMI_CRYPTO_PKA 21
|
||||
+#define SCMI_SPLL 22
|
||||
+#define SCMI_HCLK_SD 23
|
||||
+
|
||||
+#endif
|
||||
@ -1,781 +0,0 @@
|
||||
From 0a8eb7dae617a9537b9a64a6b14e63415c279eb5 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 18 Oct 2022 17:14:00 +0200
|
||||
Subject: [PATCH] dt-bindings: reset: add rk3588 reset definitions
|
||||
|
||||
Add reset ID defines for rk3588.
|
||||
|
||||
Compared to the downstream bindings and previous rockchip
|
||||
generations this uses continous gapless reset IDs starting
|
||||
at 0 instead of register offsets as IDs. Thus all numbers
|
||||
are different between upstream and downstream, but I kept
|
||||
the names exactly the same.
|
||||
|
||||
Co-Developed-by: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Acked-by: Rob Herring <robh@kernel.org>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221018151407.63395-3-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
.../dt-bindings/reset/rockchip,rk3588-cru.h | 754 ++++++++++++++++++
|
||||
1 file changed, 754 insertions(+)
|
||||
create mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h
|
||||
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
|
||||
@@ -0,0 +1,754 @@
|
||||
+/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
|
||||
+/*
|
||||
+ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
|
||||
+ * Copyright (c) 2022 Collabora Ltd.
|
||||
+ *
|
||||
+ * Author: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
+ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
+ */
|
||||
+
|
||||
+#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
|
||||
+#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
|
||||
+
|
||||
+#define SRST_A_TOP_BIU 0
|
||||
+#define SRST_P_TOP_BIU 1
|
||||
+#define SRST_P_CSIPHY0 2
|
||||
+#define SRST_CSIPHY0 3
|
||||
+#define SRST_P_CSIPHY1 4
|
||||
+#define SRST_CSIPHY1 5
|
||||
+#define SRST_A_TOP_M500_BIU 6
|
||||
+
|
||||
+#define SRST_A_TOP_M400_BIU 7
|
||||
+#define SRST_A_TOP_S200_BIU 8
|
||||
+#define SRST_A_TOP_S400_BIU 9
|
||||
+#define SRST_A_TOP_M300_BIU 10
|
||||
+#define SRST_USBDP_COMBO_PHY0_INIT 11
|
||||
+#define SRST_USBDP_COMBO_PHY0_CMN 12
|
||||
+#define SRST_USBDP_COMBO_PHY0_LANE 13
|
||||
+#define SRST_USBDP_COMBO_PHY0_PCS 14
|
||||
+#define SRST_USBDP_COMBO_PHY1_INIT 15
|
||||
+
|
||||
+#define SRST_USBDP_COMBO_PHY1_CMN 16
|
||||
+#define SRST_USBDP_COMBO_PHY1_LANE 17
|
||||
+#define SRST_USBDP_COMBO_PHY1_PCS 18
|
||||
+#define SRST_DCPHY0 19
|
||||
+#define SRST_P_MIPI_DCPHY0 20
|
||||
+#define SRST_P_MIPI_DCPHY0_GRF 21
|
||||
+
|
||||
+#define SRST_DCPHY1 22
|
||||
+#define SRST_P_MIPI_DCPHY1 23
|
||||
+#define SRST_P_MIPI_DCPHY1_GRF 24
|
||||
+#define SRST_P_APB2ASB_SLV_CDPHY 25
|
||||
+#define SRST_P_APB2ASB_SLV_CSIPHY 26
|
||||
+#define SRST_P_APB2ASB_SLV_VCCIO3_5 27
|
||||
+#define SRST_P_APB2ASB_SLV_VCCIO6 28
|
||||
+#define SRST_P_APB2ASB_SLV_EMMCIO 29
|
||||
+#define SRST_P_APB2ASB_SLV_IOC_TOP 30
|
||||
+#define SRST_P_APB2ASB_SLV_IOC_RIGHT 31
|
||||
+
|
||||
+#define SRST_P_CRU 32
|
||||
+#define SRST_A_CHANNEL_SECURE2VO1USB 33
|
||||
+#define SRST_A_CHANNEL_SECURE2CENTER 34
|
||||
+#define SRST_H_CHANNEL_SECURE2VO1USB 35
|
||||
+#define SRST_H_CHANNEL_SECURE2CENTER 36
|
||||
+
|
||||
+#define SRST_P_CHANNEL_SECURE2VO1USB 37
|
||||
+#define SRST_P_CHANNEL_SECURE2CENTER 38
|
||||
+
|
||||
+#define SRST_H_AUDIO_BIU 39
|
||||
+#define SRST_P_AUDIO_BIU 40
|
||||
+#define SRST_H_I2S0_8CH 41
|
||||
+#define SRST_M_I2S0_8CH_TX 42
|
||||
+#define SRST_M_I2S0_8CH_RX 43
|
||||
+#define SRST_P_ACDCDIG 44
|
||||
+#define SRST_H_I2S2_2CH 45
|
||||
+#define SRST_H_I2S3_2CH 46
|
||||
+
|
||||
+#define SRST_M_I2S2_2CH 47
|
||||
+#define SRST_M_I2S3_2CH 48
|
||||
+#define SRST_DAC_ACDCDIG 49
|
||||
+#define SRST_H_SPDIF0 50
|
||||
+
|
||||
+#define SRST_M_SPDIF0 51
|
||||
+#define SRST_H_SPDIF1 52
|
||||
+#define SRST_M_SPDIF1 53
|
||||
+#define SRST_H_PDM1 54
|
||||
+#define SRST_PDM1 55
|
||||
+
|
||||
+#define SRST_A_BUS_BIU 56
|
||||
+#define SRST_P_BUS_BIU 57
|
||||
+#define SRST_A_GIC 58
|
||||
+#define SRST_A_GIC_DBG 59
|
||||
+#define SRST_A_DMAC0 60
|
||||
+#define SRST_A_DMAC1 61
|
||||
+#define SRST_A_DMAC2 62
|
||||
+#define SRST_P_I2C1 63
|
||||
+#define SRST_P_I2C2 64
|
||||
+#define SRST_P_I2C3 65
|
||||
+#define SRST_P_I2C4 66
|
||||
+#define SRST_P_I2C5 67
|
||||
+#define SRST_P_I2C6 68
|
||||
+#define SRST_P_I2C7 69
|
||||
+#define SRST_P_I2C8 70
|
||||
+
|
||||
+#define SRST_I2C1 71
|
||||
+#define SRST_I2C2 72
|
||||
+#define SRST_I2C3 73
|
||||
+#define SRST_I2C4 74
|
||||
+#define SRST_I2C5 75
|
||||
+#define SRST_I2C6 76
|
||||
+#define SRST_I2C7 77
|
||||
+#define SRST_I2C8 78
|
||||
+#define SRST_P_CAN0 79
|
||||
+#define SRST_CAN0 80
|
||||
+#define SRST_P_CAN1 81
|
||||
+#define SRST_CAN1 82
|
||||
+#define SRST_P_CAN2 83
|
||||
+#define SRST_CAN2 84
|
||||
+#define SRST_P_SARADC 85
|
||||
+
|
||||
+#define SRST_P_TSADC 86
|
||||
+#define SRST_TSADC 87
|
||||
+#define SRST_P_UART1 88
|
||||
+#define SRST_P_UART2 89
|
||||
+#define SRST_P_UART3 90
|
||||
+#define SRST_P_UART4 91
|
||||
+#define SRST_P_UART5 92
|
||||
+#define SRST_P_UART6 93
|
||||
+#define SRST_P_UART7 94
|
||||
+#define SRST_P_UART8 95
|
||||
+#define SRST_P_UART9 96
|
||||
+#define SRST_S_UART1 97
|
||||
+
|
||||
+#define SRST_S_UART2 98
|
||||
+#define SRST_S_UART3 99
|
||||
+#define SRST_S_UART4 100
|
||||
+#define SRST_S_UART5 101
|
||||
+#define SRST_S_UART6 102
|
||||
+#define SRST_S_UART7 103
|
||||
+
|
||||
+#define SRST_S_UART8 104
|
||||
+#define SRST_S_UART9 105
|
||||
+#define SRST_P_SPI0 106
|
||||
+#define SRST_P_SPI1 107
|
||||
+#define SRST_P_SPI2 108
|
||||
+#define SRST_P_SPI3 109
|
||||
+#define SRST_P_SPI4 110
|
||||
+#define SRST_SPI0 111
|
||||
+#define SRST_SPI1 112
|
||||
+#define SRST_SPI2 113
|
||||
+#define SRST_SPI3 114
|
||||
+#define SRST_SPI4 115
|
||||
+
|
||||
+#define SRST_P_WDT0 116
|
||||
+#define SRST_T_WDT0 117
|
||||
+#define SRST_P_SYS_GRF 118
|
||||
+#define SRST_P_PWM1 119
|
||||
+#define SRST_PWM1 120
|
||||
+#define SRST_P_PWM2 121
|
||||
+#define SRST_PWM2 122
|
||||
+#define SRST_P_PWM3 123
|
||||
+#define SRST_PWM3 124
|
||||
+#define SRST_P_BUSTIMER0 125
|
||||
+#define SRST_P_BUSTIMER1 126
|
||||
+#define SRST_BUSTIMER0 127
|
||||
+
|
||||
+#define SRST_BUSTIMER1 128
|
||||
+#define SRST_BUSTIMER2 129
|
||||
+#define SRST_BUSTIMER3 130
|
||||
+#define SRST_BUSTIMER4 131
|
||||
+#define SRST_BUSTIMER5 132
|
||||
+#define SRST_BUSTIMER6 133
|
||||
+#define SRST_BUSTIMER7 134
|
||||
+#define SRST_BUSTIMER8 135
|
||||
+#define SRST_BUSTIMER9 136
|
||||
+#define SRST_BUSTIMER10 137
|
||||
+#define SRST_BUSTIMER11 138
|
||||
+#define SRST_P_MAILBOX0 139
|
||||
+#define SRST_P_MAILBOX1 140
|
||||
+#define SRST_P_MAILBOX2 141
|
||||
+#define SRST_P_GPIO1 142
|
||||
+#define SRST_GPIO1 143
|
||||
+
|
||||
+#define SRST_P_GPIO2 144
|
||||
+#define SRST_GPIO2 145
|
||||
+#define SRST_P_GPIO3 146
|
||||
+#define SRST_GPIO3 147
|
||||
+#define SRST_P_GPIO4 148
|
||||
+#define SRST_GPIO4 149
|
||||
+#define SRST_A_DECOM 150
|
||||
+#define SRST_P_DECOM 151
|
||||
+#define SRST_D_DECOM 152
|
||||
+#define SRST_P_TOP 153
|
||||
+#define SRST_A_GICADB_GIC2CORE_BUS 154
|
||||
+#define SRST_P_DFT2APB 155
|
||||
+#define SRST_P_APB2ASB_MST_TOP 156
|
||||
+#define SRST_P_APB2ASB_MST_CDPHY 157
|
||||
+#define SRST_P_APB2ASB_MST_BOT_RIGHT 158
|
||||
+
|
||||
+#define SRST_P_APB2ASB_MST_IOC_TOP 159
|
||||
+#define SRST_P_APB2ASB_MST_IOC_RIGHT 160
|
||||
+#define SRST_P_APB2ASB_MST_CSIPHY 161
|
||||
+#define SRST_P_APB2ASB_MST_VCCIO3_5 162
|
||||
+#define SRST_P_APB2ASB_MST_VCCIO6 163
|
||||
+#define SRST_P_APB2ASB_MST_EMMCIO 164
|
||||
+#define SRST_A_SPINLOCK 165
|
||||
+#define SRST_P_OTPC_NS 166
|
||||
+#define SRST_OTPC_NS 167
|
||||
+#define SRST_OTPC_ARB 168
|
||||
+
|
||||
+#define SRST_P_BUSIOC 169
|
||||
+#define SRST_P_PMUCM0_INTMUX 170
|
||||
+#define SRST_P_DDRCM0_INTMUX 171
|
||||
+
|
||||
+#define SRST_P_DDR_DFICTL_CH0 172
|
||||
+#define SRST_P_DDR_MON_CH0 173
|
||||
+#define SRST_P_DDR_STANDBY_CH0 174
|
||||
+#define SRST_P_DDR_UPCTL_CH0 175
|
||||
+#define SRST_TM_DDR_MON_CH0 176
|
||||
+#define SRST_P_DDR_GRF_CH01 177
|
||||
+#define SRST_DFI_CH0 178
|
||||
+#define SRST_SBR_CH0 179
|
||||
+#define SRST_DDR_UPCTL_CH0 180
|
||||
+#define SRST_DDR_DFICTL_CH0 181
|
||||
+#define SRST_DDR_MON_CH0 182
|
||||
+#define SRST_DDR_STANDBY_CH0 183
|
||||
+#define SRST_A_DDR_UPCTL_CH0 184
|
||||
+#define SRST_P_DDR_DFICTL_CH1 185
|
||||
+#define SRST_P_DDR_MON_CH1 186
|
||||
+#define SRST_P_DDR_STANDBY_CH1 187
|
||||
+
|
||||
+#define SRST_P_DDR_UPCTL_CH1 188
|
||||
+#define SRST_TM_DDR_MON_CH1 189
|
||||
+#define SRST_DFI_CH1 190
|
||||
+#define SRST_SBR_CH1 191
|
||||
+#define SRST_DDR_UPCTL_CH1 192
|
||||
+#define SRST_DDR_DFICTL_CH1 193
|
||||
+#define SRST_DDR_MON_CH1 194
|
||||
+#define SRST_DDR_STANDBY_CH1 195
|
||||
+#define SRST_A_DDR_UPCTL_CH1 196
|
||||
+#define SRST_A_DDR01_MSCH0 197
|
||||
+#define SRST_A_DDR01_RS_MSCH0 198
|
||||
+#define SRST_A_DDR01_FRS_MSCH0 199
|
||||
+
|
||||
+#define SRST_A_DDR01_SCRAMBLE0 200
|
||||
+#define SRST_A_DDR01_FRS_SCRAMBLE0 201
|
||||
+#define SRST_A_DDR01_MSCH1 202
|
||||
+#define SRST_A_DDR01_RS_MSCH1 203
|
||||
+#define SRST_A_DDR01_FRS_MSCH1 204
|
||||
+#define SRST_A_DDR01_SCRAMBLE1 205
|
||||
+#define SRST_A_DDR01_FRS_SCRAMBLE1 206
|
||||
+#define SRST_P_DDR01_MSCH0 207
|
||||
+#define SRST_P_DDR01_MSCH1 208
|
||||
+
|
||||
+#define SRST_P_DDR_DFICTL_CH2 209
|
||||
+#define SRST_P_DDR_MON_CH2 210
|
||||
+#define SRST_P_DDR_STANDBY_CH2 211
|
||||
+#define SRST_P_DDR_UPCTL_CH2 212
|
||||
+#define SRST_TM_DDR_MON_CH2 213
|
||||
+#define SRST_P_DDR_GRF_CH23 214
|
||||
+#define SRST_DFI_CH2 215
|
||||
+#define SRST_SBR_CH2 216
|
||||
+#define SRST_DDR_UPCTL_CH2 217
|
||||
+#define SRST_DDR_DFICTL_CH2 218
|
||||
+#define SRST_DDR_MON_CH2 219
|
||||
+#define SRST_DDR_STANDBY_CH2 220
|
||||
+#define SRST_A_DDR_UPCTL_CH2 221
|
||||
+#define SRST_P_DDR_DFICTL_CH3 222
|
||||
+#define SRST_P_DDR_MON_CH3 223
|
||||
+#define SRST_P_DDR_STANDBY_CH3 224
|
||||
+
|
||||
+#define SRST_P_DDR_UPCTL_CH3 225
|
||||
+#define SRST_TM_DDR_MON_CH3 226
|
||||
+#define SRST_DFI_CH3 227
|
||||
+#define SRST_SBR_CH3 228
|
||||
+#define SRST_DDR_UPCTL_CH3 229
|
||||
+#define SRST_DDR_DFICTL_CH3 230
|
||||
+#define SRST_DDR_MON_CH3 231
|
||||
+#define SRST_DDR_STANDBY_CH3 232
|
||||
+#define SRST_A_DDR_UPCTL_CH3 233
|
||||
+#define SRST_A_DDR23_MSCH2 234
|
||||
+#define SRST_A_DDR23_RS_MSCH2 235
|
||||
+#define SRST_A_DDR23_FRS_MSCH2 236
|
||||
+
|
||||
+#define SRST_A_DDR23_SCRAMBLE2 237
|
||||
+#define SRST_A_DDR23_FRS_SCRAMBLE2 238
|
||||
+#define SRST_A_DDR23_MSCH3 239
|
||||
+#define SRST_A_DDR23_RS_MSCH3 240
|
||||
+#define SRST_A_DDR23_FRS_MSCH3 241
|
||||
+#define SRST_A_DDR23_SCRAMBLE3 242
|
||||
+#define SRST_A_DDR23_FRS_SCRAMBLE3 243
|
||||
+#define SRST_P_DDR23_MSCH2 244
|
||||
+#define SRST_P_DDR23_MSCH3 245
|
||||
+
|
||||
+#define SRST_ISP1 246
|
||||
+#define SRST_ISP1_VICAP 247
|
||||
+#define SRST_A_ISP1_BIU 248
|
||||
+#define SRST_H_ISP1_BIU 249
|
||||
+
|
||||
+#define SRST_A_RKNN1 250
|
||||
+#define SRST_A_RKNN1_BIU 251
|
||||
+#define SRST_H_RKNN1 252
|
||||
+#define SRST_H_RKNN1_BIU 253
|
||||
+
|
||||
+#define SRST_A_RKNN2 254
|
||||
+#define SRST_A_RKNN2_BIU 255
|
||||
+#define SRST_H_RKNN2 256
|
||||
+#define SRST_H_RKNN2_BIU 257
|
||||
+
|
||||
+#define SRST_A_RKNN_DSU0 258
|
||||
+#define SRST_P_NPUTOP_BIU 259
|
||||
+#define SRST_P_NPU_TIMER 260
|
||||
+#define SRST_NPUTIMER0 261
|
||||
+#define SRST_NPUTIMER1 262
|
||||
+#define SRST_P_NPU_WDT 263
|
||||
+#define SRST_T_NPU_WDT 264
|
||||
+#define SRST_P_NPU_PVTM 265
|
||||
+#define SRST_P_NPU_GRF 266
|
||||
+#define SRST_NPU_PVTM 267
|
||||
+
|
||||
+#define SRST_NPU_PVTPLL 268
|
||||
+#define SRST_H_NPU_CM0_BIU 269
|
||||
+#define SRST_F_NPU_CM0_CORE 270
|
||||
+#define SRST_T_NPU_CM0_JTAG 271
|
||||
+#define SRST_A_RKNN0 272
|
||||
+#define SRST_A_RKNN0_BIU 273
|
||||
+#define SRST_H_RKNN0 274
|
||||
+#define SRST_H_RKNN0_BIU 275
|
||||
+
|
||||
+#define SRST_H_NVM_BIU 276
|
||||
+#define SRST_A_NVM_BIU 277
|
||||
+#define SRST_H_EMMC 278
|
||||
+#define SRST_A_EMMC 279
|
||||
+#define SRST_C_EMMC 280
|
||||
+#define SRST_B_EMMC 281
|
||||
+#define SRST_T_EMMC 282
|
||||
+#define SRST_S_SFC 283
|
||||
+#define SRST_H_SFC 284
|
||||
+#define SRST_H_SFC_XIP 285
|
||||
+
|
||||
+#define SRST_P_GRF 286
|
||||
+#define SRST_P_DEC_BIU 287
|
||||
+#define SRST_P_PHP_BIU 288
|
||||
+#define SRST_A_PCIE_GRIDGE 289
|
||||
+#define SRST_A_PHP_BIU 290
|
||||
+#define SRST_A_GMAC0 291
|
||||
+#define SRST_A_GMAC1 292
|
||||
+#define SRST_A_PCIE_BIU 293
|
||||
+#define SRST_PCIE0_POWER_UP 294
|
||||
+#define SRST_PCIE1_POWER_UP 295
|
||||
+#define SRST_PCIE2_POWER_UP 296
|
||||
+
|
||||
+#define SRST_PCIE3_POWER_UP 297
|
||||
+#define SRST_PCIE4_POWER_UP 298
|
||||
+#define SRST_P_PCIE0 299
|
||||
+#define SRST_P_PCIE1 300
|
||||
+#define SRST_P_PCIE2 301
|
||||
+#define SRST_P_PCIE3 302
|
||||
+
|
||||
+#define SRST_P_PCIE4 303
|
||||
+#define SRST_A_PHP_GIC_ITS 304
|
||||
+#define SRST_A_MMU_PCIE 305
|
||||
+#define SRST_A_MMU_PHP 306
|
||||
+#define SRST_A_MMU_BIU 307
|
||||
+
|
||||
+#define SRST_A_USB3OTG2 308
|
||||
+
|
||||
+#define SRST_PMALIVE0 309
|
||||
+#define SRST_PMALIVE1 310
|
||||
+#define SRST_PMALIVE2 311
|
||||
+#define SRST_A_SATA0 312
|
||||
+#define SRST_A_SATA1 313
|
||||
+#define SRST_A_SATA2 314
|
||||
+#define SRST_RXOOB0 315
|
||||
+#define SRST_RXOOB1 316
|
||||
+#define SRST_RXOOB2 317
|
||||
+#define SRST_ASIC0 318
|
||||
+#define SRST_ASIC1 319
|
||||
+#define SRST_ASIC2 320
|
||||
+
|
||||
+#define SRST_A_RKVDEC_CCU 321
|
||||
+#define SRST_H_RKVDEC0 322
|
||||
+#define SRST_A_RKVDEC0 323
|
||||
+#define SRST_H_RKVDEC0_BIU 324
|
||||
+#define SRST_A_RKVDEC0_BIU 325
|
||||
+#define SRST_RKVDEC0_CA 326
|
||||
+#define SRST_RKVDEC0_HEVC_CA 327
|
||||
+#define SRST_RKVDEC0_CORE 328
|
||||
+
|
||||
+#define SRST_H_RKVDEC1 329
|
||||
+#define SRST_A_RKVDEC1 330
|
||||
+#define SRST_H_RKVDEC1_BIU 331
|
||||
+#define SRST_A_RKVDEC1_BIU 332
|
||||
+#define SRST_RKVDEC1_CA 333
|
||||
+#define SRST_RKVDEC1_HEVC_CA 334
|
||||
+#define SRST_RKVDEC1_CORE 335
|
||||
+
|
||||
+#define SRST_A_USB_BIU 336
|
||||
+#define SRST_H_USB_BIU 337
|
||||
+#define SRST_A_USB3OTG0 338
|
||||
+#define SRST_A_USB3OTG1 339
|
||||
+#define SRST_H_HOST0 340
|
||||
+#define SRST_H_HOST_ARB0 341
|
||||
+#define SRST_H_HOST1 342
|
||||
+#define SRST_H_HOST_ARB1 343
|
||||
+#define SRST_A_USB_GRF 344
|
||||
+#define SRST_C_USB2P0_HOST0 345
|
||||
+
|
||||
+#define SRST_C_USB2P0_HOST1 346
|
||||
+#define SRST_HOST_UTMI0 347
|
||||
+#define SRST_HOST_UTMI1 348
|
||||
+
|
||||
+#define SRST_A_VDPU_BIU 349
|
||||
+#define SRST_A_VDPU_LOW_BIU 350
|
||||
+#define SRST_H_VDPU_BIU 351
|
||||
+#define SRST_A_JPEG_DECODER_BIU 352
|
||||
+#define SRST_A_VPU 353
|
||||
+#define SRST_H_VPU 354
|
||||
+#define SRST_A_JPEG_ENCODER0 355
|
||||
+#define SRST_H_JPEG_ENCODER0 356
|
||||
+#define SRST_A_JPEG_ENCODER1 357
|
||||
+#define SRST_H_JPEG_ENCODER1 358
|
||||
+#define SRST_A_JPEG_ENCODER2 359
|
||||
+#define SRST_H_JPEG_ENCODER2 360
|
||||
+
|
||||
+#define SRST_A_JPEG_ENCODER3 361
|
||||
+#define SRST_H_JPEG_ENCODER3 362
|
||||
+#define SRST_A_JPEG_DECODER 363
|
||||
+#define SRST_H_JPEG_DECODER 364
|
||||
+#define SRST_H_IEP2P0 365
|
||||
+#define SRST_A_IEP2P0 366
|
||||
+#define SRST_IEP2P0_CORE 367
|
||||
+#define SRST_H_RGA2 368
|
||||
+#define SRST_A_RGA2 369
|
||||
+#define SRST_RGA2_CORE 370
|
||||
+#define SRST_H_RGA3_0 371
|
||||
+#define SRST_A_RGA3_0 372
|
||||
+#define SRST_RGA3_0_CORE 373
|
||||
+
|
||||
+#define SRST_H_RKVENC0_BIU 374
|
||||
+#define SRST_A_RKVENC0_BIU 375
|
||||
+#define SRST_H_RKVENC0 376
|
||||
+#define SRST_A_RKVENC0 377
|
||||
+#define SRST_RKVENC0_CORE 378
|
||||
+
|
||||
+#define SRST_H_RKVENC1_BIU 379
|
||||
+#define SRST_A_RKVENC1_BIU 380
|
||||
+#define SRST_H_RKVENC1 381
|
||||
+#define SRST_A_RKVENC1 382
|
||||
+#define SRST_RKVENC1_CORE 383
|
||||
+
|
||||
+#define SRST_A_VI_BIU 384
|
||||
+#define SRST_H_VI_BIU 385
|
||||
+#define SRST_P_VI_BIU 386
|
||||
+#define SRST_D_VICAP 387
|
||||
+#define SRST_A_VICAP 388
|
||||
+#define SRST_H_VICAP 389
|
||||
+#define SRST_ISP0 390
|
||||
+#define SRST_ISP0_VICAP 391
|
||||
+
|
||||
+#define SRST_FISHEYE0 392
|
||||
+#define SRST_FISHEYE1 393
|
||||
+#define SRST_P_CSI_HOST_0 394
|
||||
+#define SRST_P_CSI_HOST_1 395
|
||||
+#define SRST_P_CSI_HOST_2 396
|
||||
+#define SRST_P_CSI_HOST_3 397
|
||||
+#define SRST_P_CSI_HOST_4 398
|
||||
+#define SRST_P_CSI_HOST_5 399
|
||||
+
|
||||
+#define SRST_CSIHOST0_VICAP 400
|
||||
+#define SRST_CSIHOST1_VICAP 401
|
||||
+#define SRST_CSIHOST2_VICAP 402
|
||||
+#define SRST_CSIHOST3_VICAP 403
|
||||
+#define SRST_CSIHOST4_VICAP 404
|
||||
+#define SRST_CSIHOST5_VICAP 405
|
||||
+#define SRST_CIFIN 406
|
||||
+
|
||||
+#define SRST_A_VOP_BIU 407
|
||||
+#define SRST_A_VOP_LOW_BIU 408
|
||||
+#define SRST_H_VOP_BIU 409
|
||||
+#define SRST_P_VOP_BIU 410
|
||||
+#define SRST_H_VOP 411
|
||||
+#define SRST_A_VOP 412
|
||||
+#define SRST_D_VOP0 413
|
||||
+#define SRST_D_VOP2HDMI_BRIDGE0 414
|
||||
+#define SRST_D_VOP2HDMI_BRIDGE1 415
|
||||
+
|
||||
+#define SRST_D_VOP1 416
|
||||
+#define SRST_D_VOP2 417
|
||||
+#define SRST_D_VOP3 418
|
||||
+#define SRST_P_VOPGRF 419
|
||||
+#define SRST_P_DSIHOST0 420
|
||||
+#define SRST_P_DSIHOST1 421
|
||||
+#define SRST_DSIHOST0 422
|
||||
+#define SRST_DSIHOST1 423
|
||||
+#define SRST_VOP_PMU 424
|
||||
+#define SRST_P_VOP_CHANNEL_BIU 425
|
||||
+
|
||||
+#define SRST_H_VO0_BIU 426
|
||||
+#define SRST_H_VO0_S_BIU 427
|
||||
+#define SRST_P_VO0_BIU 428
|
||||
+#define SRST_P_VO0_S_BIU 429
|
||||
+#define SRST_A_HDCP0_BIU 430
|
||||
+#define SRST_P_VO0GRF 431
|
||||
+#define SRST_H_HDCP_KEY0 432
|
||||
+#define SRST_A_HDCP0 433
|
||||
+#define SRST_H_HDCP0 434
|
||||
+#define SRST_HDCP0 435
|
||||
+
|
||||
+#define SRST_P_TRNG0 436
|
||||
+#define SRST_DP0 437
|
||||
+#define SRST_DP1 438
|
||||
+#define SRST_H_I2S4_8CH 439
|
||||
+#define SRST_M_I2S4_8CH_TX 440
|
||||
+#define SRST_H_I2S8_8CH 441
|
||||
+
|
||||
+#define SRST_M_I2S8_8CH_TX 442
|
||||
+#define SRST_H_SPDIF2_DP0 443
|
||||
+#define SRST_M_SPDIF2_DP0 444
|
||||
+#define SRST_H_SPDIF5_DP1 445
|
||||
+#define SRST_M_SPDIF5_DP1 446
|
||||
+
|
||||
+#define SRST_A_HDCP1_BIU 447
|
||||
+#define SRST_A_VO1_BIU 448
|
||||
+#define SRST_H_VOP1_BIU 449
|
||||
+#define SRST_H_VOP1_S_BIU 450
|
||||
+#define SRST_P_VOP1_BIU 451
|
||||
+#define SRST_P_VO1GRF 452
|
||||
+#define SRST_P_VO1_S_BIU 453
|
||||
+
|
||||
+#define SRST_H_I2S7_8CH 454
|
||||
+#define SRST_M_I2S7_8CH_RX 455
|
||||
+#define SRST_H_HDCP_KEY1 456
|
||||
+#define SRST_A_HDCP1 457
|
||||
+#define SRST_H_HDCP1 458
|
||||
+#define SRST_HDCP1 459
|
||||
+#define SRST_P_TRNG1 460
|
||||
+#define SRST_P_HDMITX0 461
|
||||
+
|
||||
+#define SRST_HDMITX0_REF 462
|
||||
+#define SRST_P_HDMITX1 463
|
||||
+#define SRST_HDMITX1_REF 464
|
||||
+#define SRST_A_HDMIRX 465
|
||||
+#define SRST_P_HDMIRX 466
|
||||
+#define SRST_HDMIRX_REF 467
|
||||
+
|
||||
+#define SRST_P_EDP0 468
|
||||
+#define SRST_EDP0_24M 469
|
||||
+#define SRST_P_EDP1 470
|
||||
+#define SRST_EDP1_24M 471
|
||||
+#define SRST_M_I2S5_8CH_TX 472
|
||||
+#define SRST_H_I2S5_8CH 473
|
||||
+#define SRST_M_I2S6_8CH_TX 474
|
||||
+
|
||||
+#define SRST_M_I2S6_8CH_RX 475
|
||||
+#define SRST_H_I2S6_8CH 476
|
||||
+#define SRST_H_SPDIF3 477
|
||||
+#define SRST_M_SPDIF3 478
|
||||
+#define SRST_H_SPDIF4 479
|
||||
+#define SRST_M_SPDIF4 480
|
||||
+#define SRST_H_SPDIFRX0 481
|
||||
+#define SRST_M_SPDIFRX0 482
|
||||
+#define SRST_H_SPDIFRX1 483
|
||||
+#define SRST_M_SPDIFRX1 484
|
||||
+
|
||||
+#define SRST_H_SPDIFRX2 485
|
||||
+#define SRST_M_SPDIFRX2 486
|
||||
+#define SRST_LINKSYM_HDMITXPHY0 487
|
||||
+#define SRST_LINKSYM_HDMITXPHY1 488
|
||||
+#define SRST_VO1_BRIDGE0 489
|
||||
+#define SRST_VO1_BRIDGE1 490
|
||||
+
|
||||
+#define SRST_H_I2S9_8CH 491
|
||||
+#define SRST_M_I2S9_8CH_RX 492
|
||||
+#define SRST_H_I2S10_8CH 493
|
||||
+#define SRST_M_I2S10_8CH_RX 494
|
||||
+#define SRST_P_S_HDMIRX 495
|
||||
+
|
||||
+#define SRST_GPU 496
|
||||
+#define SRST_SYS_GPU 497
|
||||
+#define SRST_A_S_GPU_BIU 498
|
||||
+#define SRST_A_M0_GPU_BIU 499
|
||||
+#define SRST_A_M1_GPU_BIU 500
|
||||
+#define SRST_A_M2_GPU_BIU 501
|
||||
+#define SRST_A_M3_GPU_BIU 502
|
||||
+#define SRST_P_GPU_BIU 503
|
||||
+#define SRST_P_GPU_PVTM 504
|
||||
+
|
||||
+#define SRST_GPU_PVTM 505
|
||||
+#define SRST_P_GPU_GRF 506
|
||||
+#define SRST_GPU_PVTPLL 507
|
||||
+#define SRST_GPU_JTAG 508
|
||||
+
|
||||
+#define SRST_A_AV1_BIU 509
|
||||
+#define SRST_A_AV1 510
|
||||
+#define SRST_P_AV1_BIU 511
|
||||
+#define SRST_P_AV1 512
|
||||
+
|
||||
+#define SRST_A_DDR_BIU 513
|
||||
+#define SRST_A_DMA2DDR 514
|
||||
+#define SRST_A_DDR_SHAREMEM 515
|
||||
+#define SRST_A_DDR_SHAREMEM_BIU 516
|
||||
+#define SRST_A_CENTER_S200_BIU 517
|
||||
+#define SRST_A_CENTER_S400_BIU 518
|
||||
+#define SRST_H_AHB2APB 519
|
||||
+#define SRST_H_CENTER_BIU 520
|
||||
+#define SRST_F_DDR_CM0_CORE 521
|
||||
+
|
||||
+#define SRST_DDR_TIMER0 522
|
||||
+#define SRST_DDR_TIMER1 523
|
||||
+#define SRST_T_WDT_DDR 524
|
||||
+#define SRST_T_DDR_CM0_JTAG 525
|
||||
+#define SRST_P_CENTER_GRF 526
|
||||
+#define SRST_P_AHB2APB 527
|
||||
+#define SRST_P_WDT 528
|
||||
+#define SRST_P_TIMER 529
|
||||
+#define SRST_P_DMA2DDR 530
|
||||
+#define SRST_P_SHAREMEM 531
|
||||
+#define SRST_P_CENTER_BIU 532
|
||||
+#define SRST_P_CENTER_CHANNEL_BIU 533
|
||||
+
|
||||
+#define SRST_P_USBDPGRF0 534
|
||||
+#define SRST_P_USBDPPHY0 535
|
||||
+#define SRST_P_USBDPGRF1 536
|
||||
+#define SRST_P_USBDPPHY1 537
|
||||
+#define SRST_P_HDPTX0 538
|
||||
+#define SRST_P_HDPTX1 539
|
||||
+#define SRST_P_APB2ASB_SLV_BOT_RIGHT 540
|
||||
+#define SRST_P_USB2PHY_U3_0_GRF0 541
|
||||
+#define SRST_P_USB2PHY_U3_1_GRF0 542
|
||||
+#define SRST_P_USB2PHY_U2_0_GRF0 543
|
||||
+#define SRST_P_USB2PHY_U2_1_GRF0 544
|
||||
+#define SRST_HDPTX0_ROPLL 545
|
||||
+#define SRST_HDPTX0_LCPLL 546
|
||||
+#define SRST_HDPTX0 547
|
||||
+#define SRST_HDPTX1_ROPLL 548
|
||||
+
|
||||
+#define SRST_HDPTX1_LCPLL 549
|
||||
+#define SRST_HDPTX1 550
|
||||
+#define SRST_HDPTX0_HDMIRXPHY_SET 551
|
||||
+#define SRST_USBDP_COMBO_PHY0 552
|
||||
+#define SRST_USBDP_COMBO_PHY0_LCPLL 553
|
||||
+#define SRST_USBDP_COMBO_PHY0_ROPLL 554
|
||||
+#define SRST_USBDP_COMBO_PHY0_PCS_HS 555
|
||||
+#define SRST_USBDP_COMBO_PHY1 556
|
||||
+#define SRST_USBDP_COMBO_PHY1_LCPLL 557
|
||||
+#define SRST_USBDP_COMBO_PHY1_ROPLL 558
|
||||
+#define SRST_USBDP_COMBO_PHY1_PCS_HS 559
|
||||
+#define SRST_HDMIHDP0 560
|
||||
+#define SRST_HDMIHDP1 561
|
||||
+
|
||||
+#define SRST_A_VO1USB_TOP_BIU 562
|
||||
+#define SRST_H_VO1USB_TOP_BIU 563
|
||||
+
|
||||
+#define SRST_H_SDIO_BIU 564
|
||||
+#define SRST_H_SDIO 565
|
||||
+#define SRST_SDIO 566
|
||||
+
|
||||
+#define SRST_H_RGA3_BIU 567
|
||||
+#define SRST_A_RGA3_BIU 568
|
||||
+#define SRST_H_RGA3_1 569
|
||||
+#define SRST_A_RGA3_1 570
|
||||
+#define SRST_RGA3_1_CORE 571
|
||||
+
|
||||
+#define SRST_REF_PIPE_PHY0 572
|
||||
+#define SRST_REF_PIPE_PHY1 573
|
||||
+#define SRST_REF_PIPE_PHY2 574
|
||||
+
|
||||
+#define SRST_P_PHPTOP_CRU 575
|
||||
+#define SRST_P_PCIE2_GRF0 576
|
||||
+#define SRST_P_PCIE2_GRF1 577
|
||||
+#define SRST_P_PCIE2_GRF2 578
|
||||
+#define SRST_P_PCIE2_PHY0 579
|
||||
+#define SRST_P_PCIE2_PHY1 580
|
||||
+#define SRST_P_PCIE2_PHY2 581
|
||||
+#define SRST_P_PCIE3_PHY 582
|
||||
+#define SRST_P_APB2ASB_SLV_CHIP_TOP 583
|
||||
+#define SRST_PCIE30_PHY 584
|
||||
+
|
||||
+#define SRST_H_PMU1_BIU 585
|
||||
+#define SRST_P_PMU1_BIU 586
|
||||
+#define SRST_H_PMU_CM0_BIU 587
|
||||
+#define SRST_F_PMU_CM0_CORE 588
|
||||
+#define SRST_T_PMU1_CM0_JTAG 589
|
||||
+
|
||||
+#define SRST_DDR_FAIL_SAFE 590
|
||||
+#define SRST_P_CRU_PMU1 591
|
||||
+#define SRST_P_PMU1_GRF 592
|
||||
+#define SRST_P_PMU1_IOC 593
|
||||
+#define SRST_P_PMU1WDT 594
|
||||
+#define SRST_T_PMU1WDT 595
|
||||
+#define SRST_P_PMU1TIMER 596
|
||||
+#define SRST_PMU1TIMER0 597
|
||||
+#define SRST_PMU1TIMER1 598
|
||||
+#define SRST_P_PMU1PWM 599
|
||||
+#define SRST_PMU1PWM 600
|
||||
+
|
||||
+#define SRST_P_I2C0 601
|
||||
+#define SRST_I2C0 602
|
||||
+#define SRST_S_UART0 603
|
||||
+#define SRST_P_UART0 604
|
||||
+#define SRST_H_I2S1_8CH 605
|
||||
+#define SRST_M_I2S1_8CH_TX 606
|
||||
+#define SRST_M_I2S1_8CH_RX 607
|
||||
+#define SRST_H_PDM0 608
|
||||
+#define SRST_PDM0 609
|
||||
+
|
||||
+#define SRST_H_VAD 610
|
||||
+#define SRST_HDPTX0_INIT 611
|
||||
+#define SRST_HDPTX0_CMN 612
|
||||
+#define SRST_HDPTX0_LANE 613
|
||||
+#define SRST_HDPTX1_INIT 614
|
||||
+
|
||||
+#define SRST_HDPTX1_CMN 615
|
||||
+#define SRST_HDPTX1_LANE 616
|
||||
+#define SRST_M_MIPI_DCPHY0 617
|
||||
+#define SRST_S_MIPI_DCPHY0 618
|
||||
+#define SRST_M_MIPI_DCPHY1 619
|
||||
+#define SRST_S_MIPI_DCPHY1 620
|
||||
+#define SRST_OTGPHY_U3_0 621
|
||||
+#define SRST_OTGPHY_U3_1 622
|
||||
+#define SRST_OTGPHY_U2_0 623
|
||||
+#define SRST_OTGPHY_U2_1 624
|
||||
+
|
||||
+#define SRST_P_PMU0GRF 625
|
||||
+#define SRST_P_PMU0IOC 626
|
||||
+#define SRST_P_GPIO0 627
|
||||
+#define SRST_GPIO0 628
|
||||
+
|
||||
+#define SRST_A_SECURE_NS_BIU 629
|
||||
+#define SRST_H_SECURE_NS_BIU 630
|
||||
+#define SRST_A_SECURE_S_BIU 631
|
||||
+#define SRST_H_SECURE_S_BIU 632
|
||||
+#define SRST_P_SECURE_S_BIU 633
|
||||
+#define SRST_CRYPTO_CORE 634
|
||||
+
|
||||
+#define SRST_CRYPTO_PKA 635
|
||||
+#define SRST_CRYPTO_RNG 636
|
||||
+#define SRST_A_CRYPTO 637
|
||||
+#define SRST_H_CRYPTO 638
|
||||
+#define SRST_KEYLADDER_CORE 639
|
||||
+#define SRST_KEYLADDER_RNG 640
|
||||
+#define SRST_A_KEYLADDER 641
|
||||
+#define SRST_H_KEYLADDER 642
|
||||
+#define SRST_P_OTPC_S 643
|
||||
+#define SRST_OTPC_S 644
|
||||
+#define SRST_WDT_S 645
|
||||
+
|
||||
+#define SRST_T_WDT_S 646
|
||||
+#define SRST_H_BOOTROM 647
|
||||
+#define SRST_A_DCF 648
|
||||
+#define SRST_P_DCF 649
|
||||
+#define SRST_H_BOOTROM_NS 650
|
||||
+#define SRST_P_KEYLADDER 651
|
||||
+#define SRST_H_TRNG_S 652
|
||||
+
|
||||
+#define SRST_H_TRNG_NS 653
|
||||
+#define SRST_D_SDMMC_BUFFER 654
|
||||
+#define SRST_H_SDMMC 655
|
||||
+#define SRST_H_SDMMC_BUFFER 656
|
||||
+#define SRST_SDMMC 657
|
||||
+#define SRST_P_TRNG_CHK 658
|
||||
+#define SRST_TRNG_S 659
|
||||
+
|
||||
+#endif
|
||||
@ -1,79 +0,0 @@
|
||||
From cf87691f143e6cc5727767b02ec2be3725534a5d Mon Sep 17 00:00:00 2001
|
||||
From: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Date: Tue, 18 Oct 2022 17:14:02 +0200
|
||||
Subject: [PATCH] clk: rockchip: add register offset of the cores select parent
|
||||
|
||||
The cores select parent register is special on RK3588.
|
||||
|
||||
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-cpu.c | 28 ++++++++++++++++++++--------
|
||||
drivers/clk/rockchip/clk.h | 3 +++
|
||||
2 files changed, 23 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-cpu.c
|
||||
+++ b/drivers/clk/rockchip/clk-cpu.c
|
||||
@@ -166,10 +166,16 @@ static int rockchip_cpuclk_pre_rate_chan
|
||||
}
|
||||
}
|
||||
/* select alternate parent */
|
||||
- writel(HIWORD_UPDATE(reg_data->mux_core_alt,
|
||||
- reg_data->mux_core_mask,
|
||||
- reg_data->mux_core_shift),
|
||||
- cpuclk->reg_base + reg_data->core_reg[0]);
|
||||
+ if (reg_data->mux_core_reg)
|
||||
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
|
||||
+ reg_data->mux_core_mask,
|
||||
+ reg_data->mux_core_shift),
|
||||
+ cpuclk->reg_base + reg_data->mux_core_reg);
|
||||
+ else
|
||||
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
|
||||
+ reg_data->mux_core_mask,
|
||||
+ reg_data->mux_core_shift),
|
||||
+ cpuclk->reg_base + reg_data->core_reg[0]);
|
||||
|
||||
spin_unlock_irqrestore(cpuclk->lock, flags);
|
||||
return 0;
|
||||
@@ -202,10 +208,16 @@ static int rockchip_cpuclk_post_rate_cha
|
||||
* primary parent by the extra dividers that were needed for the alt.
|
||||
*/
|
||||
|
||||
- writel(HIWORD_UPDATE(reg_data->mux_core_main,
|
||||
- reg_data->mux_core_mask,
|
||||
- reg_data->mux_core_shift),
|
||||
- cpuclk->reg_base + reg_data->core_reg[0]);
|
||||
+ if (reg_data->mux_core_reg)
|
||||
+ writel(HIWORD_UPDATE(reg_data->mux_core_main,
|
||||
+ reg_data->mux_core_mask,
|
||||
+ reg_data->mux_core_shift),
|
||||
+ cpuclk->reg_base + reg_data->mux_core_reg);
|
||||
+ else
|
||||
+ writel(HIWORD_UPDATE(reg_data->mux_core_main,
|
||||
+ reg_data->mux_core_mask,
|
||||
+ reg_data->mux_core_shift),
|
||||
+ cpuclk->reg_base + reg_data->core_reg[0]);
|
||||
|
||||
/* remove dividers */
|
||||
for (i = 0; i < reg_data->num_cores; i++) {
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -389,6 +389,8 @@ struct rockchip_cpuclk_rate_table {
|
||||
* @div_core_shift[]: cores divider offset used to divide the pll value
|
||||
* @div_core_mask[]: cores divider mask
|
||||
* @num_cores: number of cpu cores
|
||||
+ * @mux_core_reg: register offset of the cores select parent
|
||||
+ * @mux_core_alt: mux value to select alternate parent
|
||||
* @mux_core_main: mux value to select main parent of core
|
||||
* @mux_core_shift: offset of the core multiplexer
|
||||
* @mux_core_mask: core multiplexer mask
|
||||
@@ -398,6 +400,7 @@ struct rockchip_cpuclk_reg_data {
|
||||
u8 div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
|
||||
u32 div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
|
||||
int num_cores;
|
||||
+ int mux_core_reg;
|
||||
u8 mux_core_alt;
|
||||
u8 mux_core_main;
|
||||
u8 mux_core_shift;
|
||||
@ -1,300 +0,0 @@
|
||||
From 8f6594494b1cb0ad14493795b436413cfe64a0f8 Mon Sep 17 00:00:00 2001
|
||||
From: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Date: Tue, 18 Oct 2022 17:14:03 +0200
|
||||
Subject: [PATCH] clk: rockchip: add pll type for RK3588
|
||||
|
||||
Add RK3588 PLL support fully relying on lookup tables like
|
||||
the other upstream supported rockchip platforms.
|
||||
|
||||
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
[rebase and modify code to avoid PLL parameter calculation]
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221018151407.63395-6-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-pll.c | 218 ++++++++++++++++++++++++++++++++-
|
||||
drivers/clk/rockchip/clk.h | 18 +++
|
||||
2 files changed, 235 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-pll.c
|
||||
+++ b/drivers/clk/rockchip/clk-pll.c
|
||||
@@ -843,6 +843,213 @@ static const struct clk_ops rockchip_rk3
|
||||
};
|
||||
|
||||
/*
|
||||
+ * PLL used in RK3588
|
||||
+ */
|
||||
+
|
||||
+#define RK3588_PLLCON(i) (i * 0x4)
|
||||
+#define RK3588_PLLCON0_M_MASK 0x3ff
|
||||
+#define RK3588_PLLCON0_M_SHIFT 0
|
||||
+#define RK3588_PLLCON1_P_MASK 0x3f
|
||||
+#define RK3588_PLLCON1_P_SHIFT 0
|
||||
+#define RK3588_PLLCON1_S_MASK 0x7
|
||||
+#define RK3588_PLLCON1_S_SHIFT 6
|
||||
+#define RK3588_PLLCON2_K_MASK 0xffff
|
||||
+#define RK3588_PLLCON2_K_SHIFT 0
|
||||
+#define RK3588_PLLCON1_PWRDOWN BIT(13)
|
||||
+#define RK3588_PLLCON6_LOCK_STATUS BIT(15)
|
||||
+
|
||||
+static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
|
||||
+{
|
||||
+ u32 pllcon;
|
||||
+ int ret;
|
||||
+
|
||||
+ /*
|
||||
+ * Lock time typical 250, max 500 input clock cycles @24MHz
|
||||
+ * So define a very safe maximum of 1000us, meaning 24000 cycles.
|
||||
+ */
|
||||
+ ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6),
|
||||
+ pllcon,
|
||||
+ pllcon & RK3588_PLLCON6_LOCK_STATUS,
|
||||
+ 0, 1000);
|
||||
+ if (ret)
|
||||
+ pr_err("%s: timeout waiting for pll to lock\n", __func__);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll,
|
||||
+ struct rockchip_pll_rate_table *rate)
|
||||
+{
|
||||
+ u32 pllcon;
|
||||
+
|
||||
+ pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0));
|
||||
+ rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK);
|
||||
+
|
||||
+ pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1));
|
||||
+ rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK);
|
||||
+ rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK);
|
||||
+
|
||||
+ pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2));
|
||||
+ rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK);
|
||||
+}
|
||||
+
|
||||
+static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
|
||||
+{
|
||||
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
+ struct rockchip_pll_rate_table cur;
|
||||
+ u64 rate64 = prate, postdiv;
|
||||
+
|
||||
+ rockchip_rk3588_pll_get_params(pll, &cur);
|
||||
+
|
||||
+ rate64 *= cur.m;
|
||||
+ do_div(rate64, cur.p);
|
||||
+
|
||||
+ if (cur.k) {
|
||||
+ /* fractional mode */
|
||||
+ u64 frac_rate64 = prate * cur.k;
|
||||
+
|
||||
+ postdiv = cur.p * 65535;
|
||||
+ do_div(frac_rate64, postdiv);
|
||||
+ rate64 += frac_rate64;
|
||||
+ }
|
||||
+ rate64 = rate64 >> cur.s;
|
||||
+
|
||||
+ return (unsigned long)rate64;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
|
||||
+ const struct rockchip_pll_rate_table *rate)
|
||||
+{
|
||||
+ const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
|
||||
+ struct clk_mux *pll_mux = &pll->pll_mux;
|
||||
+ struct rockchip_pll_rate_table cur;
|
||||
+ int rate_change_remuxed = 0;
|
||||
+ int cur_parent;
|
||||
+ int ret;
|
||||
+
|
||||
+ pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n",
|
||||
+ __func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
|
||||
+
|
||||
+ rockchip_rk3588_pll_get_params(pll, &cur);
|
||||
+ cur.rate = 0;
|
||||
+
|
||||
+ if (pll->type == pll_rk3588) {
|
||||
+ cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
|
||||
+ if (cur_parent == PLL_MODE_NORM) {
|
||||
+ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
|
||||
+ rate_change_remuxed = 1;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* set pll power down */
|
||||
+ writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN,
|
||||
+ RK3588_PLLCON1_PWRDOWN, 0),
|
||||
+ pll->reg_base + RK3399_PLLCON(1));
|
||||
+
|
||||
+ /* update pll values */
|
||||
+ writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT),
|
||||
+ pll->reg_base + RK3399_PLLCON(0));
|
||||
+
|
||||
+ writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) |
|
||||
+ HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT),
|
||||
+ pll->reg_base + RK3399_PLLCON(1));
|
||||
+
|
||||
+ writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT),
|
||||
+ pll->reg_base + RK3399_PLLCON(2));
|
||||
+
|
||||
+ /* set pll power up */
|
||||
+ writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),
|
||||
+ pll->reg_base + RK3588_PLLCON(1));
|
||||
+
|
||||
+ /* wait for the pll to lock */
|
||||
+ ret = rockchip_rk3588_pll_wait_lock(pll);
|
||||
+ if (ret) {
|
||||
+ pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
|
||||
+ __func__);
|
||||
+ rockchip_rk3588_pll_set_params(pll, &cur);
|
||||
+ }
|
||||
+
|
||||
+ if ((pll->type == pll_rk3588) && rate_change_remuxed)
|
||||
+ pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
+static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate,
|
||||
+ unsigned long prate)
|
||||
+{
|
||||
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
+ const struct rockchip_pll_rate_table *rate;
|
||||
+
|
||||
+ pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
|
||||
+ __func__, __clk_get_name(hw->clk), drate, prate);
|
||||
+
|
||||
+ /* Get required rate settings from table */
|
||||
+ rate = rockchip_get_pll_settings(pll, drate);
|
||||
+ if (!rate) {
|
||||
+ pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
|
||||
+ drate, __clk_get_name(hw->clk));
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return rockchip_rk3588_pll_set_params(pll, rate);
|
||||
+}
|
||||
+
|
||||
+static int rockchip_rk3588_pll_enable(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
+
|
||||
+ writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),
|
||||
+ pll->reg_base + RK3588_PLLCON(1));
|
||||
+ rockchip_rk3588_pll_wait_lock(pll);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static void rockchip_rk3588_pll_disable(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
+
|
||||
+ writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0),
|
||||
+ pll->reg_base + RK3588_PLLCON(1));
|
||||
+}
|
||||
+
|
||||
+static int rockchip_rk3588_pll_is_enabled(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
+ u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1));
|
||||
+
|
||||
+ return !(pllcon & RK3588_PLLCON1_PWRDOWN);
|
||||
+}
|
||||
+
|
||||
+static int rockchip_rk3588_pll_init(struct clk_hw *hw)
|
||||
+{
|
||||
+ struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
|
||||
+
|
||||
+ if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
|
||||
+ return 0;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = {
|
||||
+ .recalc_rate = rockchip_rk3588_pll_recalc_rate,
|
||||
+ .enable = rockchip_rk3588_pll_enable,
|
||||
+ .disable = rockchip_rk3588_pll_disable,
|
||||
+ .is_enabled = rockchip_rk3588_pll_is_enabled,
|
||||
+};
|
||||
+
|
||||
+static const struct clk_ops rockchip_rk3588_pll_clk_ops = {
|
||||
+ .recalc_rate = rockchip_rk3588_pll_recalc_rate,
|
||||
+ .round_rate = rockchip_pll_round_rate,
|
||||
+ .set_rate = rockchip_rk3588_pll_set_rate,
|
||||
+ .enable = rockchip_rk3588_pll_enable,
|
||||
+ .disable = rockchip_rk3588_pll_disable,
|
||||
+ .is_enabled = rockchip_rk3588_pll_is_enabled,
|
||||
+ .init = rockchip_rk3588_pll_init,
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
* Common registering of pll clocks
|
||||
*/
|
||||
|
||||
@@ -890,7 +1097,8 @@ struct clk *rockchip_clk_register_pll(st
|
||||
if (pll_type == pll_rk3036 ||
|
||||
pll_type == pll_rk3066 ||
|
||||
pll_type == pll_rk3328 ||
|
||||
- pll_type == pll_rk3399)
|
||||
+ pll_type == pll_rk3399 ||
|
||||
+ pll_type == pll_rk3588)
|
||||
pll_mux->flags |= CLK_MUX_HIWORD_MASK;
|
||||
|
||||
/* the actual muxing is xin24m, pll-output, xin32k */
|
||||
@@ -957,6 +1165,14 @@ struct clk *rockchip_clk_register_pll(st
|
||||
else
|
||||
init.ops = &rockchip_rk3399_pll_clk_ops;
|
||||
break;
|
||||
+ case pll_rk3588:
|
||||
+ case pll_rk3588_core:
|
||||
+ if (!pll->rate_table)
|
||||
+ init.ops = &rockchip_rk3588_pll_clk_norate_ops;
|
||||
+ else
|
||||
+ init.ops = &rockchip_rk3588_pll_clk_ops;
|
||||
+ init.flags = flags;
|
||||
+ break;
|
||||
default:
|
||||
pr_warn("%s: Unknown pll type for pll clk %s\n",
|
||||
__func__, name);
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -240,6 +240,8 @@ enum rockchip_pll_type {
|
||||
pll_rk3066,
|
||||
pll_rk3328,
|
||||
pll_rk3399,
|
||||
+ pll_rk3588,
|
||||
+ pll_rk3588_core,
|
||||
};
|
||||
|
||||
#define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \
|
||||
@@ -272,6 +274,15 @@ enum rockchip_pll_type {
|
||||
.nb = _nb, \
|
||||
}
|
||||
|
||||
+#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k) \
|
||||
+{ \
|
||||
+ .rate = _rate##U, \
|
||||
+ .p = _p, \
|
||||
+ .m = _m, \
|
||||
+ .s = _s, \
|
||||
+ .k = _k, \
|
||||
+}
|
||||
+
|
||||
/**
|
||||
* struct rockchip_clk_provider - information about clock provider
|
||||
* @reg_base: virtual address for the register base.
|
||||
@@ -307,6 +318,13 @@ struct rockchip_pll_rate_table {
|
||||
unsigned int dsmpd;
|
||||
unsigned int frac;
|
||||
};
|
||||
+ struct {
|
||||
+ /* for RK3588 */
|
||||
+ unsigned int m;
|
||||
+ unsigned int p;
|
||||
+ unsigned int s;
|
||||
+ unsigned int k;
|
||||
+ };
|
||||
};
|
||||
};
|
||||
|
||||
@ -1,122 +0,0 @@
|
||||
From 2004b7b1803719eaaaee5fa6b089b1699a65d31d Mon Sep 17 00:00:00 2001
|
||||
From: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
Date: Tue, 18 Oct 2022 17:14:04 +0200
|
||||
Subject: [PATCH] clk: rockchip: allow additional mux options for cpu-clock
|
||||
frequency changes
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
In order to improve the main frequency of CPU, the clock path of CPU is
|
||||
simplified as follows:
|
||||
|--\
|
||||
| \ |--\
|
||||
--apll--|\ | \ | \
|
||||
| |--apll_core--| \ | \
|
||||
--24M---|/ |mux1 |--[gate]--|mux2|---clk_core
|
||||
| / | /
|
||||
--gpll--|\ | / |------| /
|
||||
| |--gpll_core--| / | |--/
|
||||
--24M---|/ |--/ |
|
||||
|
|
||||
-------apll_directly--------------|
|
||||
|
||||
When the CPU requests high frequency, we want to use MUX2 select the
|
||||
"apll_directly".
|
||||
At low frequencies use MUX1 to select “apll_core" and then MUX2 to
|
||||
select "apll_core_gate".
|
||||
|
||||
However, in this way, the CPU frequency conversion needs to be
|
||||
in the following order:
|
||||
1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
|
||||
2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
|
||||
sets normal_mode
|
||||
3. MUX1 select "apll_core", MUX2 select "apll_directly"
|
||||
|
||||
So add pre_mux and post_mux options to cover this special requirements.
|
||||
|
||||
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
|
||||
[rebase]
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-cpu.c | 41 ++++++++++++++++++++++++++++++++++
|
||||
drivers/clk/rockchip/clk.h | 2 ++
|
||||
2 files changed, 43 insertions(+)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-cpu.c
|
||||
+++ b/drivers/clk/rockchip/clk-cpu.c
|
||||
@@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers
|
||||
}
|
||||
}
|
||||
|
||||
+static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,
|
||||
+ const struct rockchip_cpuclk_rate_table *rate)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ /* alternate parent is active now. set the pre_muxs */
|
||||
+ for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) {
|
||||
+ const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i];
|
||||
+
|
||||
+ if (!clksel->reg)
|
||||
+ break;
|
||||
+
|
||||
+ pr_debug("%s: setting reg 0x%x to 0x%x\n",
|
||||
+ __func__, clksel->reg, clksel->val);
|
||||
+ writel(clksel->val, cpuclk->reg_base + clksel->reg);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,
|
||||
+ const struct rockchip_cpuclk_rate_table *rate)
|
||||
+{
|
||||
+ int i;
|
||||
+
|
||||
+ /* alternate parent is active now. set the muxs */
|
||||
+ for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) {
|
||||
+ const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i];
|
||||
+
|
||||
+ if (!clksel->reg)
|
||||
+ break;
|
||||
+
|
||||
+ pr_debug("%s: setting reg 0x%x to 0x%x\n",
|
||||
+ __func__, clksel->reg, clksel->val);
|
||||
+ writel(clksel->val, cpuclk->reg_base + clksel->reg);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
|
||||
struct clk_notifier_data *ndata)
|
||||
{
|
||||
@@ -165,6 +201,9 @@ static int rockchip_cpuclk_pre_rate_chan
|
||||
cpuclk->reg_base + reg_data->core_reg[i]);
|
||||
}
|
||||
}
|
||||
+
|
||||
+ rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
|
||||
+
|
||||
/* select alternate parent */
|
||||
if (reg_data->mux_core_reg)
|
||||
writel(HIWORD_UPDATE(reg_data->mux_core_alt,
|
||||
@@ -219,6 +258,8 @@ static int rockchip_cpuclk_post_rate_cha
|
||||
reg_data->mux_core_shift),
|
||||
cpuclk->reg_base + reg_data->core_reg[0]);
|
||||
|
||||
+ rockchip_cpuclk_set_post_muxs(cpuclk, rate);
|
||||
+
|
||||
/* remove dividers */
|
||||
for (i = 0; i < reg_data->num_cores; i++) {
|
||||
writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -399,6 +399,8 @@ struct rockchip_cpuclk_clksel {
|
||||
struct rockchip_cpuclk_rate_table {
|
||||
unsigned long prate;
|
||||
struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
|
||||
+ struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
|
||||
+ struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
|
||||
};
|
||||
|
||||
/**
|
||||
@ -1,72 +0,0 @@
|
||||
From ff94c8660dac444081f2f650fae36a283c55b117 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 18 Oct 2022 17:14:05 +0200
|
||||
Subject: [PATCH] clk: rockchip: simplify rockchip_clk_add_lookup
|
||||
|
||||
rockchip_clk_add_lookup is only called from within the file,
|
||||
so it can be made static. The additional checks are removed
|
||||
with the following reasoning:
|
||||
|
||||
1. The data structure is initialized by rockchip_clk_init(),
|
||||
which is called by all rockchip platforms before the clocks
|
||||
are registered. Not doing so would result in an incomplete
|
||||
clock tree at the moment, which is a fatal error. In other
|
||||
parts of the kernel these kind of checks are usually
|
||||
omitted, so this was done here. The alternative is adding
|
||||
a pr_err to inform the kernel programmer adding a new platform
|
||||
about his incorrect code. Apart from that we are also not
|
||||
checking if the clock id is within the array boundings.
|
||||
|
||||
2. While not used so far by any rockchip platform, 0 is a valid
|
||||
clock identifier. To align rockchip closer to other ARM
|
||||
platforms we will start using it with rk3588.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221018151407.63395-8-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk.c | 14 ++++++--------
|
||||
drivers/clk/rockchip/clk.h | 2 --
|
||||
2 files changed, 6 insertions(+), 10 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk.c
|
||||
+++ b/drivers/clk/rockchip/clk.c
|
||||
@@ -198,6 +198,12 @@ static void rockchip_fractional_approxim
|
||||
clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n);
|
||||
}
|
||||
|
||||
+static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
||||
+ struct clk *clk, unsigned int id)
|
||||
+{
|
||||
+ ctx->clk_data.clks[id] = clk;
|
||||
+}
|
||||
+
|
||||
static struct clk *rockchip_clk_register_frac_branch(
|
||||
struct rockchip_clk_provider *ctx, const char *name,
|
||||
const char *const *parent_names, u8 num_parents,
|
||||
@@ -401,14 +407,6 @@ void rockchip_clk_of_add_provider(struct
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
|
||||
|
||||
-void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
||||
- struct clk *clk, unsigned int id)
|
||||
-{
|
||||
- if (ctx->clk_data.clks && id)
|
||||
- ctx->clk_data.clks[id] = clk;
|
||||
-}
|
||||
-EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup);
|
||||
-
|
||||
void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_pll_clock *list,
|
||||
unsigned int nr_pll, int grf_lock_offset)
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -928,8 +928,6 @@ struct rockchip_clk_provider *rockchip_c
|
||||
void __iomem *base, unsigned long nr_clks);
|
||||
void rockchip_clk_of_add_provider(struct device_node *np,
|
||||
struct rockchip_clk_provider *ctx);
|
||||
-void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
||||
- struct clk *clk, unsigned int id);
|
||||
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk);
|
||||
@ -1,130 +0,0 @@
|
||||
From ada8f95ba04e8fe07289b7de157ae99bb96bc8cb Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Tue, 18 Oct 2022 17:14:06 +0200
|
||||
Subject: [PATCH] clk: rockchip: add lookup table support
|
||||
|
||||
Add support for mapping reset IDs to register offsets
|
||||
to support gapless continous platform reset IDs.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221018151407.63395-9-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk.h | 21 +++++++++++++++------
|
||||
drivers/clk/rockchip/softrst.c | 34 +++++++++++++++++++++++++---------
|
||||
2 files changed, 40 insertions(+), 15 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk.h
|
||||
+++ b/drivers/clk/rockchip/clk.h
|
||||
@@ -958,15 +958,24 @@ struct clk *rockchip_clk_register_halfdi
|
||||
spinlock_t *lock);
|
||||
|
||||
#ifdef CONFIG_RESET_CONTROLLER
|
||||
-void rockchip_register_softrst(struct device_node *np,
|
||||
- unsigned int num_regs,
|
||||
- void __iomem *base, u8 flags);
|
||||
+void rockchip_register_softrst_lut(struct device_node *np,
|
||||
+ const int *lookup_table,
|
||||
+ unsigned int num_regs,
|
||||
+ void __iomem *base, u8 flags);
|
||||
#else
|
||||
-static inline void rockchip_register_softrst(struct device_node *np,
|
||||
- unsigned int num_regs,
|
||||
- void __iomem *base, u8 flags)
|
||||
+static inline void rockchip_register_softrst_lut(struct device_node *np,
|
||||
+ const int *lookup_table,
|
||||
+ unsigned int num_regs,
|
||||
+ void __iomem *base, u8 flags)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
+static inline void rockchip_register_softrst(struct device_node *np,
|
||||
+ unsigned int num_regs,
|
||||
+ void __iomem *base, u8 flags)
|
||||
+{
|
||||
+ return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
|
||||
+}
|
||||
+
|
||||
#endif
|
||||
--- a/drivers/clk/rockchip/softrst.c
|
||||
+++ b/drivers/clk/rockchip/softrst.c
|
||||
@@ -12,6 +12,7 @@
|
||||
|
||||
struct rockchip_softrst {
|
||||
struct reset_controller_dev rcdev;
|
||||
+ const int *lut;
|
||||
void __iomem *reg_base;
|
||||
int num_regs;
|
||||
int num_per_reg;
|
||||
@@ -25,8 +26,13 @@ static int rockchip_softrst_assert(struc
|
||||
struct rockchip_softrst *softrst = container_of(rcdev,
|
||||
struct rockchip_softrst,
|
||||
rcdev);
|
||||
- int bank = id / softrst->num_per_reg;
|
||||
- int offset = id % softrst->num_per_reg;
|
||||
+ int bank, offset;
|
||||
+
|
||||
+ if (softrst->lut)
|
||||
+ id = softrst->lut[id];
|
||||
+
|
||||
+ bank = id / softrst->num_per_reg;
|
||||
+ offset = id % softrst->num_per_reg;
|
||||
|
||||
if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
|
||||
writel(BIT(offset) | (BIT(offset) << 16),
|
||||
@@ -52,8 +58,13 @@ static int rockchip_softrst_deassert(str
|
||||
struct rockchip_softrst *softrst = container_of(rcdev,
|
||||
struct rockchip_softrst,
|
||||
rcdev);
|
||||
- int bank = id / softrst->num_per_reg;
|
||||
- int offset = id % softrst->num_per_reg;
|
||||
+ int bank, offset;
|
||||
+
|
||||
+ if (softrst->lut)
|
||||
+ id = softrst->lut[id];
|
||||
+
|
||||
+ bank = id / softrst->num_per_reg;
|
||||
+ offset = id % softrst->num_per_reg;
|
||||
|
||||
if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
|
||||
writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));
|
||||
@@ -77,9 +88,10 @@ static const struct reset_control_ops ro
|
||||
.deassert = rockchip_softrst_deassert,
|
||||
};
|
||||
|
||||
-void rockchip_register_softrst(struct device_node *np,
|
||||
- unsigned int num_regs,
|
||||
- void __iomem *base, u8 flags)
|
||||
+void rockchip_register_softrst_lut(struct device_node *np,
|
||||
+ const int *lookup_table,
|
||||
+ unsigned int num_regs,
|
||||
+ void __iomem *base, u8 flags)
|
||||
{
|
||||
struct rockchip_softrst *softrst;
|
||||
int ret;
|
||||
@@ -91,13 +103,17 @@ void rockchip_register_softrst(struct de
|
||||
spin_lock_init(&softrst->lock);
|
||||
|
||||
softrst->reg_base = base;
|
||||
+ softrst->lut = lookup_table;
|
||||
softrst->flags = flags;
|
||||
softrst->num_regs = num_regs;
|
||||
softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16
|
||||
: 32;
|
||||
|
||||
softrst->rcdev.owner = THIS_MODULE;
|
||||
- softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg;
|
||||
+ if (lookup_table)
|
||||
+ softrst->rcdev.nr_resets = num_regs;
|
||||
+ else
|
||||
+ softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg;
|
||||
softrst->rcdev.ops = &rockchip_softrst_ops;
|
||||
softrst->rcdev.of_node = np;
|
||||
ret = reset_controller_register(&softrst->rcdev);
|
||||
@@ -107,4 +123,4 @@ void rockchip_register_softrst(struct de
|
||||
kfree(softrst);
|
||||
}
|
||||
};
|
||||
-EXPORT_SYMBOL_GPL(rockchip_register_softrst);
|
||||
+EXPORT_SYMBOL_GPL(rockchip_register_softrst_lut);
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,30 +0,0 @@
|
||||
From 645a5198ddba6d6b2dea8346ca796064e931a0c3 Mon Sep 17 00:00:00 2001
|
||||
From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
|
||||
Date: Sun, 2 Apr 2023 11:42:06 +0200
|
||||
Subject: [PATCH] clk: rockchip: Remove values for mmask and nmask in struct
|
||||
clk_fractional_divider
|
||||
|
||||
Now that fractional_divider clk computes mmask and nmask when needed, there
|
||||
is no more need to provide them explicitly anymore.
|
||||
|
||||
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
|
||||
Link: https://lore.kernel.org/r/58e1950566e40e2fbb31004baee57a164ca6a390.1680423909.git.christophe.jaillet@wanadoo.fr
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
drivers/clk/rockchip/clk.c | 2 --
|
||||
1 file changed, 2 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk.c
|
||||
+++ b/drivers/clk/rockchip/clk.c
|
||||
@@ -245,10 +245,8 @@ static struct clk *rockchip_clk_register
|
||||
div->reg = base + muxdiv_offset;
|
||||
div->mshift = 16;
|
||||
div->mwidth = 16;
|
||||
- div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
|
||||
div->nshift = 0;
|
||||
div->nwidth = 16;
|
||||
- div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
|
||||
div->lock = lock;
|
||||
div->approximation = rockchip_fractional_approximation;
|
||||
div_ops = &clk_fractional_divider_ops;
|
||||
@ -1,148 +0,0 @@
|
||||
From 64042c28c3bb6729df8e2fda89bc7ebbe3790907 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 3 Apr 2023 21:32:49 +0200
|
||||
Subject: [PATCH] clk: rockchip: rk3588: make gate linked clocks critical
|
||||
|
||||
RK3588 has a couple of hardware blocks called Native Interface Unit
|
||||
(NIU) that gate the clocks to devices behind them. Effectively this
|
||||
means that some clocks require two parent clocks being enabled.
|
||||
Downstream implemented this by using a separate clock driver
|
||||
("clk-link") for them, which enables the second clock using PM
|
||||
framework.
|
||||
|
||||
In the upstream kernel we are currently missing support for the second
|
||||
parent. The information about it is in the GATE_LINK() macro as
|
||||
linkname, but that is not used. Thus the second parent clock is not
|
||||
properly enabled. So far this did not really matter, since these clocks
|
||||
are mostly required for the more advanced IP blocks, that are not yet
|
||||
supported upstream. As this is about to change we need a fix. There
|
||||
are three options available:
|
||||
|
||||
1. Properly implement support for having two parent clocks in the
|
||||
clock framework.
|
||||
2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
|
||||
disabled. This wastes some power, but keeps the hack contained
|
||||
within the clock driver. Going from this to the first solution
|
||||
is easy once that has been implemented.
|
||||
3. Enabling the extra clock in the consumer driver. This leaks some
|
||||
implementation details into DT.
|
||||
|
||||
This patch implements the second option as an intermediate solution
|
||||
until the first one is available. I used an alias for CLK_IS_CRITICAL,
|
||||
so that it's easy to see which clocks are not really critical once
|
||||
the clock framework supports a better way to implement this.
|
||||
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230403193250.108693-2-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
---
|
||||
drivers/clk/rockchip/clk-rk3588.c | 42 +++++++++++++++++++------------
|
||||
1 file changed, 26 insertions(+), 16 deletions(-)
|
||||
|
||||
--- a/drivers/clk/rockchip/clk-rk3588.c
|
||||
+++ b/drivers/clk/rockchip/clk-rk3588.c
|
||||
@@ -13,15 +13,25 @@
|
||||
#include "clk.h"
|
||||
|
||||
/*
|
||||
- * GATE with additional linked clock. Downstream enables the linked clock
|
||||
- * (via runtime PM) whenever the gate is enabled. The downstream implementation
|
||||
- * does this via separate clock nodes for each of the linked gate clocks,
|
||||
- * which leaks parts of the clock tree into DT. It is unclear why this is
|
||||
- * actually needed and things work without it for simple use cases. Thus
|
||||
- * the linked clock is ignored for now.
|
||||
+ * Recent Rockchip SoCs have a new hardware block called Native Interface
|
||||
+ * Unit (NIU), which gates clocks to devices behind them. These effectively
|
||||
+ * need two parent clocks.
|
||||
+ *
|
||||
+ * Downstream enables the linked clock via runtime PM whenever the gate is
|
||||
+ * enabled. This implementation uses separate clock nodes for each of the
|
||||
+ * linked gate clocks, which leaks parts of the clock tree into DT.
|
||||
+ *
|
||||
+ * The GATE_LINK macro instead takes the second parent via 'linkname', but
|
||||
+ * ignores the information. Once the clock framework is ready to handle it, the
|
||||
+ * information should be passed on here. But since these clocks are required to
|
||||
+ * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
|
||||
+ * clocks critical until a better solution is available. This will waste some
|
||||
+ * power, but avoids leaking implementation details into DT or hanging the
|
||||
+ * system.
|
||||
*/
|
||||
#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
|
||||
GATE(_id, cname, pname, f, o, b, gf)
|
||||
+#define RK3588_LINKED_CLK CLK_IS_CRITICAL
|
||||
|
||||
|
||||
#define RK3588_GRF_SOC_STATUS0 0x600
|
||||
@@ -1446,7 +1456,7 @@ static struct rockchip_clk_branch rk3588
|
||||
COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
|
||||
RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
|
||||
RK3588_CLKGATE_CON(31), 0, GFLAGS),
|
||||
- COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
|
||||
+ COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
|
||||
RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
|
||||
RK3588_CLKGATE_CON(31), 1, GFLAGS),
|
||||
GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
|
||||
@@ -1675,13 +1685,13 @@ static struct rockchip_clk_branch rk3588
|
||||
RK3588_CLKGATE_CON(42), 9, GFLAGS),
|
||||
|
||||
/* vdpu */
|
||||
- COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
|
||||
+ COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,
|
||||
RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3588_CLKGATE_CON(44), 0, GFLAGS),
|
||||
COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
|
||||
RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
|
||||
RK3588_CLKGATE_CON(44), 1, GFLAGS),
|
||||
- COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
|
||||
+ COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
|
||||
RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
|
||||
RK3588_CLKGATE_CON(44), 2, GFLAGS),
|
||||
COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
|
||||
@@ -1732,9 +1742,9 @@ static struct rockchip_clk_branch rk3588
|
||||
COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
|
||||
RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
|
||||
RK3588_CLKGATE_CON(47), 1, GFLAGS),
|
||||
- GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
|
||||
+ GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
|
||||
RK3588_CLKGATE_CON(47), 4, GFLAGS),
|
||||
- GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
|
||||
+ GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
|
||||
RK3588_CLKGATE_CON(47), 5, GFLAGS),
|
||||
COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
|
||||
RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
|
||||
@@ -1744,10 +1754,10 @@ static struct rockchip_clk_branch rk3588
|
||||
RK3588_CLKGATE_CON(48), 6, GFLAGS),
|
||||
|
||||
/* vi */
|
||||
- COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
|
||||
+ COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,
|
||||
RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3588_CLKGATE_CON(49), 0, GFLAGS),
|
||||
- COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
|
||||
+ COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
|
||||
RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
|
||||
RK3588_CLKGATE_CON(49), 1, GFLAGS),
|
||||
COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
|
||||
@@ -1919,10 +1929,10 @@ static struct rockchip_clk_branch rk3588
|
||||
COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
|
||||
RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
|
||||
RK3588_CLKGATE_CON(52), 0, GFLAGS),
|
||||
- COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
|
||||
+ COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,
|
||||
RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
|
||||
RK3588_CLKGATE_CON(52), 1, GFLAGS),
|
||||
- COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
|
||||
+ COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
|
||||
RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
|
||||
RK3588_CLKGATE_CON(52), 2, GFLAGS),
|
||||
COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
|
||||
@@ -2425,7 +2435,7 @@ static struct rockchip_clk_branch rk3588
|
||||
|
||||
GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
|
||||
GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
|
||||
- GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),
|
||||
+ GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
|
||||
GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
|
||||
GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
|
||||
GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
|
||||
@ -1,57 +0,0 @@
|
||||
From d54fb4b25a0261bf2f2bb7093fdf11a36718bf25 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Fri, 26 May 2023 19:10:56 +0200
|
||||
Subject: [PATCH] clk: composite: Fix handling of high clock rates
|
||||
|
||||
ULONG_MAX is used by a few drivers to figure out the highest available
|
||||
clock rate via clk_round_rate(clk, ULONG_MAX). Since abs() takes a
|
||||
signed value as input, the current logic effectively calculates with
|
||||
ULONG_MAX = -1, which results in the worst parent clock being chosen
|
||||
instead of the best one.
|
||||
|
||||
For example on Rockchip RK3588 the eMMC driver tries to figure out
|
||||
the highest available clock rate. There are three parent clocks
|
||||
available resulting in the following rate diffs with the existing
|
||||
logic:
|
||||
|
||||
GPLL: abs(18446744073709551615 - 1188000000) = 1188000001
|
||||
CPLL: abs(18446744073709551615 - 1500000000) = 1500000001
|
||||
XIN24M: abs(18446744073709551615 - 24000000) = 24000001
|
||||
|
||||
As a result the clock framework will promote a maximum supported
|
||||
clock rate of 24 MHz, even though 1.5GHz are possible. With the
|
||||
updated logic any casting between signed and unsigned is avoided
|
||||
and the numbers look like this instead:
|
||||
|
||||
GPLL: 18446744073709551615 - 1188000000 = 18446744072521551615
|
||||
CPLL: 18446744073709551615 - 1500000000 = 18446744072209551615
|
||||
XIN24M: 18446744073709551615 - 24000000 = 18446744073685551615
|
||||
|
||||
As a result the parent with the highest acceptable rate is chosen
|
||||
instead of the parent clock with the lowest one.
|
||||
|
||||
Cc: stable@vger.kernel.org
|
||||
Fixes: 49502408007b ("mmc: sdhci-of-dwcmshc: properly determine max clock on Rockchip")
|
||||
Tested-by: Christopher Obbard <chris.obbard@collabora.com>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230526171057.66876-2-sebastian.reichel@collabora.com
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
||||
---
|
||||
drivers/clk/clk-composite.c | 5 ++++-
|
||||
1 file changed, 4 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/clk/clk-composite.c
|
||||
+++ b/drivers/clk/clk-composite.c
|
||||
@@ -119,7 +119,10 @@ static int clk_composite_determine_rate(
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
- rate_diff = abs(req->rate - tmp_req.rate);
|
||||
+ if (req->rate >= tmp_req.rate)
|
||||
+ rate_diff = req->rate - tmp_req.rate;
|
||||
+ else
|
||||
+ rate_diff = tmp_req.rate - req->rate;
|
||||
|
||||
if (!rate_diff || !req->best_parent_hw
|
||||
|| best_rate_diff > rate_diff) {
|
||||
@ -41,7 +41,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
|
||||
iounmap(reg_base);
|
||||
--- a/drivers/clk/rockchip/clk.c
|
||||
+++ b/drivers/clk/rockchip/clk.c
|
||||
@@ -430,6 +430,23 @@ void rockchip_clk_register_plls(struct r
|
||||
@@ -429,6 +429,23 @@ void rockchip_clk_register_plls(struct r
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
|
||||
|
||||
|
||||
@ -1,39 +0,0 @@
|
||||
From 8416360935b9b632a517503eac6e320cbd5f310a Mon Sep 17 00:00:00 2001
|
||||
From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
|
||||
Date: Fri, 18 Nov 2022 23:43:07 +0100
|
||||
Subject: [PATCH] mfd: rk808: Convert to i2c's .probe_new()
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
The probe function doesn't make use of the i2c_device_id * parameter so it
|
||||
can be trivially converted.
|
||||
|
||||
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221118224540.619276-454-uwe@kleine-koenig.org
|
||||
---
|
||||
drivers/mfd/rk808.c | 5 ++---
|
||||
1 file changed, 2 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -640,8 +640,7 @@ static const struct of_device_id rk808_o
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rk808_of_match);
|
||||
|
||||
-static int rk808_probe(struct i2c_client *client,
|
||||
- const struct i2c_device_id *id)
|
||||
+static int rk808_probe(struct i2c_client *client)
|
||||
{
|
||||
struct device_node *np = client->dev.of_node;
|
||||
struct rk808 *rk808;
|
||||
@@ -861,7 +860,7 @@ static struct i2c_driver rk808_i2c_drive
|
||||
.of_match_table = rk808_of_match,
|
||||
.pm = &rk8xx_pm_ops,
|
||||
},
|
||||
- .probe = rk808_probe,
|
||||
+ .probe_new = rk808_probe,
|
||||
.remove = rk808_remove,
|
||||
.shutdown = rk8xx_shutdown,
|
||||
};
|
||||
@ -1,96 +0,0 @@
|
||||
From 3633daacea2e54bf991d2f6b871efe9f83a0cac8 Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
Date: Mon, 31 Oct 2022 17:05:07 +0100
|
||||
Subject: [PATCH] mfd: rk808: Permit having multiple PMIC instances
|
||||
|
||||
This set each cells id to PLATFORM_DEVID_NONE to allow multiple
|
||||
instances of each cell in case multiple PMICs handled by the rk808
|
||||
driver are probed.
|
||||
|
||||
This fixes probing a RK818 and a RK817 on the Odroid Go Ultra
|
||||
devices.
|
||||
|
||||
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20221025-rk808-multi-v2-0-d292d51ada81@linaro.org
|
||||
---
|
||||
drivers/mfd/rk808.c | 26 ++++++++++++++++----------
|
||||
1 file changed, 16 insertions(+), 10 deletions(-)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -137,58 +137,64 @@ static const struct resource rk817_charg
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk805s[] = {
|
||||
- { .name = "rk808-clkout", },
|
||||
- { .name = "rk808-regulator", },
|
||||
- { .name = "rk805-pinctrl", },
|
||||
+ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
|
||||
+ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
+ { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, },
|
||||
{
|
||||
.name = "rk808-rtc",
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resources = &rtc_resources[0],
|
||||
+ .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
{ .name = "rk805-pwrkey",
|
||||
.num_resources = ARRAY_SIZE(rk805_key_resources),
|
||||
.resources = &rk805_key_resources[0],
|
||||
+ .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk808s[] = {
|
||||
- { .name = "rk808-clkout", },
|
||||
- { .name = "rk808-regulator", },
|
||||
+ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
|
||||
+ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
{
|
||||
.name = "rk808-rtc",
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resources = rtc_resources,
|
||||
+ .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk817s[] = {
|
||||
- { .name = "rk808-clkout",},
|
||||
- { .name = "rk808-regulator",},
|
||||
+ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
|
||||
+ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
{
|
||||
.name = "rk805-pwrkey",
|
||||
.num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
|
||||
.resources = &rk817_pwrkey_resources[0],
|
||||
+ .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
{
|
||||
.name = "rk808-rtc",
|
||||
.num_resources = ARRAY_SIZE(rk817_rtc_resources),
|
||||
.resources = &rk817_rtc_resources[0],
|
||||
+ .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
- { .name = "rk817-codec",},
|
||||
+ { .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, },
|
||||
{
|
||||
.name = "rk817-charger",
|
||||
.num_resources = ARRAY_SIZE(rk817_charger_resources),
|
||||
.resources = &rk817_charger_resources[0],
|
||||
+ .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk818s[] = {
|
||||
- { .name = "rk808-clkout", },
|
||||
- { .name = "rk808-regulator", },
|
||||
+ { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
{
|
||||
.name = "rk808-rtc",
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resources = rtc_resources,
|
||||
+ .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1,31 +0,0 @@
|
||||
From 5d69b181cd0db10dc8327d28ce837b3623cd531a Mon Sep 17 00:00:00 2001
|
||||
From: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
|
||||
Date: Mon, 2 Jan 2023 22:11:47 +1100
|
||||
Subject: [PATCH] mfd: rk808: Re-add rk808-clkout to RK818
|
||||
|
||||
Fixes RK818 (e.g. on Pinephone Pro) to register its clock, without which
|
||||
dependent devices (e.g. wifi/BT, via sdio-wifi-pwrseq) fail to probe.
|
||||
|
||||
This line was removed in commit 3633daacea2e
|
||||
("mfd: rk808: Permit having multiple PMIC instances"), but only from RK818.
|
||||
|
||||
Fixes: 3633daacea2e ("mfd: rk808: Permit having multiple PMIC instances")
|
||||
Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
|
||||
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
|
||||
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
Link: https://lore.kernel.org/r/20230102111147.2580861-1-tom@tom-fitzhenry.me.uk
|
||||
---
|
||||
drivers/mfd/rk808.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -189,6 +189,7 @@ static const struct mfd_cell rk817s[] =
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk818s[] = {
|
||||
+ { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
|
||||
{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
{
|
||||
.name = "rk808-rtc",
|
||||
@ -1,215 +0,0 @@
|
||||
From 2e830ccc21eb67a4c2490279d907e5e9199e5156 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 20 Oct 2022 22:42:41 +0200
|
||||
Subject: [PATCH] rtc: rk808: reduce 'struct rk808' usage
|
||||
|
||||
Reduce usage of 'struct rk808' (driver data of the parent MFD), so
|
||||
that only the chip variant field is still being accessed directly.
|
||||
This allows restructuring the MFD driver to support SPI based
|
||||
PMICs.
|
||||
|
||||
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221020204251.108565-4-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
|
||||
---
|
||||
drivers/rtc/rtc-rk808.c | 47 ++++++++++++++++++-----------------------
|
||||
1 file changed, 20 insertions(+), 27 deletions(-)
|
||||
|
||||
--- a/drivers/rtc/rtc-rk808.c
|
||||
+++ b/drivers/rtc/rtc-rk808.c
|
||||
@@ -14,7 +14,6 @@
|
||||
#include <linux/bcd.h>
|
||||
#include <linux/mfd/rk808.h>
|
||||
#include <linux/platform_device.h>
|
||||
-#include <linux/i2c.h>
|
||||
|
||||
/* RTC_CTRL_REG bitfields */
|
||||
#define BIT_RTC_CTRL_REG_STOP_RTC_M BIT(0)
|
||||
@@ -51,7 +50,7 @@ struct rk_rtc_compat_reg {
|
||||
};
|
||||
|
||||
struct rk808_rtc {
|
||||
- struct rk808 *rk808;
|
||||
+ struct regmap *regmap;
|
||||
struct rtc_device *rtc;
|
||||
struct rk_rtc_compat_reg *creg;
|
||||
int irq;
|
||||
@@ -97,12 +96,11 @@ static void gregorian_to_rockchip(struct
|
||||
static int rk808_rtc_readtime(struct device *dev, struct rtc_time *tm)
|
||||
{
|
||||
struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
|
||||
- struct rk808 *rk808 = rk808_rtc->rk808;
|
||||
u8 rtc_data[NUM_TIME_REGS];
|
||||
int ret;
|
||||
|
||||
/* Force an update of the shadowed registers right now */
|
||||
- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
+ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
BIT_RTC_CTRL_REG_RTC_GET_TIME,
|
||||
BIT_RTC_CTRL_REG_RTC_GET_TIME);
|
||||
if (ret) {
|
||||
@@ -116,7 +114,7 @@ static int rk808_rtc_readtime(struct dev
|
||||
* 32khz. If we clear the GET_TIME bit here, the time of i2c transfer
|
||||
* certainly more than 31.25us: 16 * 2.5us at 400kHz bus frequency.
|
||||
*/
|
||||
- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
+ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
BIT_RTC_CTRL_REG_RTC_GET_TIME,
|
||||
0);
|
||||
if (ret) {
|
||||
@@ -124,7 +122,7 @@ static int rk808_rtc_readtime(struct dev
|
||||
return ret;
|
||||
}
|
||||
|
||||
- ret = regmap_bulk_read(rk808->regmap, rk808_rtc->creg->seconds_reg,
|
||||
+ ret = regmap_bulk_read(rk808_rtc->regmap, rk808_rtc->creg->seconds_reg,
|
||||
rtc_data, NUM_TIME_REGS);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret);
|
||||
@@ -148,7 +146,6 @@ static int rk808_rtc_readtime(struct dev
|
||||
static int rk808_rtc_set_time(struct device *dev, struct rtc_time *tm)
|
||||
{
|
||||
struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
|
||||
- struct rk808 *rk808 = rk808_rtc->rk808;
|
||||
u8 rtc_data[NUM_TIME_REGS];
|
||||
int ret;
|
||||
|
||||
@@ -163,7 +160,7 @@ static int rk808_rtc_set_time(struct dev
|
||||
rtc_data[6] = bin2bcd(tm->tm_wday);
|
||||
|
||||
/* Stop RTC while updating the RTC registers */
|
||||
- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
+ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
BIT_RTC_CTRL_REG_STOP_RTC_M,
|
||||
BIT_RTC_CTRL_REG_STOP_RTC_M);
|
||||
if (ret) {
|
||||
@@ -171,14 +168,14 @@ static int rk808_rtc_set_time(struct dev
|
||||
return ret;
|
||||
}
|
||||
|
||||
- ret = regmap_bulk_write(rk808->regmap, rk808_rtc->creg->seconds_reg,
|
||||
+ ret = regmap_bulk_write(rk808_rtc->regmap, rk808_rtc->creg->seconds_reg,
|
||||
rtc_data, NUM_TIME_REGS);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to bull write rtc_data: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
/* Start RTC again */
|
||||
- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
+ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
BIT_RTC_CTRL_REG_STOP_RTC_M, 0);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to update RTC control: %d\n", ret);
|
||||
@@ -191,12 +188,11 @@ static int rk808_rtc_set_time(struct dev
|
||||
static int rk808_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
|
||||
{
|
||||
struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
|
||||
- struct rk808 *rk808 = rk808_rtc->rk808;
|
||||
u8 alrm_data[NUM_ALARM_REGS];
|
||||
uint32_t int_reg;
|
||||
int ret;
|
||||
|
||||
- ret = regmap_bulk_read(rk808->regmap,
|
||||
+ ret = regmap_bulk_read(rk808_rtc->regmap,
|
||||
rk808_rtc->creg->alarm_seconds_reg,
|
||||
alrm_data, NUM_ALARM_REGS);
|
||||
if (ret) {
|
||||
@@ -212,7 +208,7 @@ static int rk808_rtc_readalarm(struct de
|
||||
alrm->time.tm_year = (bcd2bin(alrm_data[5] & YEARS_REG_MSK)) + 100;
|
||||
rockchip_to_gregorian(&alrm->time);
|
||||
|
||||
- ret = regmap_read(rk808->regmap, rk808_rtc->creg->int_reg, &int_reg);
|
||||
+ ret = regmap_read(rk808_rtc->regmap, rk808_rtc->creg->int_reg, &int_reg);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to read RTC INT REG: %d\n", ret);
|
||||
return ret;
|
||||
@@ -228,10 +224,9 @@ static int rk808_rtc_readalarm(struct de
|
||||
|
||||
static int rk808_rtc_stop_alarm(struct rk808_rtc *rk808_rtc)
|
||||
{
|
||||
- struct rk808 *rk808 = rk808_rtc->rk808;
|
||||
int ret;
|
||||
|
||||
- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->int_reg,
|
||||
+ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->int_reg,
|
||||
BIT_RTC_INTERRUPTS_REG_IT_ALARM_M, 0);
|
||||
|
||||
return ret;
|
||||
@@ -239,10 +234,9 @@ static int rk808_rtc_stop_alarm(struct r
|
||||
|
||||
static int rk808_rtc_start_alarm(struct rk808_rtc *rk808_rtc)
|
||||
{
|
||||
- struct rk808 *rk808 = rk808_rtc->rk808;
|
||||
int ret;
|
||||
|
||||
- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->int_reg,
|
||||
+ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->int_reg,
|
||||
BIT_RTC_INTERRUPTS_REG_IT_ALARM_M,
|
||||
BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
|
||||
|
||||
@@ -252,7 +246,6 @@ static int rk808_rtc_start_alarm(struct
|
||||
static int rk808_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
|
||||
{
|
||||
struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
|
||||
- struct rk808 *rk808 = rk808_rtc->rk808;
|
||||
u8 alrm_data[NUM_ALARM_REGS];
|
||||
int ret;
|
||||
|
||||
@@ -272,7 +265,7 @@ static int rk808_rtc_setalarm(struct dev
|
||||
alrm_data[4] = bin2bcd(alrm->time.tm_mon + 1);
|
||||
alrm_data[5] = bin2bcd(alrm->time.tm_year - 100);
|
||||
|
||||
- ret = regmap_bulk_write(rk808->regmap,
|
||||
+ ret = regmap_bulk_write(rk808_rtc->regmap,
|
||||
rk808_rtc->creg->alarm_seconds_reg,
|
||||
alrm_data, NUM_ALARM_REGS);
|
||||
if (ret) {
|
||||
@@ -313,20 +306,18 @@ static int rk808_rtc_alarm_irq_enable(st
|
||||
static irqreturn_t rk808_alarm_irq(int irq, void *data)
|
||||
{
|
||||
struct rk808_rtc *rk808_rtc = data;
|
||||
- struct rk808 *rk808 = rk808_rtc->rk808;
|
||||
- struct i2c_client *client = rk808->i2c;
|
||||
int ret;
|
||||
|
||||
- ret = regmap_write(rk808->regmap, rk808_rtc->creg->status_reg,
|
||||
+ ret = regmap_write(rk808_rtc->regmap, rk808_rtc->creg->status_reg,
|
||||
RTC_STATUS_MASK);
|
||||
if (ret) {
|
||||
- dev_err(&client->dev,
|
||||
+ dev_err(&rk808_rtc->rtc->dev,
|
||||
"%s:Failed to update RTC status: %d\n", __func__, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
rtc_update_irq(rk808_rtc->rtc, 1, RTC_IRQF | RTC_AF);
|
||||
- dev_dbg(&client->dev,
|
||||
+ dev_dbg(&rk808_rtc->rtc->dev,
|
||||
"%s:irq=%d\n", __func__, irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
@@ -404,10 +395,12 @@ static int rk808_rtc_probe(struct platfo
|
||||
break;
|
||||
}
|
||||
platform_set_drvdata(pdev, rk808_rtc);
|
||||
- rk808_rtc->rk808 = rk808;
|
||||
+ rk808_rtc->regmap = dev_get_regmap(pdev->dev.parent, NULL);
|
||||
+ if (!rk808_rtc->regmap)
|
||||
+ return -ENODEV;
|
||||
|
||||
/* start rtc running by default, and use shadowed timer. */
|
||||
- ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
+ ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
|
||||
BIT_RTC_CTRL_REG_STOP_RTC_M |
|
||||
BIT_RTC_CTRL_REG_RTC_READSEL_M,
|
||||
BIT_RTC_CTRL_REG_RTC_READSEL_M);
|
||||
@@ -417,7 +410,7 @@ static int rk808_rtc_probe(struct platfo
|
||||
return ret;
|
||||
}
|
||||
|
||||
- ret = regmap_write(rk808->regmap, rk808_rtc->creg->status_reg,
|
||||
+ ret = regmap_write(rk808_rtc->regmap, rk808_rtc->creg->status_reg,
|
||||
RTC_STATUS_MASK);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
@ -1,132 +0,0 @@
|
||||
From 2dc51ca822e4633e244e7f7bdc51e76a77dca939 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:05 +0200
|
||||
Subject: [PATCH] clk: RK808: Reduce 'struct rk808' usage
|
||||
|
||||
Reduce usage of 'struct rk808' (driver data of the parent MFD), so
|
||||
that only the chip variant field is still being accessed directly.
|
||||
This allows restructuring the MFD driver to support SPI based
|
||||
PMICs.
|
||||
|
||||
Acked-by: Stephen Boyd <sboyd@kernel.org>
|
||||
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-2-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/clk/clk-rk808.c | 34 ++++++++++++++++------------------
|
||||
1 file changed, 16 insertions(+), 18 deletions(-)
|
||||
|
||||
--- a/drivers/clk/clk-rk808.c
|
||||
+++ b/drivers/clk/clk-rk808.c
|
||||
@@ -12,10 +12,9 @@
|
||||
#include <linux/slab.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mfd/rk808.h>
|
||||
-#include <linux/i2c.h>
|
||||
|
||||
struct rk808_clkout {
|
||||
- struct rk808 *rk808;
|
||||
+ struct regmap *regmap;
|
||||
struct clk_hw clkout1_hw;
|
||||
struct clk_hw clkout2_hw;
|
||||
};
|
||||
@@ -31,9 +30,8 @@ static int rk808_clkout2_enable(struct c
|
||||
struct rk808_clkout *rk808_clkout = container_of(hw,
|
||||
struct rk808_clkout,
|
||||
clkout2_hw);
|
||||
- struct rk808 *rk808 = rk808_clkout->rk808;
|
||||
|
||||
- return regmap_update_bits(rk808->regmap, RK808_CLK32OUT_REG,
|
||||
+ return regmap_update_bits(rk808_clkout->regmap, RK808_CLK32OUT_REG,
|
||||
CLK32KOUT2_EN, enable ? CLK32KOUT2_EN : 0);
|
||||
}
|
||||
|
||||
@@ -52,10 +50,9 @@ static int rk808_clkout2_is_prepared(str
|
||||
struct rk808_clkout *rk808_clkout = container_of(hw,
|
||||
struct rk808_clkout,
|
||||
clkout2_hw);
|
||||
- struct rk808 *rk808 = rk808_clkout->rk808;
|
||||
uint32_t val;
|
||||
|
||||
- int ret = regmap_read(rk808->regmap, RK808_CLK32OUT_REG, &val);
|
||||
+ int ret = regmap_read(rk808_clkout->regmap, RK808_CLK32OUT_REG, &val);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
@@ -93,9 +90,8 @@ static int rk817_clkout2_enable(struct c
|
||||
struct rk808_clkout *rk808_clkout = container_of(hw,
|
||||
struct rk808_clkout,
|
||||
clkout2_hw);
|
||||
- struct rk808 *rk808 = rk808_clkout->rk808;
|
||||
|
||||
- return regmap_update_bits(rk808->regmap, RK817_SYS_CFG(1),
|
||||
+ return regmap_update_bits(rk808_clkout->regmap, RK817_SYS_CFG(1),
|
||||
RK817_CLK32KOUT2_EN,
|
||||
enable ? RK817_CLK32KOUT2_EN : 0);
|
||||
}
|
||||
@@ -115,10 +111,9 @@ static int rk817_clkout2_is_prepared(str
|
||||
struct rk808_clkout *rk808_clkout = container_of(hw,
|
||||
struct rk808_clkout,
|
||||
clkout2_hw);
|
||||
- struct rk808 *rk808 = rk808_clkout->rk808;
|
||||
unsigned int val;
|
||||
|
||||
- int ret = regmap_read(rk808->regmap, RK817_SYS_CFG(1), &val);
|
||||
+ int ret = regmap_read(rk808_clkout->regmap, RK817_SYS_CFG(1), &val);
|
||||
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
@@ -153,18 +148,21 @@ static const struct clk_ops *rkpmic_get_
|
||||
static int rk808_clkout_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
|
||||
- struct i2c_client *client = rk808->i2c;
|
||||
- struct device_node *node = client->dev.of_node;
|
||||
+ struct device *dev = &pdev->dev;
|
||||
struct clk_init_data init = {};
|
||||
struct rk808_clkout *rk808_clkout;
|
||||
int ret;
|
||||
|
||||
- rk808_clkout = devm_kzalloc(&client->dev,
|
||||
+ dev->of_node = pdev->dev.parent->of_node;
|
||||
+
|
||||
+ rk808_clkout = devm_kzalloc(dev,
|
||||
sizeof(*rk808_clkout), GFP_KERNEL);
|
||||
if (!rk808_clkout)
|
||||
return -ENOMEM;
|
||||
|
||||
- rk808_clkout->rk808 = rk808;
|
||||
+ rk808_clkout->regmap = dev_get_regmap(pdev->dev.parent, NULL);
|
||||
+ if (!rk808_clkout->regmap)
|
||||
+ return -ENODEV;
|
||||
|
||||
init.parent_names = NULL;
|
||||
init.num_parents = 0;
|
||||
@@ -173,10 +171,10 @@ static int rk808_clkout_probe(struct pla
|
||||
rk808_clkout->clkout1_hw.init = &init;
|
||||
|
||||
/* optional override of the clockname */
|
||||
- of_property_read_string_index(node, "clock-output-names",
|
||||
+ of_property_read_string_index(dev->of_node, "clock-output-names",
|
||||
0, &init.name);
|
||||
|
||||
- ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout1_hw);
|
||||
+ ret = devm_clk_hw_register(dev, &rk808_clkout->clkout1_hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@@ -185,10 +183,10 @@ static int rk808_clkout_probe(struct pla
|
||||
rk808_clkout->clkout2_hw.init = &init;
|
||||
|
||||
/* optional override of the clockname */
|
||||
- of_property_read_string_index(node, "clock-output-names",
|
||||
+ of_property_read_string_index(dev->of_node, "clock-output-names",
|
||||
1, &init.name);
|
||||
|
||||
- ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout2_hw);
|
||||
+ ret = devm_clk_hw_register(dev, &rk808_clkout->clkout2_hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
@ -1,151 +0,0 @@
|
||||
From 4fec8a5a85c495851007084e632b7f3f87cb7bdb Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:06 +0200
|
||||
Subject: [PATCH] mfd: rk808: Convert to device managed resources
|
||||
|
||||
Fully convert the driver to device managed resources.
|
||||
|
||||
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-3-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/rk808.c | 64 ++++++++++++++++-----------------------------
|
||||
1 file changed, 22 insertions(+), 42 deletions(-)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -548,13 +548,11 @@ static const struct regmap_irq_chip rk81
|
||||
.init_ack_masked = true,
|
||||
};
|
||||
|
||||
-static struct i2c_client *rk808_i2c_client;
|
||||
-
|
||||
-static void rk808_pm_power_off(void)
|
||||
+static int rk808_power_off(struct sys_off_data *data)
|
||||
{
|
||||
+ struct rk808 *rk808 = data->cb_data;
|
||||
int ret;
|
||||
unsigned int reg, bit;
|
||||
- struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
|
||||
|
||||
switch (rk808->variant) {
|
||||
case RK805_ID:
|
||||
@@ -575,16 +573,18 @@ static void rk808_pm_power_off(void)
|
||||
bit = DEV_OFF;
|
||||
break;
|
||||
default:
|
||||
- return;
|
||||
+ return NOTIFY_DONE;
|
||||
}
|
||||
ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
|
||||
if (ret)
|
||||
- dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
|
||||
+ dev_err(&rk808->i2c->dev, "Failed to shutdown device!\n");
|
||||
+
|
||||
+ return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
-static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd)
|
||||
+static int rk808_restart(struct sys_off_data *data)
|
||||
{
|
||||
- struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
|
||||
+ struct rk808 *rk808 = data->cb_data;
|
||||
unsigned int reg, bit;
|
||||
int ret;
|
||||
|
||||
@@ -600,16 +600,11 @@ static int rk808_restart_notify(struct n
|
||||
}
|
||||
ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
|
||||
if (ret)
|
||||
- dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n");
|
||||
+ dev_err(&rk808->i2c->dev, "Failed to restart device!\n");
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
-static struct notifier_block rk808_restart_handler = {
|
||||
- .notifier_call = rk808_restart_notify,
|
||||
- .priority = 192,
|
||||
-};
|
||||
-
|
||||
static void rk8xx_shutdown(struct i2c_client *client)
|
||||
{
|
||||
struct rk808 *rk808 = i2c_get_clientdata(client);
|
||||
@@ -745,9 +740,9 @@ static int rk808_probe(struct i2c_client
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- ret = regmap_add_irq_chip(rk808->regmap, client->irq,
|
||||
- IRQF_ONESHOT, -1,
|
||||
- rk808->regmap_irq_chip, &rk808->irq_data);
|
||||
+ ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq,
|
||||
+ IRQF_ONESHOT, -1,
|
||||
+ rk808->regmap_irq_chip, &rk808->irq_data);
|
||||
if (ret) {
|
||||
dev_err(&client->dev, "Failed to add irq_chip %d\n", ret);
|
||||
return ret;
|
||||
@@ -771,17 +766,23 @@ static int rk808_probe(struct i2c_client
|
||||
regmap_irq_get_domain(rk808->irq_data));
|
||||
if (ret) {
|
||||
dev_err(&client->dev, "failed to add MFD devices %d\n", ret);
|
||||
- goto err_irq;
|
||||
+ return ret;
|
||||
}
|
||||
|
||||
if (of_property_read_bool(np, "rockchip,system-power-controller")) {
|
||||
- rk808_i2c_client = client;
|
||||
- pm_power_off = rk808_pm_power_off;
|
||||
+ ret = devm_register_sys_off_handler(&client->dev,
|
||||
+ SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
|
||||
+ &rk808_power_off, rk808);
|
||||
+ if (ret)
|
||||
+ return dev_err_probe(&client->dev, ret,
|
||||
+ "failed to register poweroff handler\n");
|
||||
|
||||
switch (rk808->variant) {
|
||||
case RK809_ID:
|
||||
case RK817_ID:
|
||||
- ret = register_restart_handler(&rk808_restart_handler);
|
||||
+ ret = devm_register_sys_off_handler(&client->dev,
|
||||
+ SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
|
||||
+ &rk808_restart, rk808);
|
||||
if (ret)
|
||||
dev_warn(&client->dev, "failed to register rst handler, %d\n", ret);
|
||||
break;
|
||||
@@ -792,26 +793,6 @@ static int rk808_probe(struct i2c_client
|
||||
}
|
||||
|
||||
return 0;
|
||||
-
|
||||
-err_irq:
|
||||
- regmap_del_irq_chip(client->irq, rk808->irq_data);
|
||||
- return ret;
|
||||
-}
|
||||
-
|
||||
-static void rk808_remove(struct i2c_client *client)
|
||||
-{
|
||||
- struct rk808 *rk808 = i2c_get_clientdata(client);
|
||||
-
|
||||
- regmap_del_irq_chip(client->irq, rk808->irq_data);
|
||||
-
|
||||
- /**
|
||||
- * pm_power_off may points to a function from another module.
|
||||
- * Check if the pointer is set by us and only then overwrite it.
|
||||
- */
|
||||
- if (pm_power_off == rk808_pm_power_off)
|
||||
- pm_power_off = NULL;
|
||||
-
|
||||
- unregister_restart_handler(&rk808_restart_handler);
|
||||
}
|
||||
|
||||
static int __maybe_unused rk8xx_suspend(struct device *dev)
|
||||
@@ -868,7 +849,6 @@ static struct i2c_driver rk808_i2c_drive
|
||||
.pm = &rk8xx_pm_ops,
|
||||
},
|
||||
.probe_new = rk808_probe,
|
||||
- .remove = rk808_remove,
|
||||
.shutdown = rk8xx_shutdown,
|
||||
};
|
||||
|
||||
@ -1,103 +0,0 @@
|
||||
From e714b50bdf3cf45076c601276e9e3da00ea05319 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:07 +0200
|
||||
Subject: [PATCH] mfd: rk808: Use dev_err_probe
|
||||
|
||||
Use dev_err_probe instead of dev_err in probe function,
|
||||
which simplifies code a little bit and prints the error
|
||||
code.
|
||||
|
||||
Also drop possibly incorrect printing of chip id registers
|
||||
while touching the error message.
|
||||
|
||||
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-4-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/rk808.c | 48 +++++++++++++++------------------------------
|
||||
1 file changed, 16 insertions(+), 32 deletions(-)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -670,18 +670,12 @@ static int rk808_probe(struct i2c_client
|
||||
|
||||
/* Read chip variant */
|
||||
msb = i2c_smbus_read_byte_data(client, pmic_id_msb);
|
||||
- if (msb < 0) {
|
||||
- dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
|
||||
- RK808_ID_MSB);
|
||||
- return msb;
|
||||
- }
|
||||
+ if (msb < 0)
|
||||
+ return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n");
|
||||
|
||||
lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb);
|
||||
- if (lsb < 0) {
|
||||
- dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
|
||||
- RK808_ID_LSB);
|
||||
- return lsb;
|
||||
- }
|
||||
+ if (lsb < 0)
|
||||
+ return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n");
|
||||
|
||||
rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
|
||||
dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant);
|
||||
@@ -730,44 +724,34 @@ static int rk808_probe(struct i2c_client
|
||||
i2c_set_clientdata(client, rk808);
|
||||
|
||||
rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg);
|
||||
- if (IS_ERR(rk808->regmap)) {
|
||||
- dev_err(&client->dev, "regmap initialization failed\n");
|
||||
- return PTR_ERR(rk808->regmap);
|
||||
- }
|
||||
+ if (IS_ERR(rk808->regmap))
|
||||
+ return dev_err_probe(&client->dev, PTR_ERR(rk808->regmap),
|
||||
+ "regmap initialization failed\n");
|
||||
|
||||
- if (!client->irq) {
|
||||
- dev_err(&client->dev, "No interrupt support, no core IRQ\n");
|
||||
- return -EINVAL;
|
||||
- }
|
||||
+ if (!client->irq)
|
||||
+ return dev_err_probe(&client->dev, -EINVAL, "No interrupt support, no core IRQ\n");
|
||||
|
||||
ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq,
|
||||
IRQF_ONESHOT, -1,
|
||||
rk808->regmap_irq_chip, &rk808->irq_data);
|
||||
- if (ret) {
|
||||
- dev_err(&client->dev, "Failed to add irq_chip %d\n", ret);
|
||||
- return ret;
|
||||
- }
|
||||
+ if (ret)
|
||||
+ return dev_err_probe(&client->dev, ret, "Failed to add irq_chip\n");
|
||||
|
||||
for (i = 0; i < nr_pre_init_regs; i++) {
|
||||
ret = regmap_update_bits(rk808->regmap,
|
||||
pre_init_reg[i].addr,
|
||||
pre_init_reg[i].mask,
|
||||
pre_init_reg[i].value);
|
||||
- if (ret) {
|
||||
- dev_err(&client->dev,
|
||||
- "0x%x write err\n",
|
||||
- pre_init_reg[i].addr);
|
||||
- return ret;
|
||||
- }
|
||||
+ if (ret)
|
||||
+ return dev_err_probe(&client->dev, ret, "0x%x write err\n",
|
||||
+ pre_init_reg[i].addr);
|
||||
}
|
||||
|
||||
ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE,
|
||||
cells, nr_cells, NULL, 0,
|
||||
regmap_irq_get_domain(rk808->irq_data));
|
||||
- if (ret) {
|
||||
- dev_err(&client->dev, "failed to add MFD devices %d\n", ret);
|
||||
- return ret;
|
||||
- }
|
||||
+ if (ret)
|
||||
+ return dev_err_probe(&client->dev, ret, "failed to add MFD devices\n");
|
||||
|
||||
if (of_property_read_bool(np, "rockchip,system-power-controller")) {
|
||||
ret = devm_register_sys_off_handler(&client->dev,
|
||||
@ -1,59 +0,0 @@
|
||||
From 049449976f549605a6913d468b61356a9950a6a2 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:08 +0200
|
||||
Subject: [PATCH] mfd: rk808: Replace 'struct i2c_client' with 'struct device'
|
||||
|
||||
Put 'struct device' pointer into the MFD platform_data instead
|
||||
of the 'struct i2c_client' pointer. This simplifies the code
|
||||
and prepares the MFD for SPI support.
|
||||
|
||||
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-5-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/rk808.c | 6 +++---
|
||||
include/linux/mfd/rk808.h | 2 +-
|
||||
2 files changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/mfd/rk808.c
|
||||
+++ b/drivers/mfd/rk808.c
|
||||
@@ -577,7 +577,7 @@ static int rk808_power_off(struct sys_of
|
||||
}
|
||||
ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
|
||||
if (ret)
|
||||
- dev_err(&rk808->i2c->dev, "Failed to shutdown device!\n");
|
||||
+ dev_err(rk808->dev, "Failed to shutdown device!\n");
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
@@ -600,7 +600,7 @@ static int rk808_restart(struct sys_off_
|
||||
}
|
||||
ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
|
||||
if (ret)
|
||||
- dev_err(&rk808->i2c->dev, "Failed to restart device!\n");
|
||||
+ dev_err(rk808->dev, "Failed to restart device!\n");
|
||||
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
@@ -720,7 +720,7 @@ static int rk808_probe(struct i2c_client
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- rk808->i2c = client;
|
||||
+ rk808->dev = &client->dev;
|
||||
i2c_set_clientdata(client, rk808);
|
||||
|
||||
rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg);
|
||||
--- a/include/linux/mfd/rk808.h
|
||||
+++ b/include/linux/mfd/rk808.h
|
||||
@@ -787,7 +787,7 @@ enum {
|
||||
};
|
||||
|
||||
struct rk808 {
|
||||
- struct i2c_client *i2c;
|
||||
+ struct device *dev;
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
struct regmap *regmap;
|
||||
long variant;
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,158 +0,0 @@
|
||||
From 74413bd611b4fd21fdf90e369780b2f8543447a4 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:10 +0200
|
||||
Subject: [PATCH] mfd: rk8xx-i2c: Use device_get_match_data
|
||||
|
||||
Simplify the device identification logic by supplying the relevant
|
||||
information via of_match_data. This also removes the dev_info()
|
||||
printing the chip version, since that's supplied by the match data
|
||||
now.
|
||||
|
||||
Due to lack of hardware this change is compile-tested only.
|
||||
|
||||
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-7-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/rk8xx-core.c | 2 -
|
||||
drivers/mfd/rk8xx-i2c.c | 89 +++++++++++++++++-----------------------
|
||||
2 files changed, 37 insertions(+), 54 deletions(-)
|
||||
|
||||
--- a/drivers/mfd/rk8xx-core.c
|
||||
+++ b/drivers/mfd/rk8xx-core.c
|
||||
@@ -597,8 +597,6 @@ int rk8xx_probe(struct device *dev, int
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- dev_info(dev, "chip id: 0x%x\n", (unsigned int)rk808->variant);
|
||||
-
|
||||
if (!irq)
|
||||
return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n");
|
||||
|
||||
--- a/drivers/mfd/rk8xx-i2c.c
|
||||
+++ b/drivers/mfd/rk8xx-i2c.c
|
||||
@@ -16,6 +16,11 @@
|
||||
#include <linux/of.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
+struct rk8xx_i2c_platform_data {
|
||||
+ const struct regmap_config *regmap_cfg;
|
||||
+ int variant;
|
||||
+};
|
||||
+
|
||||
static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg)
|
||||
{
|
||||
/*
|
||||
@@ -103,66 +108,46 @@ static const struct regmap_config rk817_
|
||||
.volatile_reg = rk817_is_volatile_reg,
|
||||
};
|
||||
|
||||
-static int rk8xx_i2c_get_variant(struct i2c_client *client)
|
||||
-{
|
||||
- u8 pmic_id_msb, pmic_id_lsb;
|
||||
- int msb, lsb;
|
||||
+static const struct rk8xx_i2c_platform_data rk805_data = {
|
||||
+ .regmap_cfg = &rk805_regmap_config,
|
||||
+ .variant = RK805_ID,
|
||||
+};
|
||||
|
||||
- if (of_device_is_compatible(client->dev.of_node, "rockchip,rk817") ||
|
||||
- of_device_is_compatible(client->dev.of_node, "rockchip,rk809")) {
|
||||
- pmic_id_msb = RK817_ID_MSB;
|
||||
- pmic_id_lsb = RK817_ID_LSB;
|
||||
- } else {
|
||||
- pmic_id_msb = RK808_ID_MSB;
|
||||
- pmic_id_lsb = RK808_ID_LSB;
|
||||
- }
|
||||
+static const struct rk8xx_i2c_platform_data rk808_data = {
|
||||
+ .regmap_cfg = &rk808_regmap_config,
|
||||
+ .variant = RK808_ID,
|
||||
+};
|
||||
|
||||
- /* Read chip variant */
|
||||
- msb = i2c_smbus_read_byte_data(client, pmic_id_msb);
|
||||
- if (msb < 0)
|
||||
- return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n");
|
||||
-
|
||||
- lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb);
|
||||
- if (lsb < 0)
|
||||
- return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n");
|
||||
+static const struct rk8xx_i2c_platform_data rk809_data = {
|
||||
+ .regmap_cfg = &rk817_regmap_config,
|
||||
+ .variant = RK809_ID,
|
||||
+};
|
||||
|
||||
- return ((msb << 8) | lsb) & RK8XX_ID_MSK;
|
||||
-}
|
||||
+static const struct rk8xx_i2c_platform_data rk817_data = {
|
||||
+ .regmap_cfg = &rk817_regmap_config,
|
||||
+ .variant = RK817_ID,
|
||||
+};
|
||||
+
|
||||
+static const struct rk8xx_i2c_platform_data rk818_data = {
|
||||
+ .regmap_cfg = &rk818_regmap_config,
|
||||
+ .variant = RK818_ID,
|
||||
+};
|
||||
|
||||
static int rk8xx_i2c_probe(struct i2c_client *client)
|
||||
{
|
||||
- const struct regmap_config *regmap_cfg;
|
||||
+ const struct rk8xx_i2c_platform_data *data;
|
||||
struct regmap *regmap;
|
||||
- int variant;
|
||||
|
||||
- variant = rk8xx_i2c_get_variant(client);
|
||||
- if (variant < 0)
|
||||
- return variant;
|
||||
-
|
||||
- switch (variant) {
|
||||
- case RK805_ID:
|
||||
- regmap_cfg = &rk805_regmap_config;
|
||||
- break;
|
||||
- case RK808_ID:
|
||||
- regmap_cfg = &rk808_regmap_config;
|
||||
- break;
|
||||
- case RK818_ID:
|
||||
- regmap_cfg = &rk818_regmap_config;
|
||||
- break;
|
||||
- case RK809_ID:
|
||||
- case RK817_ID:
|
||||
- regmap_cfg = &rk817_regmap_config;
|
||||
- break;
|
||||
- default:
|
||||
- return dev_err_probe(&client->dev, -EINVAL, "Unsupported RK8XX ID %x\n", variant);
|
||||
- }
|
||||
+ data = device_get_match_data(&client->dev);
|
||||
+ if (!data)
|
||||
+ return -ENODEV;
|
||||
|
||||
- regmap = devm_regmap_init_i2c(client, regmap_cfg);
|
||||
+ regmap = devm_regmap_init_i2c(client, data->regmap_cfg);
|
||||
if (IS_ERR(regmap))
|
||||
return dev_err_probe(&client->dev, PTR_ERR(regmap),
|
||||
"regmap initialization failed\n");
|
||||
|
||||
- return rk8xx_probe(&client->dev, variant, client->irq, regmap);
|
||||
+ return rk8xx_probe(&client->dev, data->variant, client->irq, regmap);
|
||||
}
|
||||
|
||||
static void rk8xx_i2c_shutdown(struct i2c_client *client)
|
||||
@@ -173,11 +158,11 @@ static void rk8xx_i2c_shutdown(struct i2
|
||||
static SIMPLE_DEV_PM_OPS(rk8xx_i2c_pm_ops, rk8xx_suspend, rk8xx_resume);
|
||||
|
||||
static const struct of_device_id rk8xx_i2c_of_match[] = {
|
||||
- { .compatible = "rockchip,rk805" },
|
||||
- { .compatible = "rockchip,rk808" },
|
||||
- { .compatible = "rockchip,rk809" },
|
||||
- { .compatible = "rockchip,rk817" },
|
||||
- { .compatible = "rockchip,rk818" },
|
||||
+ { .compatible = "rockchip,rk805", .data = &rk805_data },
|
||||
+ { .compatible = "rockchip,rk808", .data = &rk808_data },
|
||||
+ { .compatible = "rockchip,rk809", .data = &rk809_data },
|
||||
+ { .compatible = "rockchip,rk817", .data = &rk817_data },
|
||||
+ { .compatible = "rockchip,rk818", .data = &rk818_data },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rk8xx_i2c_of_match);
|
||||
@ -1,743 +0,0 @@
|
||||
From 210f418f8ace9f056c337f7945e0ae3e242b3389 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:12 +0200
|
||||
Subject: [PATCH] mfd: rk8xx: Add rk806 support
|
||||
|
||||
Add support for SPI connected rk806, which is used by the RK3588
|
||||
evaluation boards. The PMIC is advertised to support I2C and SPI,
|
||||
but the evaluation boards all use SPI. Thus only SPI support is
|
||||
added here.
|
||||
|
||||
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-9-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/Kconfig | 14 ++
|
||||
drivers/mfd/Makefile | 1 +
|
||||
drivers/mfd/rk8xx-core.c | 69 ++++++-
|
||||
drivers/mfd/rk8xx-spi.c | 124 ++++++++++++
|
||||
include/linux/mfd/rk808.h | 409 ++++++++++++++++++++++++++++++++++++++
|
||||
5 files changed, 614 insertions(+), 3 deletions(-)
|
||||
create mode 100644 drivers/mfd/rk8xx-spi.c
|
||||
|
||||
--- a/drivers/mfd/Kconfig
|
||||
+++ b/drivers/mfd/Kconfig
|
||||
@@ -1220,6 +1220,20 @@ config MFD_RK8XX_I2C
|
||||
through I2C interface. The device supports multiple sub-devices
|
||||
including interrupts, RTC, LDO & DCDC regulators, and onkey.
|
||||
|
||||
+config MFD_RK8XX_SPI
|
||||
+ tristate "Rockchip RK806 Power Management Chip"
|
||||
+ depends on SPI && OF
|
||||
+ select MFD_CORE
|
||||
+ select REGMAP_SPI
|
||||
+ select REGMAP_IRQ
|
||||
+ select MFD_RK8XX
|
||||
+ help
|
||||
+ If you say yes here you get support for the RK806 Power Management
|
||||
+ chip.
|
||||
+ This driver provides common support for accessing the device
|
||||
+ through an SPI interface. The device supports multiple sub-devices
|
||||
+ including interrupts, LDO & DCDC regulators, and power on-key.
|
||||
+
|
||||
config MFD_RN5T618
|
||||
tristate "Ricoh RN5T567/618 PMIC"
|
||||
depends on I2C
|
||||
--- a/drivers/mfd/Makefile
|
||||
+++ b/drivers/mfd/Makefile
|
||||
@@ -225,6 +225,7 @@ obj-$(CONFIG_MFD_NTXEC) += ntxec.o
|
||||
obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o
|
||||
obj-$(CONFIG_MFD_RK8XX) += rk8xx-core.o
|
||||
obj-$(CONFIG_MFD_RK8XX_I2C) += rk8xx-i2c.o
|
||||
+obj-$(CONFIG_MFD_RK8XX_SPI) += rk8xx-spi.o
|
||||
obj-$(CONFIG_MFD_RN5T618) += rn5t618.o
|
||||
obj-$(CONFIG_MFD_SEC_CORE) += sec-core.o sec-irq.o
|
||||
obj-$(CONFIG_MFD_SYSCON) += syscon.o
|
||||
--- a/drivers/mfd/rk8xx-core.c
|
||||
+++ b/drivers/mfd/rk8xx-core.c
|
||||
@@ -37,6 +37,11 @@ static const struct resource rk805_key_r
|
||||
DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL),
|
||||
};
|
||||
|
||||
+static struct resource rk806_pwrkey_resources[] = {
|
||||
+ DEFINE_RES_IRQ(RK806_IRQ_PWRON_FALL),
|
||||
+ DEFINE_RES_IRQ(RK806_IRQ_PWRON_RISE),
|
||||
+};
|
||||
+
|
||||
static const struct resource rk817_pwrkey_resources[] = {
|
||||
DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE),
|
||||
DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL),
|
||||
@@ -64,6 +69,17 @@ static const struct mfd_cell rk805s[] =
|
||||
},
|
||||
};
|
||||
|
||||
+static const struct mfd_cell rk806s[] = {
|
||||
+ { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_AUTO, },
|
||||
+ { .name = "rk808-regulator", .id = PLATFORM_DEVID_AUTO, },
|
||||
+ {
|
||||
+ .name = "rk805-pwrkey",
|
||||
+ .resources = rk806_pwrkey_resources,
|
||||
+ .num_resources = ARRAY_SIZE(rk806_pwrkey_resources),
|
||||
+ .id = PLATFORM_DEVID_AUTO,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
static const struct mfd_cell rk808s[] = {
|
||||
{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
|
||||
{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
@@ -123,6 +139,12 @@ static const struct rk808_reg_data rk805
|
||||
{RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C},
|
||||
};
|
||||
|
||||
+static const struct rk808_reg_data rk806_pre_init_reg[] = {
|
||||
+ { RK806_GPIO_INT_CONFIG, RK806_INT_POL_MSK, RK806_INT_POL_L },
|
||||
+ { RK806_SYS_CFG3, RK806_SLAVE_RESTART_FUN_MSK, RK806_SLAVE_RESTART_FUN_EN },
|
||||
+ { RK806_SYS_OPTION, RK806_SYS_ENB2_2M_MSK, RK806_SYS_ENB2_2M_EN },
|
||||
+};
|
||||
+
|
||||
static const struct rk808_reg_data rk808_pre_init_reg[] = {
|
||||
{ RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_150MA },
|
||||
{ RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_200MA },
|
||||
@@ -273,6 +295,27 @@ static const struct regmap_irq rk805_irq
|
||||
},
|
||||
};
|
||||
|
||||
+static const struct regmap_irq rk806_irqs[] = {
|
||||
+ /* INT_STS0 IRQs */
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_PWRON_FALL, 0, RK806_INT_STS_PWRON_FALL),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_PWRON_RISE, 0, RK806_INT_STS_PWRON_RISE),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_PWRON, 0, RK806_INT_STS_PWRON),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_PWRON_LP, 0, RK806_INT_STS_PWRON_LP),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_HOTDIE, 0, RK806_INT_STS_HOTDIE),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_VDC_RISE, 0, RK806_INT_STS_VDC_RISE),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_VDC_FALL, 0, RK806_INT_STS_VDC_FALL),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_VB_LO, 0, RK806_INT_STS_VB_LO),
|
||||
+ /* INT_STS1 IRQs */
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_REV0, 1, RK806_INT_STS_REV0),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_REV1, 1, RK806_INT_STS_REV1),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_REV2, 1, RK806_INT_STS_REV2),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_CRC_ERROR, 1, RK806_INT_STS_CRC_ERROR),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_SLP3_GPIO, 1, RK806_INT_STS_SLP3_GPIO),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_SLP2_GPIO, 1, RK806_INT_STS_SLP2_GPIO),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_SLP1_GPIO, 1, RK806_INT_STS_SLP1_GPIO),
|
||||
+ REGMAP_IRQ_REG(RK806_IRQ_WDT, 1, RK806_INT_STS_WDT),
|
||||
+};
|
||||
+
|
||||
static const struct regmap_irq rk808_irqs[] = {
|
||||
/* INT_STS */
|
||||
[RK808_IRQ_VOUT_LO] = {
|
||||
@@ -423,6 +466,18 @@ static struct regmap_irq_chip rk805_irq_
|
||||
.init_ack_masked = true,
|
||||
};
|
||||
|
||||
+static struct regmap_irq_chip rk806_irq_chip = {
|
||||
+ .name = "rk806",
|
||||
+ .irqs = rk806_irqs,
|
||||
+ .num_irqs = ARRAY_SIZE(rk806_irqs),
|
||||
+ .num_regs = 2,
|
||||
+ .irq_reg_stride = 2,
|
||||
+ .mask_base = RK806_INT_MSK0,
|
||||
+ .status_base = RK806_INT_STS0,
|
||||
+ .ack_base = RK806_INT_STS0,
|
||||
+ .init_ack_masked = true,
|
||||
+};
|
||||
+
|
||||
static const struct regmap_irq_chip rk808_irq_chip = {
|
||||
.name = "rk808",
|
||||
.irqs = rk808_irqs,
|
||||
@@ -549,6 +604,7 @@ int rk8xx_probe(struct device *dev, int
|
||||
struct rk808 *rk808;
|
||||
const struct rk808_reg_data *pre_init_reg;
|
||||
const struct mfd_cell *cells;
|
||||
+ int dual_support = 0;
|
||||
int nr_pre_init_regs;
|
||||
int nr_cells;
|
||||
int ret;
|
||||
@@ -570,6 +626,14 @@ int rk8xx_probe(struct device *dev, int
|
||||
cells = rk805s;
|
||||
nr_cells = ARRAY_SIZE(rk805s);
|
||||
break;
|
||||
+ case RK806_ID:
|
||||
+ rk808->regmap_irq_chip = &rk806_irq_chip;
|
||||
+ pre_init_reg = rk806_pre_init_reg;
|
||||
+ nr_pre_init_regs = ARRAY_SIZE(rk806_pre_init_reg);
|
||||
+ cells = rk806s;
|
||||
+ nr_cells = ARRAY_SIZE(rk806s);
|
||||
+ dual_support = IRQF_SHARED;
|
||||
+ break;
|
||||
case RK808_ID:
|
||||
rk808->regmap_irq_chip = &rk808_irq_chip;
|
||||
pre_init_reg = rk808_pre_init_reg;
|
||||
@@ -601,7 +665,7 @@ int rk8xx_probe(struct device *dev, int
|
||||
return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n");
|
||||
|
||||
ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq,
|
||||
- IRQF_ONESHOT, -1,
|
||||
+ IRQF_ONESHOT | dual_support, -1,
|
||||
rk808->regmap_irq_chip, &rk808->irq_data);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "Failed to add irq_chip\n");
|
||||
@@ -616,8 +680,7 @@ int rk8xx_probe(struct device *dev, int
|
||||
pre_init_reg[i].addr);
|
||||
}
|
||||
|
||||
- ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
|
||||
- cells, nr_cells, NULL, 0,
|
||||
+ ret = devm_mfd_add_devices(dev, 0, cells, nr_cells, NULL, 0,
|
||||
regmap_irq_get_domain(rk808->irq_data));
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to add MFD devices\n");
|
||||
--- /dev/null
|
||||
+++ b/drivers/mfd/rk8xx-spi.c
|
||||
@@ -0,0 +1,124 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+/*
|
||||
+ * Rockchip RK806 Core (SPI) driver
|
||||
+ *
|
||||
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
+ * Copyright (c) 2023 Collabora Ltd.
|
||||
+ *
|
||||
+ * Author: Xu Shengfei <xsf@rock-chips.com>
|
||||
+ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
+ */
|
||||
+
|
||||
+#include <linux/interrupt.h>
|
||||
+#include <linux/mfd/core.h>
|
||||
+#include <linux/mfd/rk808.h>
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/regmap.h>
|
||||
+#include <linux/spi/spi.h>
|
||||
+
|
||||
+#define RK806_ADDR_SIZE 2
|
||||
+#define RK806_CMD_WITH_SIZE(CMD, VALUE_BYTES) \
|
||||
+ (RK806_CMD_##CMD | RK806_CMD_CRC_DIS | (VALUE_BYTES - 1))
|
||||
+
|
||||
+static const struct regmap_range rk806_volatile_ranges[] = {
|
||||
+ regmap_reg_range(RK806_POWER_EN0, RK806_POWER_EN5),
|
||||
+ regmap_reg_range(RK806_DVS_START_CTRL, RK806_INT_MSK1),
|
||||
+};
|
||||
+
|
||||
+static const struct regmap_access_table rk806_volatile_table = {
|
||||
+ .yes_ranges = rk806_volatile_ranges,
|
||||
+ .n_yes_ranges = ARRAY_SIZE(rk806_volatile_ranges),
|
||||
+};
|
||||
+
|
||||
+static const struct regmap_config rk806_regmap_config_spi = {
|
||||
+ .reg_bits = 16,
|
||||
+ .val_bits = 8,
|
||||
+ .max_register = RK806_BUCK_RSERVE_REG5,
|
||||
+ .cache_type = REGCACHE_RBTREE,
|
||||
+ .volatile_table = &rk806_volatile_table,
|
||||
+};
|
||||
+
|
||||
+static int rk806_spi_bus_write(void *context, const void *vdata, size_t count)
|
||||
+{
|
||||
+ struct device *dev = context;
|
||||
+ struct spi_device *spi = to_spi_device(dev);
|
||||
+ struct spi_transfer xfer[2] = { 0 };
|
||||
+ /* data and thus count includes the register address */
|
||||
+ size_t val_size = count - RK806_ADDR_SIZE;
|
||||
+ char cmd;
|
||||
+
|
||||
+ if (val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ cmd = RK806_CMD_WITH_SIZE(WRITE, val_size);
|
||||
+
|
||||
+ xfer[0].tx_buf = &cmd;
|
||||
+ xfer[0].len = sizeof(cmd);
|
||||
+ xfer[1].tx_buf = vdata;
|
||||
+ xfer[1].len = count;
|
||||
+
|
||||
+ return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
|
||||
+}
|
||||
+
|
||||
+static int rk806_spi_bus_read(void *context, const void *vreg, size_t reg_size,
|
||||
+ void *val, size_t val_size)
|
||||
+{
|
||||
+ struct device *dev = context;
|
||||
+ struct spi_device *spi = to_spi_device(dev);
|
||||
+ char txbuf[3] = { 0 };
|
||||
+
|
||||
+ if (reg_size != RK806_ADDR_SIZE ||
|
||||
+ val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1))
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ /* TX buffer contains command byte followed by two address bytes */
|
||||
+ txbuf[0] = RK806_CMD_WITH_SIZE(READ, val_size);
|
||||
+ memcpy(txbuf+1, vreg, reg_size);
|
||||
+
|
||||
+ return spi_write_then_read(spi, txbuf, sizeof(txbuf), val, val_size);
|
||||
+}
|
||||
+
|
||||
+static const struct regmap_bus rk806_regmap_bus_spi = {
|
||||
+ .write = rk806_spi_bus_write,
|
||||
+ .read = rk806_spi_bus_read,
|
||||
+ .reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
|
||||
+};
|
||||
+
|
||||
+static int rk8xx_spi_probe(struct spi_device *spi)
|
||||
+{
|
||||
+ struct regmap *regmap;
|
||||
+
|
||||
+ regmap = devm_regmap_init(&spi->dev, &rk806_regmap_bus_spi,
|
||||
+ &spi->dev, &rk806_regmap_config_spi);
|
||||
+ if (IS_ERR(regmap))
|
||||
+ return dev_err_probe(&spi->dev, PTR_ERR(regmap),
|
||||
+ "Failed to init regmap\n");
|
||||
+
|
||||
+ return rk8xx_probe(&spi->dev, RK806_ID, spi->irq, regmap);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id rk8xx_spi_of_match[] = {
|
||||
+ { .compatible = "rockchip,rk806", },
|
||||
+ { }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(of, rk8xx_spi_of_match);
|
||||
+
|
||||
+static const struct spi_device_id rk8xx_spi_id_table[] = {
|
||||
+ { "rk806", 0 },
|
||||
+ { }
|
||||
+};
|
||||
+MODULE_DEVICE_TABLE(spi, rk8xx_spi_id_table);
|
||||
+
|
||||
+static struct spi_driver rk8xx_spi_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "rk8xx-spi",
|
||||
+ .of_match_table = rk8xx_spi_of_match,
|
||||
+ },
|
||||
+ .probe = rk8xx_spi_probe,
|
||||
+ .id_table = rk8xx_spi_id_table,
|
||||
+};
|
||||
+module_spi_driver(rk8xx_spi_driver);
|
||||
+
|
||||
+MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
|
||||
+MODULE_DESCRIPTION("RK8xx SPI PMIC driver");
|
||||
+MODULE_LICENSE("GPL");
|
||||
--- a/include/linux/mfd/rk808.h
|
||||
+++ b/include/linux/mfd/rk808.h
|
||||
@@ -289,6 +289,414 @@ enum rk805_reg {
|
||||
#define RK805_INT_ALARM_EN (1 << 3)
|
||||
#define RK805_INT_TIMER_EN (1 << 2)
|
||||
|
||||
+/* RK806 */
|
||||
+#define RK806_POWER_EN0 0x0
|
||||
+#define RK806_POWER_EN1 0x1
|
||||
+#define RK806_POWER_EN2 0x2
|
||||
+#define RK806_POWER_EN3 0x3
|
||||
+#define RK806_POWER_EN4 0x4
|
||||
+#define RK806_POWER_EN5 0x5
|
||||
+#define RK806_POWER_SLP_EN0 0x6
|
||||
+#define RK806_POWER_SLP_EN1 0x7
|
||||
+#define RK806_POWER_SLP_EN2 0x8
|
||||
+#define RK806_POWER_DISCHRG_EN0 0x9
|
||||
+#define RK806_POWER_DISCHRG_EN1 0xA
|
||||
+#define RK806_POWER_DISCHRG_EN2 0xB
|
||||
+#define RK806_BUCK_FB_CONFIG 0xC
|
||||
+#define RK806_SLP_LP_CONFIG 0xD
|
||||
+#define RK806_POWER_FPWM_EN0 0xE
|
||||
+#define RK806_POWER_FPWM_EN1 0xF
|
||||
+#define RK806_BUCK1_CONFIG 0x10
|
||||
+#define RK806_BUCK2_CONFIG 0x11
|
||||
+#define RK806_BUCK3_CONFIG 0x12
|
||||
+#define RK806_BUCK4_CONFIG 0x13
|
||||
+#define RK806_BUCK5_CONFIG 0x14
|
||||
+#define RK806_BUCK6_CONFIG 0x15
|
||||
+#define RK806_BUCK7_CONFIG 0x16
|
||||
+#define RK806_BUCK8_CONFIG 0x17
|
||||
+#define RK806_BUCK9_CONFIG 0x18
|
||||
+#define RK806_BUCK10_CONFIG 0x19
|
||||
+#define RK806_BUCK1_ON_VSEL 0x1A
|
||||
+#define RK806_BUCK2_ON_VSEL 0x1B
|
||||
+#define RK806_BUCK3_ON_VSEL 0x1C
|
||||
+#define RK806_BUCK4_ON_VSEL 0x1D
|
||||
+#define RK806_BUCK5_ON_VSEL 0x1E
|
||||
+#define RK806_BUCK6_ON_VSEL 0x1F
|
||||
+#define RK806_BUCK7_ON_VSEL 0x20
|
||||
+#define RK806_BUCK8_ON_VSEL 0x21
|
||||
+#define RK806_BUCK9_ON_VSEL 0x22
|
||||
+#define RK806_BUCK10_ON_VSEL 0x23
|
||||
+#define RK806_BUCK1_SLP_VSEL 0x24
|
||||
+#define RK806_BUCK2_SLP_VSEL 0x25
|
||||
+#define RK806_BUCK3_SLP_VSEL 0x26
|
||||
+#define RK806_BUCK4_SLP_VSEL 0x27
|
||||
+#define RK806_BUCK5_SLP_VSEL 0x28
|
||||
+#define RK806_BUCK6_SLP_VSEL 0x29
|
||||
+#define RK806_BUCK7_SLP_VSEL 0x2A
|
||||
+#define RK806_BUCK8_SLP_VSEL 0x2B
|
||||
+#define RK806_BUCK9_SLP_VSEL 0x2D
|
||||
+#define RK806_BUCK10_SLP_VSEL 0x2E
|
||||
+#define RK806_BUCK_DEBUG1 0x30
|
||||
+#define RK806_BUCK_DEBUG2 0x31
|
||||
+#define RK806_BUCK_DEBUG3 0x32
|
||||
+#define RK806_BUCK_DEBUG4 0x33
|
||||
+#define RK806_BUCK_DEBUG5 0x34
|
||||
+#define RK806_BUCK_DEBUG6 0x35
|
||||
+#define RK806_BUCK_DEBUG7 0x36
|
||||
+#define RK806_BUCK_DEBUG8 0x37
|
||||
+#define RK806_BUCK_DEBUG9 0x38
|
||||
+#define RK806_BUCK_DEBUG10 0x39
|
||||
+#define RK806_BUCK_DEBUG11 0x3A
|
||||
+#define RK806_BUCK_DEBUG12 0x3B
|
||||
+#define RK806_BUCK_DEBUG13 0x3C
|
||||
+#define RK806_BUCK_DEBUG14 0x3D
|
||||
+#define RK806_BUCK_DEBUG15 0x3E
|
||||
+#define RK806_BUCK_DEBUG16 0x3F
|
||||
+#define RK806_BUCK_DEBUG17 0x40
|
||||
+#define RK806_BUCK_DEBUG18 0x41
|
||||
+#define RK806_NLDO_IMAX 0x42
|
||||
+#define RK806_NLDO1_ON_VSEL 0x43
|
||||
+#define RK806_NLDO2_ON_VSEL 0x44
|
||||
+#define RK806_NLDO3_ON_VSEL 0x45
|
||||
+#define RK806_NLDO4_ON_VSEL 0x46
|
||||
+#define RK806_NLDO5_ON_VSEL 0x47
|
||||
+#define RK806_NLDO1_SLP_VSEL 0x48
|
||||
+#define RK806_NLDO2_SLP_VSEL 0x49
|
||||
+#define RK806_NLDO3_SLP_VSEL 0x4A
|
||||
+#define RK806_NLDO4_SLP_VSEL 0x4B
|
||||
+#define RK806_NLDO5_SLP_VSEL 0x4C
|
||||
+#define RK806_PLDO_IMAX 0x4D
|
||||
+#define RK806_PLDO1_ON_VSEL 0x4E
|
||||
+#define RK806_PLDO2_ON_VSEL 0x4F
|
||||
+#define RK806_PLDO3_ON_VSEL 0x50
|
||||
+#define RK806_PLDO4_ON_VSEL 0x51
|
||||
+#define RK806_PLDO5_ON_VSEL 0x52
|
||||
+#define RK806_PLDO6_ON_VSEL 0x53
|
||||
+#define RK806_PLDO1_SLP_VSEL 0x54
|
||||
+#define RK806_PLDO2_SLP_VSEL 0x55
|
||||
+#define RK806_PLDO3_SLP_VSEL 0x56
|
||||
+#define RK806_PLDO4_SLP_VSEL 0x57
|
||||
+#define RK806_PLDO5_SLP_VSEL 0x58
|
||||
+#define RK806_PLDO6_SLP_VSEL 0x59
|
||||
+#define RK806_CHIP_NAME 0x5A
|
||||
+#define RK806_CHIP_VER 0x5B
|
||||
+#define RK806_OTP_VER 0x5C
|
||||
+#define RK806_SYS_STS 0x5D
|
||||
+#define RK806_SYS_CFG0 0x5E
|
||||
+#define RK806_SYS_CFG1 0x5F
|
||||
+#define RK806_SYS_OPTION 0x61
|
||||
+#define RK806_SLEEP_CONFIG0 0x62
|
||||
+#define RK806_SLEEP_CONFIG1 0x63
|
||||
+#define RK806_SLEEP_CTR_SEL0 0x64
|
||||
+#define RK806_SLEEP_CTR_SEL1 0x65
|
||||
+#define RK806_SLEEP_CTR_SEL2 0x66
|
||||
+#define RK806_SLEEP_CTR_SEL3 0x67
|
||||
+#define RK806_SLEEP_CTR_SEL4 0x68
|
||||
+#define RK806_SLEEP_CTR_SEL5 0x69
|
||||
+#define RK806_DVS_CTRL_SEL0 0x6A
|
||||
+#define RK806_DVS_CTRL_SEL1 0x6B
|
||||
+#define RK806_DVS_CTRL_SEL2 0x6C
|
||||
+#define RK806_DVS_CTRL_SEL3 0x6D
|
||||
+#define RK806_DVS_CTRL_SEL4 0x6E
|
||||
+#define RK806_DVS_CTRL_SEL5 0x6F
|
||||
+#define RK806_DVS_START_CTRL 0x70
|
||||
+#define RK806_SLEEP_GPIO 0x71
|
||||
+#define RK806_SYS_CFG3 0x72
|
||||
+#define RK806_ON_SOURCE 0x74
|
||||
+#define RK806_OFF_SOURCE 0x75
|
||||
+#define RK806_PWRON_KEY 0x76
|
||||
+#define RK806_INT_STS0 0x77
|
||||
+#define RK806_INT_MSK0 0x78
|
||||
+#define RK806_INT_STS1 0x79
|
||||
+#define RK806_INT_MSK1 0x7A
|
||||
+#define RK806_GPIO_INT_CONFIG 0x7B
|
||||
+#define RK806_DATA_REG0 0x7C
|
||||
+#define RK806_DATA_REG1 0x7D
|
||||
+#define RK806_DATA_REG2 0x7E
|
||||
+#define RK806_DATA_REG3 0x7F
|
||||
+#define RK806_DATA_REG4 0x80
|
||||
+#define RK806_DATA_REG5 0x81
|
||||
+#define RK806_DATA_REG6 0x82
|
||||
+#define RK806_DATA_REG7 0x83
|
||||
+#define RK806_DATA_REG8 0x84
|
||||
+#define RK806_DATA_REG9 0x85
|
||||
+#define RK806_DATA_REG10 0x86
|
||||
+#define RK806_DATA_REG11 0x87
|
||||
+#define RK806_DATA_REG12 0x88
|
||||
+#define RK806_DATA_REG13 0x89
|
||||
+#define RK806_DATA_REG14 0x8A
|
||||
+#define RK806_DATA_REG15 0x8B
|
||||
+#define RK806_TM_REG 0x8C
|
||||
+#define RK806_OTP_EN_REG 0x8D
|
||||
+#define RK806_FUNC_OTP_EN_REG 0x8E
|
||||
+#define RK806_TEST_REG1 0x8F
|
||||
+#define RK806_TEST_REG2 0x90
|
||||
+#define RK806_TEST_REG3 0x91
|
||||
+#define RK806_TEST_REG4 0x92
|
||||
+#define RK806_TEST_REG5 0x93
|
||||
+#define RK806_BUCK_VSEL_OTP_REG0 0x94
|
||||
+#define RK806_BUCK_VSEL_OTP_REG1 0x95
|
||||
+#define RK806_BUCK_VSEL_OTP_REG2 0x96
|
||||
+#define RK806_BUCK_VSEL_OTP_REG3 0x97
|
||||
+#define RK806_BUCK_VSEL_OTP_REG4 0x98
|
||||
+#define RK806_BUCK_VSEL_OTP_REG5 0x99
|
||||
+#define RK806_BUCK_VSEL_OTP_REG6 0x9A
|
||||
+#define RK806_BUCK_VSEL_OTP_REG7 0x9B
|
||||
+#define RK806_BUCK_VSEL_OTP_REG8 0x9C
|
||||
+#define RK806_BUCK_VSEL_OTP_REG9 0x9D
|
||||
+#define RK806_NLDO1_VSEL_OTP_REG0 0x9E
|
||||
+#define RK806_NLDO1_VSEL_OTP_REG1 0x9F
|
||||
+#define RK806_NLDO1_VSEL_OTP_REG2 0xA0
|
||||
+#define RK806_NLDO1_VSEL_OTP_REG3 0xA1
|
||||
+#define RK806_NLDO1_VSEL_OTP_REG4 0xA2
|
||||
+#define RK806_PLDO_VSEL_OTP_REG0 0xA3
|
||||
+#define RK806_PLDO_VSEL_OTP_REG1 0xA4
|
||||
+#define RK806_PLDO_VSEL_OTP_REG2 0xA5
|
||||
+#define RK806_PLDO_VSEL_OTP_REG3 0xA6
|
||||
+#define RK806_PLDO_VSEL_OTP_REG4 0xA7
|
||||
+#define RK806_PLDO_VSEL_OTP_REG5 0xA8
|
||||
+#define RK806_BUCK_EN_OTP_REG1 0xA9
|
||||
+#define RK806_NLDO_EN_OTP_REG1 0xAA
|
||||
+#define RK806_PLDO_EN_OTP_REG1 0xAB
|
||||
+#define RK806_BUCK_FB_RES_OTP_REG1 0xAC
|
||||
+#define RK806_OTP_RESEV_REG0 0xAD
|
||||
+#define RK806_OTP_RESEV_REG1 0xAE
|
||||
+#define RK806_OTP_RESEV_REG2 0xAF
|
||||
+#define RK806_OTP_RESEV_REG3 0xB0
|
||||
+#define RK806_OTP_RESEV_REG4 0xB1
|
||||
+#define RK806_BUCK_SEQ_REG0 0xB2
|
||||
+#define RK806_BUCK_SEQ_REG1 0xB3
|
||||
+#define RK806_BUCK_SEQ_REG2 0xB4
|
||||
+#define RK806_BUCK_SEQ_REG3 0xB5
|
||||
+#define RK806_BUCK_SEQ_REG4 0xB6
|
||||
+#define RK806_BUCK_SEQ_REG5 0xB7
|
||||
+#define RK806_BUCK_SEQ_REG6 0xB8
|
||||
+#define RK806_BUCK_SEQ_REG7 0xB9
|
||||
+#define RK806_BUCK_SEQ_REG8 0xBA
|
||||
+#define RK806_BUCK_SEQ_REG9 0xBB
|
||||
+#define RK806_BUCK_SEQ_REG10 0xBC
|
||||
+#define RK806_BUCK_SEQ_REG11 0xBD
|
||||
+#define RK806_BUCK_SEQ_REG12 0xBE
|
||||
+#define RK806_BUCK_SEQ_REG13 0xBF
|
||||
+#define RK806_BUCK_SEQ_REG14 0xC0
|
||||
+#define RK806_BUCK_SEQ_REG15 0xC1
|
||||
+#define RK806_BUCK_SEQ_REG16 0xC2
|
||||
+#define RK806_BUCK_SEQ_REG17 0xC3
|
||||
+#define RK806_HK_TRIM_REG1 0xC4
|
||||
+#define RK806_HK_TRIM_REG2 0xC5
|
||||
+#define RK806_BUCK_REF_TRIM_REG1 0xC6
|
||||
+#define RK806_BUCK_REF_TRIM_REG2 0xC7
|
||||
+#define RK806_BUCK_REF_TRIM_REG3 0xC8
|
||||
+#define RK806_BUCK_REF_TRIM_REG4 0xC9
|
||||
+#define RK806_BUCK_REF_TRIM_REG5 0xCA
|
||||
+#define RK806_BUCK_OSC_TRIM_REG1 0xCB
|
||||
+#define RK806_BUCK_OSC_TRIM_REG2 0xCC
|
||||
+#define RK806_BUCK_OSC_TRIM_REG3 0xCD
|
||||
+#define RK806_BUCK_OSC_TRIM_REG4 0xCE
|
||||
+#define RK806_BUCK_OSC_TRIM_REG5 0xCF
|
||||
+#define RK806_BUCK_TRIM_ZCDIOS_REG1 0xD0
|
||||
+#define RK806_BUCK_TRIM_ZCDIOS_REG2 0xD1
|
||||
+#define RK806_NLDO_TRIM_REG1 0xD2
|
||||
+#define RK806_NLDO_TRIM_REG2 0xD3
|
||||
+#define RK806_NLDO_TRIM_REG3 0xD4
|
||||
+#define RK806_PLDO_TRIM_REG1 0xD5
|
||||
+#define RK806_PLDO_TRIM_REG2 0xD6
|
||||
+#define RK806_PLDO_TRIM_REG3 0xD7
|
||||
+#define RK806_TRIM_ICOMP_REG1 0xD8
|
||||
+#define RK806_TRIM_ICOMP_REG2 0xD9
|
||||
+#define RK806_EFUSE_CONTROL_REGH 0xDA
|
||||
+#define RK806_FUSE_PROG_REG 0xDB
|
||||
+#define RK806_MAIN_FSM_STS_REG 0xDD
|
||||
+#define RK806_FSM_REG 0xDE
|
||||
+#define RK806_TOP_RESEV_OFFR 0xEC
|
||||
+#define RK806_TOP_RESEV_POR 0xED
|
||||
+#define RK806_BUCK_VRSN_REG1 0xEE
|
||||
+#define RK806_BUCK_VRSN_REG2 0xEF
|
||||
+#define RK806_NLDO_RLOAD_SEL_REG1 0xF0
|
||||
+#define RK806_PLDO_RLOAD_SEL_REG1 0xF1
|
||||
+#define RK806_PLDO_RLOAD_SEL_REG2 0xF2
|
||||
+#define RK806_BUCK_CMIN_MX_REG1 0xF3
|
||||
+#define RK806_BUCK_CMIN_MX_REG2 0xF4
|
||||
+#define RK806_BUCK_FREQ_SET_REG1 0xF5
|
||||
+#define RK806_BUCK_FREQ_SET_REG2 0xF6
|
||||
+#define RK806_BUCK_RS_MEABS_REG1 0xF7
|
||||
+#define RK806_BUCK_RS_MEABS_REG2 0xF8
|
||||
+#define RK806_BUCK_RS_ZDLEB_REG1 0xF9
|
||||
+#define RK806_BUCK_RS_ZDLEB_REG2 0xFA
|
||||
+#define RK806_BUCK_RSERVE_REG1 0xFB
|
||||
+#define RK806_BUCK_RSERVE_REG2 0xFC
|
||||
+#define RK806_BUCK_RSERVE_REG3 0xFD
|
||||
+#define RK806_BUCK_RSERVE_REG4 0xFE
|
||||
+#define RK806_BUCK_RSERVE_REG5 0xFF
|
||||
+
|
||||
+/* INT_STS Register field definitions */
|
||||
+#define RK806_INT_STS_PWRON_FALL BIT(0)
|
||||
+#define RK806_INT_STS_PWRON_RISE BIT(1)
|
||||
+#define RK806_INT_STS_PWRON BIT(2)
|
||||
+#define RK806_INT_STS_PWRON_LP BIT(3)
|
||||
+#define RK806_INT_STS_HOTDIE BIT(4)
|
||||
+#define RK806_INT_STS_VDC_RISE BIT(5)
|
||||
+#define RK806_INT_STS_VDC_FALL BIT(6)
|
||||
+#define RK806_INT_STS_VB_LO BIT(7)
|
||||
+#define RK806_INT_STS_REV0 BIT(0)
|
||||
+#define RK806_INT_STS_REV1 BIT(1)
|
||||
+#define RK806_INT_STS_REV2 BIT(2)
|
||||
+#define RK806_INT_STS_CRC_ERROR BIT(3)
|
||||
+#define RK806_INT_STS_SLP3_GPIO BIT(4)
|
||||
+#define RK806_INT_STS_SLP2_GPIO BIT(5)
|
||||
+#define RK806_INT_STS_SLP1_GPIO BIT(6)
|
||||
+#define RK806_INT_STS_WDT BIT(7)
|
||||
+
|
||||
+/* SPI command */
|
||||
+#define RK806_CMD_READ 0
|
||||
+#define RK806_CMD_WRITE BIT(7)
|
||||
+#define RK806_CMD_CRC_EN BIT(6)
|
||||
+#define RK806_CMD_CRC_DIS 0
|
||||
+#define RK806_CMD_LEN_MSK 0x0f
|
||||
+#define RK806_REG_H 0x00
|
||||
+
|
||||
+#define VERSION_AB 0x01
|
||||
+
|
||||
+enum rk806_reg_id {
|
||||
+ RK806_ID_DCDC1 = 0,
|
||||
+ RK806_ID_DCDC2,
|
||||
+ RK806_ID_DCDC3,
|
||||
+ RK806_ID_DCDC4,
|
||||
+ RK806_ID_DCDC5,
|
||||
+ RK806_ID_DCDC6,
|
||||
+ RK806_ID_DCDC7,
|
||||
+ RK806_ID_DCDC8,
|
||||
+ RK806_ID_DCDC9,
|
||||
+ RK806_ID_DCDC10,
|
||||
+
|
||||
+ RK806_ID_NLDO1,
|
||||
+ RK806_ID_NLDO2,
|
||||
+ RK806_ID_NLDO3,
|
||||
+ RK806_ID_NLDO4,
|
||||
+ RK806_ID_NLDO5,
|
||||
+
|
||||
+ RK806_ID_PLDO1,
|
||||
+ RK806_ID_PLDO2,
|
||||
+ RK806_ID_PLDO3,
|
||||
+ RK806_ID_PLDO4,
|
||||
+ RK806_ID_PLDO5,
|
||||
+ RK806_ID_PLDO6,
|
||||
+ RK806_ID_END,
|
||||
+};
|
||||
+
|
||||
+/* Define the RK806 IRQ numbers */
|
||||
+enum rk806_irqs {
|
||||
+ /* INT_STS0 registers */
|
||||
+ RK806_IRQ_PWRON_FALL,
|
||||
+ RK806_IRQ_PWRON_RISE,
|
||||
+ RK806_IRQ_PWRON,
|
||||
+ RK806_IRQ_PWRON_LP,
|
||||
+ RK806_IRQ_HOTDIE,
|
||||
+ RK806_IRQ_VDC_RISE,
|
||||
+ RK806_IRQ_VDC_FALL,
|
||||
+ RK806_IRQ_VB_LO,
|
||||
+
|
||||
+ /* INT_STS0 registers */
|
||||
+ RK806_IRQ_REV0,
|
||||
+ RK806_IRQ_REV1,
|
||||
+ RK806_IRQ_REV2,
|
||||
+ RK806_IRQ_CRC_ERROR,
|
||||
+ RK806_IRQ_SLP3_GPIO,
|
||||
+ RK806_IRQ_SLP2_GPIO,
|
||||
+ RK806_IRQ_SLP1_GPIO,
|
||||
+ RK806_IRQ_WDT,
|
||||
+};
|
||||
+
|
||||
+/* VCC1 Low Voltage Threshold */
|
||||
+enum rk806_lv_sel {
|
||||
+ VB_LO_SEL_2800,
|
||||
+ VB_LO_SEL_2900,
|
||||
+ VB_LO_SEL_3000,
|
||||
+ VB_LO_SEL_3100,
|
||||
+ VB_LO_SEL_3200,
|
||||
+ VB_LO_SEL_3300,
|
||||
+ VB_LO_SEL_3400,
|
||||
+ VB_LO_SEL_3500,
|
||||
+};
|
||||
+
|
||||
+/* System Shutdown Voltage Select */
|
||||
+enum rk806_uv_sel {
|
||||
+ VB_UV_SEL_2700,
|
||||
+ VB_UV_SEL_2800,
|
||||
+ VB_UV_SEL_2900,
|
||||
+ VB_UV_SEL_3000,
|
||||
+ VB_UV_SEL_3100,
|
||||
+ VB_UV_SEL_3200,
|
||||
+ VB_UV_SEL_3300,
|
||||
+ VB_UV_SEL_3400,
|
||||
+};
|
||||
+
|
||||
+/* Pin Function */
|
||||
+enum rk806_pwrctrl_fun {
|
||||
+ PWRCTRL_NULL_FUN,
|
||||
+ PWRCTRL_SLP_FUN,
|
||||
+ PWRCTRL_POWOFF_FUN,
|
||||
+ PWRCTRL_RST_FUN,
|
||||
+ PWRCTRL_DVS_FUN,
|
||||
+ PWRCTRL_GPIO_FUN,
|
||||
+};
|
||||
+
|
||||
+/* Pin Polarity */
|
||||
+enum rk806_pin_level {
|
||||
+ POL_LOW,
|
||||
+ POL_HIGH,
|
||||
+};
|
||||
+
|
||||
+enum rk806_vsel_ctr_sel {
|
||||
+ CTR_BY_NO_EFFECT,
|
||||
+ CTR_BY_PWRCTRL1,
|
||||
+ CTR_BY_PWRCTRL2,
|
||||
+ CTR_BY_PWRCTRL3,
|
||||
+};
|
||||
+
|
||||
+enum rk806_dvs_ctr_sel {
|
||||
+ CTR_SEL_NO_EFFECT,
|
||||
+ CTR_SEL_DVS_START1,
|
||||
+ CTR_SEL_DVS_START2,
|
||||
+ CTR_SEL_DVS_START3,
|
||||
+};
|
||||
+
|
||||
+enum rk806_pin_dr_sel {
|
||||
+ RK806_PIN_INPUT,
|
||||
+ RK806_PIN_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+#define RK806_INT_POL_MSK BIT(1)
|
||||
+#define RK806_INT_POL_H BIT(1)
|
||||
+#define RK806_INT_POL_L 0
|
||||
+
|
||||
+#define RK806_SLAVE_RESTART_FUN_MSK BIT(1)
|
||||
+#define RK806_SLAVE_RESTART_FUN_EN BIT(1)
|
||||
+#define RK806_SLAVE_RESTART_FUN_OFF 0
|
||||
+
|
||||
+#define RK806_SYS_ENB2_2M_MSK BIT(1)
|
||||
+#define RK806_SYS_ENB2_2M_EN BIT(1)
|
||||
+#define RK806_SYS_ENB2_2M_OFF 0
|
||||
+
|
||||
+enum rk806_int_fun {
|
||||
+ RK806_INT_ONLY,
|
||||
+ RK806_INT_ADN_WKUP,
|
||||
+};
|
||||
+
|
||||
+enum rk806_dvs_mode {
|
||||
+ RK806_DVS_NOT_SUPPORT,
|
||||
+ RK806_DVS_START1,
|
||||
+ RK806_DVS_START2,
|
||||
+ RK806_DVS_START3,
|
||||
+ RK806_DVS_PWRCTRL1,
|
||||
+ RK806_DVS_PWRCTRL2,
|
||||
+ RK806_DVS_PWRCTRL3,
|
||||
+ RK806_DVS_START_PWRCTR1,
|
||||
+ RK806_DVS_START_PWRCTR2,
|
||||
+ RK806_DVS_START_PWRCTR3,
|
||||
+ RK806_DVS_END,
|
||||
+};
|
||||
+
|
||||
/* RK808 IRQ Definitions */
|
||||
#define RK808_IRQ_VOUT_LO 0
|
||||
#define RK808_IRQ_VB_LO 1
|
||||
@@ -780,6 +1188,7 @@ enum {
|
||||
|
||||
enum {
|
||||
RK805_ID = 0x8050,
|
||||
+ RK806_ID = 0x8060,
|
||||
RK808_ID = 0x0000,
|
||||
RK809_ID = 0x8090,
|
||||
RK817_ID = 0x8170,
|
||||
@ -1,338 +0,0 @@
|
||||
From 924764aa5f2e705f46f548611e6a9d6b986ae880 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:13 +0200
|
||||
Subject: [PATCH] pinctrl: rk805: Add rk806 pinctrl support
|
||||
|
||||
Add support for rk806 dvs pinctrl to the existing rk805
|
||||
driver.
|
||||
|
||||
This has been implemented using shengfei Xu's rk806
|
||||
specific driver from the vendor tree as reference.
|
||||
|
||||
Co-developed-by: shengfei Xu <xsf@rock-chips.com>
|
||||
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
|
||||
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
Acked-by: Linus Walleij <linus.walleij@linaro.org>
|
||||
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-10-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/pinctrl/pinctrl-rk805.c | 189 ++++++++++++++++++++++++++++----
|
||||
1 file changed, 168 insertions(+), 21 deletions(-)
|
||||
|
||||
--- a/drivers/pinctrl/pinctrl-rk805.c
|
||||
+++ b/drivers/pinctrl/pinctrl-rk805.c
|
||||
@@ -1,10 +1,12 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
- * Pinctrl driver for Rockchip RK805 PMIC
|
||||
+ * Pinctrl driver for Rockchip RK805/RK806 PMIC
|
||||
*
|
||||
* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
|
||||
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
* Author: Joseph Chen <chenjh@rock-chips.com>
|
||||
+ * Author: Xu Shengfei <xsf@rock-chips.com>
|
||||
*
|
||||
* Based on the pinctrl-as3722 driver
|
||||
*/
|
||||
@@ -44,6 +46,7 @@ struct rk805_pin_group {
|
||||
|
||||
/*
|
||||
* @reg: gpio setting register;
|
||||
+ * @fun_reg: functions select register;
|
||||
* @fun_mask: functions select mask value, when set is gpio;
|
||||
* @dir_mask: input or output mask value, when set is output, otherwise input;
|
||||
* @val_mask: gpio set value, when set is level high, otherwise low;
|
||||
@@ -56,6 +59,7 @@ struct rk805_pin_group {
|
||||
*/
|
||||
struct rk805_pin_config {
|
||||
u8 reg;
|
||||
+ u8 fun_reg;
|
||||
u8 fun_msk;
|
||||
u8 dir_msk;
|
||||
u8 val_msk;
|
||||
@@ -80,22 +84,50 @@ enum rk805_pinmux_option {
|
||||
RK805_PINMUX_GPIO,
|
||||
};
|
||||
|
||||
+enum rk806_pinmux_option {
|
||||
+ RK806_PINMUX_FUN0 = 0,
|
||||
+ RK806_PINMUX_FUN1,
|
||||
+ RK806_PINMUX_FUN2,
|
||||
+ RK806_PINMUX_FUN3,
|
||||
+ RK806_PINMUX_FUN4,
|
||||
+ RK806_PINMUX_FUN5,
|
||||
+};
|
||||
+
|
||||
enum {
|
||||
RK805_GPIO0,
|
||||
RK805_GPIO1,
|
||||
};
|
||||
|
||||
+enum {
|
||||
+ RK806_GPIO_DVS1,
|
||||
+ RK806_GPIO_DVS2,
|
||||
+ RK806_GPIO_DVS3
|
||||
+};
|
||||
+
|
||||
static const char *const rk805_gpio_groups[] = {
|
||||
"gpio0",
|
||||
"gpio1",
|
||||
};
|
||||
|
||||
+static const char *const rk806_gpio_groups[] = {
|
||||
+ "gpio_pwrctrl1",
|
||||
+ "gpio_pwrctrl2",
|
||||
+ "gpio_pwrctrl3",
|
||||
+};
|
||||
+
|
||||
/* RK805: 2 output only GPIOs */
|
||||
static const struct pinctrl_pin_desc rk805_pins_desc[] = {
|
||||
PINCTRL_PIN(RK805_GPIO0, "gpio0"),
|
||||
PINCTRL_PIN(RK805_GPIO1, "gpio1"),
|
||||
};
|
||||
|
||||
+/* RK806 */
|
||||
+static const struct pinctrl_pin_desc rk806_pins_desc[] = {
|
||||
+ PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"),
|
||||
+ PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"),
|
||||
+ PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"),
|
||||
+};
|
||||
+
|
||||
static const struct rk805_pin_function rk805_pin_functions[] = {
|
||||
{
|
||||
.name = "gpio",
|
||||
@@ -105,6 +137,45 @@ static const struct rk805_pin_function r
|
||||
},
|
||||
};
|
||||
|
||||
+static const struct rk805_pin_function rk806_pin_functions[] = {
|
||||
+ {
|
||||
+ .name = "pin_fun0",
|
||||
+ .groups = rk806_gpio_groups,
|
||||
+ .ngroups = ARRAY_SIZE(rk806_gpio_groups),
|
||||
+ .mux_option = RK806_PINMUX_FUN0,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "pin_fun1",
|
||||
+ .groups = rk806_gpio_groups,
|
||||
+ .ngroups = ARRAY_SIZE(rk806_gpio_groups),
|
||||
+ .mux_option = RK806_PINMUX_FUN1,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "pin_fun2",
|
||||
+ .groups = rk806_gpio_groups,
|
||||
+ .ngroups = ARRAY_SIZE(rk806_gpio_groups),
|
||||
+ .mux_option = RK806_PINMUX_FUN2,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "pin_fun3",
|
||||
+ .groups = rk806_gpio_groups,
|
||||
+ .ngroups = ARRAY_SIZE(rk806_gpio_groups),
|
||||
+ .mux_option = RK806_PINMUX_FUN3,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "pin_fun4",
|
||||
+ .groups = rk806_gpio_groups,
|
||||
+ .ngroups = ARRAY_SIZE(rk806_gpio_groups),
|
||||
+ .mux_option = RK806_PINMUX_FUN4,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "pin_fun5",
|
||||
+ .groups = rk806_gpio_groups,
|
||||
+ .ngroups = ARRAY_SIZE(rk806_gpio_groups),
|
||||
+ .mux_option = RK806_PINMUX_FUN5,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
static const struct rk805_pin_group rk805_pin_groups[] = {
|
||||
{
|
||||
.name = "gpio0",
|
||||
@@ -118,6 +189,24 @@ static const struct rk805_pin_group rk80
|
||||
},
|
||||
};
|
||||
|
||||
+static const struct rk805_pin_group rk806_pin_groups[] = {
|
||||
+ {
|
||||
+ .name = "gpio_pwrctrl1",
|
||||
+ .pins = { RK806_GPIO_DVS1 },
|
||||
+ .npins = 1,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "gpio_pwrctrl2",
|
||||
+ .pins = { RK806_GPIO_DVS2 },
|
||||
+ .npins = 1,
|
||||
+ },
|
||||
+ {
|
||||
+ .name = "gpio_pwrctrl3",
|
||||
+ .pins = { RK806_GPIO_DVS3 },
|
||||
+ .npins = 1,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
#define RK805_GPIO0_VAL_MSK BIT(0)
|
||||
#define RK805_GPIO1_VAL_MSK BIT(1)
|
||||
|
||||
@@ -132,6 +221,40 @@ static const struct rk805_pin_config rk8
|
||||
},
|
||||
};
|
||||
|
||||
+#define RK806_PWRCTRL1_DR BIT(0)
|
||||
+#define RK806_PWRCTRL2_DR BIT(1)
|
||||
+#define RK806_PWRCTRL3_DR BIT(2)
|
||||
+#define RK806_PWRCTRL1_DATA BIT(4)
|
||||
+#define RK806_PWRCTRL2_DATA BIT(5)
|
||||
+#define RK806_PWRCTRL3_DATA BIT(6)
|
||||
+#define RK806_PWRCTRL1_FUN GENMASK(2, 0)
|
||||
+#define RK806_PWRCTRL2_FUN GENMASK(6, 4)
|
||||
+#define RK806_PWRCTRL3_FUN GENMASK(2, 0)
|
||||
+
|
||||
+static struct rk805_pin_config rk806_gpio_cfgs[] = {
|
||||
+ {
|
||||
+ .fun_reg = RK806_SLEEP_CONFIG0,
|
||||
+ .fun_msk = RK806_PWRCTRL1_FUN,
|
||||
+ .reg = RK806_SLEEP_GPIO,
|
||||
+ .val_msk = RK806_PWRCTRL1_DATA,
|
||||
+ .dir_msk = RK806_PWRCTRL1_DR,
|
||||
+ },
|
||||
+ {
|
||||
+ .fun_reg = RK806_SLEEP_CONFIG0,
|
||||
+ .fun_msk = RK806_PWRCTRL2_FUN,
|
||||
+ .reg = RK806_SLEEP_GPIO,
|
||||
+ .val_msk = RK806_PWRCTRL2_DATA,
|
||||
+ .dir_msk = RK806_PWRCTRL2_DR,
|
||||
+ },
|
||||
+ {
|
||||
+ .fun_reg = RK806_SLEEP_CONFIG1,
|
||||
+ .fun_msk = RK806_PWRCTRL3_FUN,
|
||||
+ .reg = RK806_SLEEP_GPIO,
|
||||
+ .val_msk = RK806_PWRCTRL3_DATA,
|
||||
+ .dir_msk = RK806_PWRCTRL3_DR,
|
||||
+ }
|
||||
+};
|
||||
+
|
||||
/* generic gpio chip */
|
||||
static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
@@ -289,19 +412,13 @@ static int _rk805_pinctrl_set_mux(struct
|
||||
if (!pci->pin_cfg[offset].fun_msk)
|
||||
return 0;
|
||||
|
||||
- if (mux == RK805_PINMUX_GPIO) {
|
||||
- ret = regmap_update_bits(pci->rk808->regmap,
|
||||
- pci->pin_cfg[offset].reg,
|
||||
- pci->pin_cfg[offset].fun_msk,
|
||||
- pci->pin_cfg[offset].fun_msk);
|
||||
- if (ret) {
|
||||
- dev_err(pci->dev, "set gpio%d GPIO failed\n", offset);
|
||||
- return ret;
|
||||
- }
|
||||
- } else {
|
||||
- dev_err(pci->dev, "Couldn't find function mux %d\n", mux);
|
||||
- return -EINVAL;
|
||||
- }
|
||||
+ mux <<= ffs(pci->pin_cfg[offset].fun_msk) - 1;
|
||||
+ ret = regmap_update_bits(pci->rk808->regmap,
|
||||
+ pci->pin_cfg[offset].fun_reg,
|
||||
+ pci->pin_cfg[offset].fun_msk, mux);
|
||||
+
|
||||
+ if (ret)
|
||||
+ dev_err(pci->dev, "set gpio%d func%d failed\n", offset, mux);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -317,6 +434,22 @@ static int rk805_pinctrl_set_mux(struct
|
||||
return _rk805_pinctrl_set_mux(pctldev, offset, mux);
|
||||
}
|
||||
|
||||
+static int rk805_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
|
||||
+ struct pinctrl_gpio_range *range,
|
||||
+ unsigned int offset)
|
||||
+{
|
||||
+ struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
|
||||
+
|
||||
+ switch (pci->rk808->variant) {
|
||||
+ case RK805_ID:
|
||||
+ return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
|
||||
+ case RK806_ID:
|
||||
+ return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5);
|
||||
+ }
|
||||
+
|
||||
+ return -ENOTSUPP;
|
||||
+}
|
||||
+
|
||||
static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_gpio_range *range,
|
||||
unsigned int offset, bool input)
|
||||
@@ -324,13 +457,6 @@ static int rk805_pmx_gpio_set_direction(
|
||||
struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
|
||||
int ret;
|
||||
|
||||
- /* switch to gpio function */
|
||||
- ret = _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
|
||||
- if (ret) {
|
||||
- dev_err(pci->dev, "set gpio%d mux failed\n", offset);
|
||||
- return ret;
|
||||
- }
|
||||
-
|
||||
/* set direction */
|
||||
if (!pci->pin_cfg[offset].dir_msk)
|
||||
return 0;
|
||||
@@ -352,6 +478,7 @@ static const struct pinmux_ops rk805_pin
|
||||
.get_function_name = rk805_pinctrl_get_func_name,
|
||||
.get_function_groups = rk805_pinctrl_get_func_groups,
|
||||
.set_mux = rk805_pinctrl_set_mux,
|
||||
+ .gpio_request_enable = rk805_pinctrl_gpio_request_enable,
|
||||
.gpio_set_direction = rk805_pmx_gpio_set_direction,
|
||||
};
|
||||
|
||||
@@ -364,6 +491,7 @@ static int rk805_pinconf_get(struct pinc
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_OUTPUT:
|
||||
+ case PIN_CONFIG_INPUT_ENABLE:
|
||||
arg = rk805_gpio_get(&pci->gpio_chip, pin);
|
||||
break;
|
||||
default:
|
||||
@@ -393,6 +521,12 @@ static int rk805_pinconf_set(struct pinc
|
||||
rk805_gpio_set(&pci->gpio_chip, pin, arg);
|
||||
rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false);
|
||||
break;
|
||||
+ case PIN_CONFIG_INPUT_ENABLE:
|
||||
+ if (pci->rk808->variant != RK805_ID && arg) {
|
||||
+ rk805_pmx_gpio_set_direction(pctldev, NULL, pin, true);
|
||||
+ break;
|
||||
+ }
|
||||
+ fallthrough;
|
||||
default:
|
||||
dev_err(pci->dev, "Properties not supported\n");
|
||||
return -ENOTSUPP;
|
||||
@@ -448,6 +582,18 @@ static int rk805_pinctrl_probe(struct pl
|
||||
pci->pin_cfg = rk805_gpio_cfgs;
|
||||
pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs);
|
||||
break;
|
||||
+ case RK806_ID:
|
||||
+ pci->pins = rk806_pins_desc;
|
||||
+ pci->num_pins = ARRAY_SIZE(rk806_pins_desc);
|
||||
+ pci->functions = rk806_pin_functions;
|
||||
+ pci->num_functions = ARRAY_SIZE(rk806_pin_functions);
|
||||
+ pci->groups = rk806_pin_groups;
|
||||
+ pci->num_pin_groups = ARRAY_SIZE(rk806_pin_groups);
|
||||
+ pci->pinctrl_desc.pins = rk806_pins_desc;
|
||||
+ pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc);
|
||||
+ pci->pin_cfg = rk806_gpio_cfgs;
|
||||
+ pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs);
|
||||
+ break;
|
||||
default:
|
||||
dev_err(&pdev->dev, "unsupported RK805 ID %lu\n",
|
||||
pci->rk808->variant);
|
||||
@@ -488,5 +634,6 @@ static struct platform_driver rk805_pinc
|
||||
module_platform_driver(rk805_pinctrl_driver);
|
||||
|
||||
MODULE_DESCRIPTION("RK805 pin control and GPIO driver");
|
||||
+MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
|
||||
MODULE_AUTHOR("Joseph Chen <chenjh@rock-chips.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -16,7 +16,7 @@ Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
|
||||
--- a/drivers/mfd/rk8xx-core.c
|
||||
+++ b/drivers/mfd/rk8xx-core.c
|
||||
@@ -685,7 +685,8 @@ int rk8xx_probe(struct device *dev, int
|
||||
@@ -677,7 +677,8 @@ int rk8xx_probe(struct device *dev, int
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to add MFD devices\n");
|
||||
|
||||
|
||||
@ -16,7 +16,7 @@ Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
|
||||
--- a/drivers/mfd/rk8xx-core.c
|
||||
+++ b/drivers/mfd/rk8xx-core.c
|
||||
@@ -525,6 +525,10 @@ static int rk808_power_off(struct sys_of
|
||||
@@ -517,6 +517,10 @@ static int rk808_power_off(struct sys_of
|
||||
reg = RK805_DEV_CTRL_REG;
|
||||
bit = DEV_OFF;
|
||||
break;
|
||||
|
||||
@ -1,164 +0,0 @@
|
||||
From 4aedcd4aa61d536ca17e67ecd5bc5d42529164f4 Mon Sep 17 00:00:00 2001
|
||||
From: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
Date: Thu, 16 Nov 2023 15:05:13 +0100
|
||||
Subject: [PATCH] mfd: rk8xx: fixup devices registration with
|
||||
PLATFORM_DEVID_AUTO
|
||||
|
||||
Since commit 210f418f8ace ("mfd: rk8xx: Add rk806 support"), devices are
|
||||
registered with "0" as id, causing devices to not have an automatic device id
|
||||
and prevents having multiple RK8xx PMICs on the same system.
|
||||
|
||||
Properly pass PLATFORM_DEVID_AUTO to devm_mfd_add_devices() and since
|
||||
it will ignore the cells .id with this special value, also cleanup
|
||||
by removing all now ignored cells .id values.
|
||||
|
||||
Now we have the same behaviour as before rk806 introduction and rk806
|
||||
retains the intended behavior.
|
||||
|
||||
This fixes a regression while booting the Odroid Go Ultra on v6.6.1:
|
||||
sysfs: cannot create duplicate filename '/bus/platform/devices/rk808-clkout'
|
||||
CPU: 3 PID: 97 Comm: kworker/u12:2 Not tainted 6.6.1 #1
|
||||
Hardware name: Hardkernel ODROID-GO-Ultra (DT)
|
||||
Workqueue: events_unbound deferred_probe_work_func
|
||||
Call trace:
|
||||
dump_backtrace+0x9c/0x11c
|
||||
show_stack+0x18/0x24
|
||||
dump_stack_lvl+0x78/0xc4
|
||||
dump_stack+0x18/0x24
|
||||
sysfs_warn_dup+0x64/0x80
|
||||
sysfs_do_create_link_sd+0xf0/0xf8
|
||||
sysfs_create_link+0x20/0x40
|
||||
bus_add_device+0x114/0x160
|
||||
device_add+0x3f0/0x7cc
|
||||
platform_device_add+0x180/0x270
|
||||
mfd_add_device+0x390/0x4a8
|
||||
devm_mfd_add_devices+0xb0/0x150
|
||||
rk8xx_probe+0x26c/0x410
|
||||
rk8xx_i2c_probe+0x64/0x98
|
||||
i2c_device_probe+0x104/0x2e8
|
||||
really_probe+0x184/0x3c8
|
||||
__driver_probe_device+0x7c/0x16c
|
||||
driver_probe_device+0x3c/0x10c
|
||||
__device_attach_driver+0xbc/0x158
|
||||
bus_for_each_drv+0x80/0xdc
|
||||
__device_attach+0x9c/0x1ac
|
||||
device_initial_probe+0x14/0x20
|
||||
bus_probe_device+0xac/0xb0
|
||||
deferred_probe_work_func+0xa0/0xf4
|
||||
process_one_work+0x1bc/0x378
|
||||
worker_thread+0x1dc/0x3d4
|
||||
kthread+0x104/0x118
|
||||
ret_from_fork+0x10/0x20
|
||||
rk8xx-i2c 0-001c: error -EEXIST: failed to add MFD devices
|
||||
rk8xx-i2c: probe of 0-001c failed with error -17
|
||||
|
||||
Fixes: 210f418f8ace ("mfd: rk8xx: Add rk806 support")
|
||||
Reported-by: Adam Green <greena88@gmail.com>
|
||||
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20231116-topic-amlogic-upstream-fix-rk8xx-devid-auto-v2-1-3f1bad68ab9d@linaro.org
|
||||
Signed-off-by: Lee Jones <lee@kernel.org>
|
||||
---
|
||||
drivers/mfd/rk8xx-core.c | 34 +++++++++++++---------------------
|
||||
1 file changed, 13 insertions(+), 21 deletions(-)
|
||||
|
||||
--- a/drivers/mfd/rk8xx-core.c
|
||||
+++ b/drivers/mfd/rk8xx-core.c
|
||||
@@ -53,76 +53,68 @@ static const struct resource rk817_charg
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk805s[] = {
|
||||
- { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
|
||||
- { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
- { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, },
|
||||
+ { .name = "rk808-clkout", },
|
||||
+ { .name = "rk808-regulator", },
|
||||
+ { .name = "rk805-pinctrl", },
|
||||
{
|
||||
.name = "rk808-rtc",
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resources = &rtc_resources[0],
|
||||
- .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
{ .name = "rk805-pwrkey",
|
||||
.num_resources = ARRAY_SIZE(rk805_key_resources),
|
||||
.resources = &rk805_key_resources[0],
|
||||
- .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk806s[] = {
|
||||
- { .name = "rk805-pinctrl", .id = PLATFORM_DEVID_AUTO, },
|
||||
- { .name = "rk808-regulator", .id = PLATFORM_DEVID_AUTO, },
|
||||
+ { .name = "rk805-pinctrl", },
|
||||
+ { .name = "rk808-regulator", },
|
||||
{
|
||||
.name = "rk805-pwrkey",
|
||||
.resources = rk806_pwrkey_resources,
|
||||
.num_resources = ARRAY_SIZE(rk806_pwrkey_resources),
|
||||
- .id = PLATFORM_DEVID_AUTO,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk808s[] = {
|
||||
- { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
|
||||
- { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
+ { .name = "rk808-clkout", },
|
||||
+ { .name = "rk808-regulator", },
|
||||
{
|
||||
.name = "rk808-rtc",
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resources = rtc_resources,
|
||||
- .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk817s[] = {
|
||||
- { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
|
||||
- { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
+ { .name = "rk808-clkout", },
|
||||
+ { .name = "rk808-regulator", },
|
||||
{
|
||||
.name = "rk805-pwrkey",
|
||||
.num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
|
||||
.resources = &rk817_pwrkey_resources[0],
|
||||
- .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
{
|
||||
.name = "rk808-rtc",
|
||||
.num_resources = ARRAY_SIZE(rk817_rtc_resources),
|
||||
.resources = &rk817_rtc_resources[0],
|
||||
- .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
- { .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, },
|
||||
+ { .name = "rk817-codec", },
|
||||
{
|
||||
.name = "rk817-charger",
|
||||
.num_resources = ARRAY_SIZE(rk817_charger_resources),
|
||||
.resources = &rk817_charger_resources[0],
|
||||
- .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct mfd_cell rk818s[] = {
|
||||
- { .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
|
||||
- { .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
|
||||
+ { .name = "rk808-clkout", },
|
||||
+ { .name = "rk808-regulator", },
|
||||
{
|
||||
.name = "rk808-rtc",
|
||||
.num_resources = ARRAY_SIZE(rtc_resources),
|
||||
.resources = rtc_resources,
|
||||
- .id = PLATFORM_DEVID_NONE,
|
||||
},
|
||||
};
|
||||
|
||||
@@ -684,7 +676,7 @@ int rk8xx_probe(struct device *dev, int
|
||||
pre_init_reg[i].addr);
|
||||
}
|
||||
|
||||
- ret = devm_mfd_add_devices(dev, 0, cells, nr_cells, NULL, 0,
|
||||
+ ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, nr_cells, NULL, 0,
|
||||
regmap_irq_get_domain(rk808->irq_data));
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to add MFD devices\n");
|
||||
@ -1,82 +0,0 @@
|
||||
From 647e57351f8ebc37d8e12cbc0f4bf7471754a0cc Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 20 Oct 2022 22:42:40 +0200
|
||||
Subject: [PATCH] regulator: rk808: reduce 'struct rk808' usage
|
||||
|
||||
Reduce usage of 'struct rk808' (driver data of the parent MFD), so
|
||||
that only the chip variant field is still being accessed directly.
|
||||
This allows restructuring the MFD driver to support SPI based
|
||||
PMICs.
|
||||
|
||||
Acked-by: Mark Brown <broonie@kernel.org>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221020204251.108565-3-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/rk808-regulator.c | 20 ++++++++++++--------
|
||||
1 file changed, 12 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/regulator/rk808-regulator.c
|
||||
+++ b/drivers/regulator/rk808-regulator.c
|
||||
@@ -14,7 +14,6 @@
|
||||
|
||||
#include <linux/delay.h>
|
||||
#include <linux/gpio.h>
|
||||
-#include <linux/i2c.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_gpio.h>
|
||||
@@ -1286,19 +1285,23 @@ dt_parse_end:
|
||||
static int rk808_regulator_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
|
||||
- struct i2c_client *client = rk808->i2c;
|
||||
struct regulator_config config = {};
|
||||
struct regulator_dev *rk808_rdev;
|
||||
struct rk808_regulator_data *pdata;
|
||||
const struct regulator_desc *regulators;
|
||||
+ struct regmap *regmap;
|
||||
int ret, i, nregulators;
|
||||
|
||||
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
|
||||
+ if (!regmap)
|
||||
+ return -ENODEV;
|
||||
+
|
||||
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
||||
if (!pdata)
|
||||
return -ENOMEM;
|
||||
|
||||
- ret = rk808_regulator_dt_parse_pdata(&pdev->dev, &client->dev,
|
||||
- rk808->regmap, pdata);
|
||||
+ ret = rk808_regulator_dt_parse_pdata(&pdev->dev, pdev->dev.parent,
|
||||
+ regmap, pdata);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
@@ -1326,21 +1329,22 @@ static int rk808_regulator_probe(struct
|
||||
nregulators = RK818_NUM_REGULATORS;
|
||||
break;
|
||||
default:
|
||||
- dev_err(&client->dev, "unsupported RK8XX ID %lu\n",
|
||||
+ dev_err(&pdev->dev, "unsupported RK8XX ID %lu\n",
|
||||
rk808->variant);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
- config.dev = &client->dev;
|
||||
+ config.dev = &pdev->dev;
|
||||
+ config.dev->of_node = pdev->dev.parent->of_node;
|
||||
config.driver_data = pdata;
|
||||
- config.regmap = rk808->regmap;
|
||||
+ config.regmap = regmap;
|
||||
|
||||
/* Instantiate the regulators */
|
||||
for (i = 0; i < nregulators; i++) {
|
||||
rk808_rdev = devm_regulator_register(&pdev->dev,
|
||||
®ulators[i], &config);
|
||||
if (IS_ERR(rk808_rdev)) {
|
||||
- dev_err(&client->dev,
|
||||
+ dev_err(&pdev->dev,
|
||||
"failed to register %d regulator\n", i);
|
||||
return PTR_ERR(rk808_rdev);
|
||||
}
|
||||
@ -1,34 +0,0 @@
|
||||
From f39f8709c217d82aabbf51d8669731137ce09aea Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 20 Oct 2022 22:42:49 +0200
|
||||
Subject: [PATCH] regulator: rk808: Use dev_err_probe
|
||||
|
||||
Print error message for potential EPROBE_DEFER error using
|
||||
dev_err_probe, which captures the reason in
|
||||
/sys/kernel/debug/devices_deferred and otherwise silences
|
||||
the message.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20221020204251.108565-12-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/rk808-regulator.c | 8 +++-----
|
||||
1 file changed, 3 insertions(+), 5 deletions(-)
|
||||
|
||||
--- a/drivers/regulator/rk808-regulator.c
|
||||
+++ b/drivers/regulator/rk808-regulator.c
|
||||
@@ -1343,11 +1343,9 @@ static int rk808_regulator_probe(struct
|
||||
for (i = 0; i < nregulators; i++) {
|
||||
rk808_rdev = devm_regulator_register(&pdev->dev,
|
||||
®ulators[i], &config);
|
||||
- if (IS_ERR(rk808_rdev)) {
|
||||
- dev_err(&pdev->dev,
|
||||
- "failed to register %d regulator\n", i);
|
||||
- return PTR_ERR(rk808_rdev);
|
||||
- }
|
||||
+ if (IS_ERR(rk808_rdev))
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(rk808_rdev),
|
||||
+ "failed to register %d regulator\n", i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -1,76 +0,0 @@
|
||||
From 431cb97b763133fba8b1c68c1ed089315f25e4dd Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:14 +0200
|
||||
Subject: [PATCH] regulator: expose regulator_find_closest_bigger
|
||||
|
||||
Expose and document the table lookup logic used by
|
||||
regulator_set_ramp_delay_regmap, so that it can be
|
||||
reused for devices that cannot be configured via
|
||||
regulator_set_ramp_delay_regmap.
|
||||
|
||||
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-11-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/helpers.c | 22 ++++++++++++++++++----
|
||||
include/linux/regulator/driver.h | 2 ++
|
||||
2 files changed, 20 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/regulator/helpers.c
|
||||
+++ b/drivers/regulator/helpers.c
|
||||
@@ -902,8 +902,21 @@ bool regulator_is_equal(struct regulator
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(regulator_is_equal);
|
||||
|
||||
-static int find_closest_bigger(unsigned int target, const unsigned int *table,
|
||||
- unsigned int num_sel, unsigned int *sel)
|
||||
+/**
|
||||
+ * regulator_find_closest_bigger - helper to find offset in ramp delay table
|
||||
+ *
|
||||
+ * @target: targeted ramp_delay
|
||||
+ * @table: table with supported ramp delays
|
||||
+ * @num_sel: number of entries in the table
|
||||
+ * @sel: Pointer to store table offset
|
||||
+ *
|
||||
+ * This is the internal helper used by regulator_set_ramp_delay_regmap to
|
||||
+ * map ramp delay to register value. It should only be used directly if
|
||||
+ * regulator_set_ramp_delay_regmap cannot handle a specific device setup
|
||||
+ * (e.g. because the value is split over multiple registers).
|
||||
+ */
|
||||
+int regulator_find_closest_bigger(unsigned int target, const unsigned int *table,
|
||||
+ unsigned int num_sel, unsigned int *sel)
|
||||
{
|
||||
unsigned int s, tmp, max, maxsel = 0;
|
||||
bool found = false;
|
||||
@@ -933,6 +946,7 @@ static int find_closest_bigger(unsigned
|
||||
|
||||
return 0;
|
||||
}
|
||||
+EXPORT_SYMBOL_GPL(regulator_find_closest_bigger);
|
||||
|
||||
/**
|
||||
* regulator_set_ramp_delay_regmap - set_ramp_delay() helper
|
||||
@@ -951,8 +965,8 @@ int regulator_set_ramp_delay_regmap(stru
|
||||
if (WARN_ON(!rdev->desc->n_ramp_values || !rdev->desc->ramp_delay_table))
|
||||
return -EINVAL;
|
||||
|
||||
- ret = find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table,
|
||||
- rdev->desc->n_ramp_values, &sel);
|
||||
+ ret = regulator_find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table,
|
||||
+ rdev->desc->n_ramp_values, &sel);
|
||||
|
||||
if (ret) {
|
||||
dev_warn(rdev_get_dev(rdev),
|
||||
--- a/include/linux/regulator/driver.h
|
||||
+++ b/include/linux/regulator/driver.h
|
||||
@@ -758,6 +758,8 @@ int regulator_set_current_limit_regmap(s
|
||||
int min_uA, int max_uA);
|
||||
int regulator_get_current_limit_regmap(struct regulator_dev *rdev);
|
||||
void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data);
|
||||
+int regulator_find_closest_bigger(unsigned int target, const unsigned int *table,
|
||||
+ unsigned int num_sel, unsigned int *sel);
|
||||
int regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay);
|
||||
int regulator_sync_voltage_rdev(struct regulator_dev *rdev);
|
||||
|
||||
@ -1,31 +0,0 @@
|
||||
From 1b9e86d445a0f5c6d8dcbaf11508cb5dfb5848a8 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:15 +0200
|
||||
Subject: [PATCH] regulator: rk808: fix asynchronous probing
|
||||
|
||||
If the probe routine fails with -EPROBE_DEFER after taking over the
|
||||
OF node from its parent driver, reprobing triggers pinctrl_bind_pins()
|
||||
and that will fail. Fix this by setting of_node_reused, so that the
|
||||
device does not try to setup pin muxing.
|
||||
|
||||
For me this always happens once the driver is marked to prefer async
|
||||
probing and never happens without that flag.
|
||||
|
||||
Fixes: 259b93b21a9f ("regulator: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in 4.14")
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-12-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/rk808-regulator.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/drivers/regulator/rk808-regulator.c
|
||||
+++ b/drivers/regulator/rk808-regulator.c
|
||||
@@ -1336,6 +1336,7 @@ static int rk808_regulator_probe(struct
|
||||
|
||||
config.dev = &pdev->dev;
|
||||
config.dev->of_node = pdev->dev.parent->of_node;
|
||||
+ config.dev->of_node_reused = true;
|
||||
config.driver_data = pdata;
|
||||
config.regmap = regmap;
|
||||
|
||||
@ -1,70 +0,0 @@
|
||||
From 5111c931f36cebe77d4ce66964c348e6eb4afca0 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:16 +0200
|
||||
Subject: [PATCH] regulator: rk808: cleanup parent device usage
|
||||
|
||||
By overridering the device's of_node a bit earlier we can
|
||||
get the GPIOs and any other DT properties from our own
|
||||
device instead of relying on the parent device.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-13-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/rk808-regulator.c | 13 ++++++-------
|
||||
1 file changed, 6 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/drivers/regulator/rk808-regulator.c
|
||||
+++ b/drivers/regulator/rk808-regulator.c
|
||||
@@ -1245,20 +1245,19 @@ static const struct regulator_desc rk818
|
||||
};
|
||||
|
||||
static int rk808_regulator_dt_parse_pdata(struct device *dev,
|
||||
- struct device *client_dev,
|
||||
struct regmap *map,
|
||||
struct rk808_regulator_data *pdata)
|
||||
{
|
||||
struct device_node *np;
|
||||
int tmp, ret = 0, i;
|
||||
|
||||
- np = of_get_child_by_name(client_dev->of_node, "regulators");
|
||||
+ np = of_get_child_by_name(dev->of_node, "regulators");
|
||||
if (!np)
|
||||
return -ENXIO;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pdata->dvs_gpio); i++) {
|
||||
pdata->dvs_gpio[i] =
|
||||
- devm_gpiod_get_index_optional(client_dev, "dvs", i,
|
||||
+ devm_gpiod_get_index_optional(dev, "dvs", i,
|
||||
GPIOD_OUT_LOW);
|
||||
if (IS_ERR(pdata->dvs_gpio[i])) {
|
||||
ret = PTR_ERR(pdata->dvs_gpio[i]);
|
||||
@@ -1292,6 +1291,9 @@ static int rk808_regulator_probe(struct
|
||||
struct regmap *regmap;
|
||||
int ret, i, nregulators;
|
||||
|
||||
+ pdev->dev.of_node = pdev->dev.parent->of_node;
|
||||
+ pdev->dev.of_node_reused = true;
|
||||
+
|
||||
regmap = dev_get_regmap(pdev->dev.parent, NULL);
|
||||
if (!regmap)
|
||||
return -ENODEV;
|
||||
@@ -1300,8 +1302,7 @@ static int rk808_regulator_probe(struct
|
||||
if (!pdata)
|
||||
return -ENOMEM;
|
||||
|
||||
- ret = rk808_regulator_dt_parse_pdata(&pdev->dev, pdev->dev.parent,
|
||||
- regmap, pdata);
|
||||
+ ret = rk808_regulator_dt_parse_pdata(&pdev->dev, regmap, pdata);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
@@ -1335,8 +1336,6 @@ static int rk808_regulator_probe(struct
|
||||
}
|
||||
|
||||
config.dev = &pdev->dev;
|
||||
- config.dev->of_node = pdev->dev.parent->of_node;
|
||||
- config.dev->of_node_reused = true;
|
||||
config.driver_data = pdata;
|
||||
config.regmap = regmap;
|
||||
|
||||
@ -1,482 +0,0 @@
|
||||
From f991a220a44726c54c2332569a2a80bf074aa775 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Thu, 4 May 2023 19:36:18 +0200
|
||||
Subject: [PATCH] regulator: rk808: add rk806 support
|
||||
|
||||
Add rk806 support to the existing rk808 regulator
|
||||
driver.
|
||||
|
||||
This has been implemented using shengfei Xu's rk806
|
||||
specific driver from the vendor tree as reference.
|
||||
|
||||
Co-developed-by: shengfei Xu <xsf@rock-chips.com>
|
||||
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
|
||||
Reviewed-by: Matti Vaittinen <mazziesaccount@gmail.com>
|
||||
Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
|
||||
Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230504173618.142075-15-sebastian.reichel@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/rk808-regulator.c | 385 ++++++++++++++++++++++++++++
|
||||
1 file changed, 385 insertions(+)
|
||||
|
||||
--- a/drivers/regulator/rk808-regulator.c
|
||||
+++ b/drivers/regulator/rk808-regulator.c
|
||||
@@ -3,9 +3,11 @@
|
||||
* Regulator driver for Rockchip RK805/RK808/RK818
|
||||
*
|
||||
* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
|
||||
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
* Author: Chris Zhong <zyw@rock-chips.com>
|
||||
* Author: Zhang Qing <zhangqing@rock-chips.com>
|
||||
+ * Author: Xu Shengfei <xsf@rock-chips.com>
|
||||
*
|
||||
* Copyright (C) 2016 PHYTEC Messtechnik GmbH
|
||||
*
|
||||
@@ -39,6 +41,13 @@
|
||||
#define RK818_LDO3_ON_VSEL_MASK 0xf
|
||||
#define RK818_BOOST_ON_VSEL_MASK 0xe0
|
||||
|
||||
+#define RK806_DCDC_SLP_REG_OFFSET 0x0A
|
||||
+#define RK806_NLDO_SLP_REG_OFFSET 0x05
|
||||
+#define RK806_PLDO_SLP_REG_OFFSET 0x06
|
||||
+
|
||||
+#define RK806_BUCK_SEL_CNT 0xff
|
||||
+#define RK806_LDO_SEL_CNT 0xff
|
||||
+
|
||||
/* Ramp rate definitions for buck1 / buck2 only */
|
||||
#define RK808_RAMP_RATE_OFFSET 3
|
||||
#define RK808_RAMP_RATE_MASK (3 << RK808_RAMP_RATE_OFFSET)
|
||||
@@ -117,6 +126,34 @@
|
||||
RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
|
||||
_vmask, _ereg, _emask, 0, 0, _etime, &rk805_reg_ops)
|
||||
|
||||
+#define RK806_REGULATOR(_name, _supply_name, _id, _ops,\
|
||||
+ _n_voltages, _vr, _er, _lr, ctrl_bit,\
|
||||
+ _rr, _rm, _rt)\
|
||||
+[_id] = {\
|
||||
+ .name = _name,\
|
||||
+ .supply_name = _supply_name,\
|
||||
+ .of_match = of_match_ptr(_name),\
|
||||
+ .regulators_node = of_match_ptr("regulators"),\
|
||||
+ .id = _id,\
|
||||
+ .ops = &_ops,\
|
||||
+ .type = REGULATOR_VOLTAGE,\
|
||||
+ .n_voltages = _n_voltages,\
|
||||
+ .linear_ranges = _lr,\
|
||||
+ .n_linear_ranges = ARRAY_SIZE(_lr),\
|
||||
+ .vsel_reg = _vr,\
|
||||
+ .vsel_mask = 0xff,\
|
||||
+ .enable_reg = _er,\
|
||||
+ .enable_mask = ENABLE_MASK(ctrl_bit),\
|
||||
+ .enable_val = ENABLE_MASK(ctrl_bit),\
|
||||
+ .disable_val = DISABLE_VAL(ctrl_bit),\
|
||||
+ .of_map_mode = rk8xx_regulator_of_map_mode,\
|
||||
+ .ramp_reg = _rr,\
|
||||
+ .ramp_mask = _rm,\
|
||||
+ .ramp_delay_table = _rt, \
|
||||
+ .n_ramp_values = ARRAY_SIZE(_rt), \
|
||||
+ .owner = THIS_MODULE,\
|
||||
+ }
|
||||
+
|
||||
#define RK8XX_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
|
||||
_vmask, _ereg, _emask, _etime) \
|
||||
RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
|
||||
@@ -153,6 +190,17 @@
|
||||
RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask, \
|
||||
0, 0, &rk808_switch_ops)
|
||||
|
||||
+struct rk8xx_register_bit {
|
||||
+ u8 reg;
|
||||
+ u8 bit;
|
||||
+};
|
||||
+
|
||||
+#define RK8XX_REG_BIT(_reg, _bit) \
|
||||
+ { \
|
||||
+ .reg = _reg, \
|
||||
+ .bit = BIT(_bit), \
|
||||
+ }
|
||||
+
|
||||
struct rk808_regulator_data {
|
||||
struct gpio_desc *dvs_gpio[2];
|
||||
};
|
||||
@@ -216,6 +264,133 @@ static const unsigned int rk817_buck1_4_
|
||||
3000, 6300, 12500, 25000
|
||||
};
|
||||
|
||||
+static int rk806_set_mode_dcdc(struct regulator_dev *rdev, unsigned int mode)
|
||||
+{
|
||||
+ int rid = rdev_get_id(rdev);
|
||||
+ int ctr_bit, reg;
|
||||
+
|
||||
+ reg = RK806_POWER_FPWM_EN0 + rid / 8;
|
||||
+ ctr_bit = rid % 8;
|
||||
+
|
||||
+ switch (mode) {
|
||||
+ case REGULATOR_MODE_FAST:
|
||||
+ return regmap_update_bits(rdev->regmap, reg,
|
||||
+ PWM_MODE_MSK << ctr_bit,
|
||||
+ FPWM_MODE << ctr_bit);
|
||||
+ case REGULATOR_MODE_NORMAL:
|
||||
+ return regmap_update_bits(rdev->regmap, reg,
|
||||
+ PWM_MODE_MSK << ctr_bit,
|
||||
+ AUTO_PWM_MODE << ctr_bit);
|
||||
+ default:
|
||||
+ dev_err(rdev_get_dev(rdev), "mode unsupported: %u\n", mode);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static unsigned int rk806_get_mode_dcdc(struct regulator_dev *rdev)
|
||||
+{
|
||||
+ int rid = rdev_get_id(rdev);
|
||||
+ int ctr_bit, reg;
|
||||
+ unsigned int val;
|
||||
+ int err;
|
||||
+
|
||||
+ reg = RK806_POWER_FPWM_EN0 + rid / 8;
|
||||
+ ctr_bit = rid % 8;
|
||||
+
|
||||
+ err = regmap_read(rdev->regmap, reg, &val);
|
||||
+ if (err)
|
||||
+ return err;
|
||||
+
|
||||
+ if ((val >> ctr_bit) & FPWM_MODE)
|
||||
+ return REGULATOR_MODE_FAST;
|
||||
+ else
|
||||
+ return REGULATOR_MODE_NORMAL;
|
||||
+}
|
||||
+
|
||||
+static const struct rk8xx_register_bit rk806_dcdc_rate2[] = {
|
||||
+ RK8XX_REG_BIT(0xEB, 0),
|
||||
+ RK8XX_REG_BIT(0xEB, 1),
|
||||
+ RK8XX_REG_BIT(0xEB, 2),
|
||||
+ RK8XX_REG_BIT(0xEB, 3),
|
||||
+ RK8XX_REG_BIT(0xEB, 4),
|
||||
+ RK8XX_REG_BIT(0xEB, 5),
|
||||
+ RK8XX_REG_BIT(0xEB, 6),
|
||||
+ RK8XX_REG_BIT(0xEB, 7),
|
||||
+ RK8XX_REG_BIT(0xEA, 0),
|
||||
+ RK8XX_REG_BIT(0xEA, 1),
|
||||
+};
|
||||
+
|
||||
+static const unsigned int rk806_ramp_delay_table_dcdc[] = {
|
||||
+ 50000, 25000, 12500, 6250, 3125, 1560, 961, 390
|
||||
+};
|
||||
+
|
||||
+static int rk806_set_ramp_delay_dcdc(struct regulator_dev *rdev, int ramp_delay)
|
||||
+{
|
||||
+ int rid = rdev_get_id(rdev);
|
||||
+ int regval, ramp_value, ret;
|
||||
+
|
||||
+ ret = regulator_find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table,
|
||||
+ rdev->desc->n_ramp_values, &ramp_value);
|
||||
+ if (ret) {
|
||||
+ dev_warn(rdev_get_dev(rdev),
|
||||
+ "Can't set ramp-delay %u, setting %u\n", ramp_delay,
|
||||
+ rdev->desc->ramp_delay_table[ramp_value]);
|
||||
+ }
|
||||
+
|
||||
+ regval = ramp_value << (ffs(rdev->desc->ramp_mask) - 1);
|
||||
+
|
||||
+ ret = regmap_update_bits(rdev->regmap, rdev->desc->ramp_reg,
|
||||
+ rdev->desc->ramp_mask, regval);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /*
|
||||
+ * The above is effectively a copy of regulator_set_ramp_delay_regmap(),
|
||||
+ * but that only stores the lower 2 bits for rk806 DCDC ramp. The MSB must
|
||||
+ * be stored in a separate register, so this open codes the implementation
|
||||
+ * to have access to the ramp_value.
|
||||
+ */
|
||||
+
|
||||
+ regval = (ramp_value >> 2) & 0x1 ? rk806_dcdc_rate2[rid].bit : 0;
|
||||
+ return regmap_update_bits(rdev->regmap, rk806_dcdc_rate2[rid].reg,
|
||||
+ rk806_dcdc_rate2[rid].bit,
|
||||
+ regval);
|
||||
+}
|
||||
+
|
||||
+static const unsigned int rk806_ramp_delay_table_ldo[] = {
|
||||
+ 100000, 50000, 25000, 12500, 6280, 3120, 1900, 780
|
||||
+};
|
||||
+
|
||||
+static int rk806_set_suspend_voltage_range(struct regulator_dev *rdev, int reg_offset, int uv)
|
||||
+{
|
||||
+ int sel = regulator_map_voltage_linear_range(rdev, uv, uv);
|
||||
+ unsigned int reg;
|
||||
+
|
||||
+ if (sel < 0)
|
||||
+ return -EINVAL;
|
||||
+
|
||||
+ reg = rdev->desc->vsel_reg + reg_offset;
|
||||
+
|
||||
+ return regmap_update_bits(rdev->regmap, reg, rdev->desc->vsel_mask, sel);
|
||||
+}
|
||||
+
|
||||
+static int rk806_set_suspend_voltage_range_dcdc(struct regulator_dev *rdev, int uv)
|
||||
+{
|
||||
+ return rk806_set_suspend_voltage_range(rdev, RK806_DCDC_SLP_REG_OFFSET, uv);
|
||||
+}
|
||||
+
|
||||
+static int rk806_set_suspend_voltage_range_nldo(struct regulator_dev *rdev, int uv)
|
||||
+{
|
||||
+ return rk806_set_suspend_voltage_range(rdev, RK806_NLDO_SLP_REG_OFFSET, uv);
|
||||
+}
|
||||
+
|
||||
+static int rk806_set_suspend_voltage_range_pldo(struct regulator_dev *rdev, int uv)
|
||||
+{
|
||||
+ return rk806_set_suspend_voltage_range(rdev, RK806_PLDO_SLP_REG_OFFSET, uv);
|
||||
+}
|
||||
+
|
||||
static int rk808_buck1_2_get_voltage_sel_regmap(struct regulator_dev *rdev)
|
||||
{
|
||||
struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev);
|
||||
@@ -393,6 +568,47 @@ static int rk805_set_suspend_disable(str
|
||||
0);
|
||||
}
|
||||
|
||||
+static const struct rk8xx_register_bit rk806_suspend_bits[] = {
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 0),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 1),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 2),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 3),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 4),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 5),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 6),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 7),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 6),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 7),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 0),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 1),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 2),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 3),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 4),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 1),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 2),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 3),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 4),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 5),
|
||||
+ RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 0),
|
||||
+};
|
||||
+
|
||||
+static int rk806_set_suspend_enable(struct regulator_dev *rdev)
|
||||
+{
|
||||
+ int rid = rdev_get_id(rdev);
|
||||
+
|
||||
+ return regmap_update_bits(rdev->regmap, rk806_suspend_bits[rid].reg,
|
||||
+ rk806_suspend_bits[rid].bit,
|
||||
+ rk806_suspend_bits[rid].bit);
|
||||
+}
|
||||
+
|
||||
+static int rk806_set_suspend_disable(struct regulator_dev *rdev)
|
||||
+{
|
||||
+ int rid = rdev_get_id(rdev);
|
||||
+
|
||||
+ return regmap_update_bits(rdev->regmap, rk806_suspend_bits[rid].reg,
|
||||
+ rk806_suspend_bits[rid].bit, 0);
|
||||
+}
|
||||
+
|
||||
static int rk808_set_suspend_enable(struct regulator_dev *rdev)
|
||||
{
|
||||
unsigned int reg;
|
||||
@@ -561,6 +777,64 @@ static const struct regulator_ops rk805_
|
||||
.set_suspend_disable = rk805_set_suspend_disable,
|
||||
};
|
||||
|
||||
+static const struct regulator_ops rk806_ops_dcdc = {
|
||||
+ .list_voltage = regulator_list_voltage_linear_range,
|
||||
+ .map_voltage = regulator_map_voltage_linear_range,
|
||||
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
|
||||
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
|
||||
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
|
||||
+ .set_mode = rk806_set_mode_dcdc,
|
||||
+ .get_mode = rk806_get_mode_dcdc,
|
||||
+
|
||||
+ .enable = regulator_enable_regmap,
|
||||
+ .disable = regulator_disable_regmap,
|
||||
+ .is_enabled = rk8xx_is_enabled_wmsk_regmap,
|
||||
+
|
||||
+ .set_suspend_mode = rk806_set_mode_dcdc,
|
||||
+ .set_ramp_delay = rk806_set_ramp_delay_dcdc,
|
||||
+
|
||||
+ .set_suspend_voltage = rk806_set_suspend_voltage_range_dcdc,
|
||||
+ .set_suspend_enable = rk806_set_suspend_enable,
|
||||
+ .set_suspend_disable = rk806_set_suspend_disable,
|
||||
+};
|
||||
+
|
||||
+static const struct regulator_ops rk806_ops_nldo = {
|
||||
+ .list_voltage = regulator_list_voltage_linear_range,
|
||||
+ .map_voltage = regulator_map_voltage_linear_range,
|
||||
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
|
||||
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
|
||||
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
|
||||
+
|
||||
+ .enable = regulator_enable_regmap,
|
||||
+ .disable = regulator_disable_regmap,
|
||||
+ .is_enabled = regulator_is_enabled_regmap,
|
||||
+
|
||||
+ .set_ramp_delay = regulator_set_ramp_delay_regmap,
|
||||
+
|
||||
+ .set_suspend_voltage = rk806_set_suspend_voltage_range_nldo,
|
||||
+ .set_suspend_enable = rk806_set_suspend_enable,
|
||||
+ .set_suspend_disable = rk806_set_suspend_disable,
|
||||
+};
|
||||
+
|
||||
+static const struct regulator_ops rk806_ops_pldo = {
|
||||
+ .list_voltage = regulator_list_voltage_linear_range,
|
||||
+ .map_voltage = regulator_map_voltage_linear_range,
|
||||
+
|
||||
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
|
||||
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
|
||||
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
|
||||
+
|
||||
+ .enable = regulator_enable_regmap,
|
||||
+ .disable = regulator_disable_regmap,
|
||||
+ .is_enabled = regulator_is_enabled_regmap,
|
||||
+
|
||||
+ .set_ramp_delay = regulator_set_ramp_delay_regmap,
|
||||
+
|
||||
+ .set_suspend_voltage = rk806_set_suspend_voltage_range_pldo,
|
||||
+ .set_suspend_enable = rk806_set_suspend_enable,
|
||||
+ .set_suspend_disable = rk806_set_suspend_disable,
|
||||
+};
|
||||
+
|
||||
static const struct regulator_ops rk808_buck1_2_ops = {
|
||||
.list_voltage = regulator_list_voltage_linear,
|
||||
.map_voltage = regulator_map_voltage_linear,
|
||||
@@ -743,6 +1017,112 @@ static const struct regulator_desc rk805
|
||||
BIT(2), 400),
|
||||
};
|
||||
|
||||
+static const struct linear_range rk806_buck_voltage_ranges[] = {
|
||||
+ REGULATOR_LINEAR_RANGE(500000, 0, 160, 6250), /* 500mV ~ 1500mV */
|
||||
+ REGULATOR_LINEAR_RANGE(1500000, 161, 237, 25000), /* 1500mV ~ 3400mV */
|
||||
+ REGULATOR_LINEAR_RANGE(3400000, 238, 255, 0),
|
||||
+};
|
||||
+
|
||||
+static const struct linear_range rk806_ldo_voltage_ranges[] = {
|
||||
+ REGULATOR_LINEAR_RANGE(500000, 0, 232, 12500), /* 500mV ~ 3400mV */
|
||||
+ REGULATOR_LINEAR_RANGE(3400000, 233, 255, 0), /* 500mV ~ 3400mV */
|
||||
+};
|
||||
+
|
||||
+static const struct regulator_desc rk806_reg[] = {
|
||||
+ RK806_REGULATOR("dcdc-reg1", "vcc1", RK806_ID_DCDC1, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK1_ON_VSEL,
|
||||
+ RK806_POWER_EN0, rk806_buck_voltage_ranges, 0,
|
||||
+ RK806_BUCK1_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+ RK806_REGULATOR("dcdc-reg2", "vcc2", RK806_ID_DCDC2, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK2_ON_VSEL,
|
||||
+ RK806_POWER_EN0, rk806_buck_voltage_ranges, 1,
|
||||
+ RK806_BUCK2_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+ RK806_REGULATOR("dcdc-reg3", "vcc3", RK806_ID_DCDC3, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK3_ON_VSEL,
|
||||
+ RK806_POWER_EN0, rk806_buck_voltage_ranges, 2,
|
||||
+ RK806_BUCK3_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+ RK806_REGULATOR("dcdc-reg4", "vcc4", RK806_ID_DCDC4, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK4_ON_VSEL,
|
||||
+ RK806_POWER_EN0, rk806_buck_voltage_ranges, 3,
|
||||
+ RK806_BUCK4_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+
|
||||
+ RK806_REGULATOR("dcdc-reg5", "vcc5", RK806_ID_DCDC5, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK5_ON_VSEL,
|
||||
+ RK806_POWER_EN1, rk806_buck_voltage_ranges, 0,
|
||||
+ RK806_BUCK5_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+ RK806_REGULATOR("dcdc-reg6", "vcc6", RK806_ID_DCDC6, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK6_ON_VSEL,
|
||||
+ RK806_POWER_EN1, rk806_buck_voltage_ranges, 1,
|
||||
+ RK806_BUCK6_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+ RK806_REGULATOR("dcdc-reg7", "vcc7", RK806_ID_DCDC7, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK7_ON_VSEL,
|
||||
+ RK806_POWER_EN1, rk806_buck_voltage_ranges, 2,
|
||||
+ RK806_BUCK7_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+ RK806_REGULATOR("dcdc-reg8", "vcc8", RK806_ID_DCDC8, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK8_ON_VSEL,
|
||||
+ RK806_POWER_EN1, rk806_buck_voltage_ranges, 3,
|
||||
+ RK806_BUCK8_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+
|
||||
+ RK806_REGULATOR("dcdc-reg9", "vcc9", RK806_ID_DCDC9, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK9_ON_VSEL,
|
||||
+ RK806_POWER_EN2, rk806_buck_voltage_ranges, 0,
|
||||
+ RK806_BUCK9_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+ RK806_REGULATOR("dcdc-reg10", "vcc10", RK806_ID_DCDC10, rk806_ops_dcdc,
|
||||
+ RK806_BUCK_SEL_CNT, RK806_BUCK10_ON_VSEL,
|
||||
+ RK806_POWER_EN2, rk806_buck_voltage_ranges, 1,
|
||||
+ RK806_BUCK10_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
|
||||
+
|
||||
+ RK806_REGULATOR("nldo-reg1", "vcc13", RK806_ID_NLDO1, rk806_ops_nldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_NLDO1_ON_VSEL,
|
||||
+ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 0,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+ RK806_REGULATOR("nldo-reg2", "vcc13", RK806_ID_NLDO2, rk806_ops_nldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_NLDO2_ON_VSEL,
|
||||
+ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 1,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+ RK806_REGULATOR("nldo-reg3", "vcc13", RK806_ID_NLDO3, rk806_ops_nldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_NLDO3_ON_VSEL,
|
||||
+ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 2,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+ RK806_REGULATOR("nldo-reg4", "vcc14", RK806_ID_NLDO4, rk806_ops_nldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_NLDO4_ON_VSEL,
|
||||
+ RK806_POWER_EN3, rk806_ldo_voltage_ranges, 3,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+
|
||||
+ RK806_REGULATOR("nldo-reg5", "vcc14", RK806_ID_NLDO5, rk806_ops_nldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_NLDO5_ON_VSEL,
|
||||
+ RK806_POWER_EN5, rk806_ldo_voltage_ranges, 2,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+
|
||||
+ RK806_REGULATOR("pldo-reg1", "vcc11", RK806_ID_PLDO1, rk806_ops_pldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_PLDO1_ON_VSEL,
|
||||
+ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 1,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+ RK806_REGULATOR("pldo-reg2", "vcc11", RK806_ID_PLDO2, rk806_ops_pldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_PLDO2_ON_VSEL,
|
||||
+ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 2,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+ RK806_REGULATOR("pldo-reg3", "vcc11", RK806_ID_PLDO3, rk806_ops_pldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_PLDO3_ON_VSEL,
|
||||
+ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 3,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+
|
||||
+ RK806_REGULATOR("pldo-reg4", "vcc12", RK806_ID_PLDO4, rk806_ops_pldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_PLDO4_ON_VSEL,
|
||||
+ RK806_POWER_EN5, rk806_ldo_voltage_ranges, 0,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+ RK806_REGULATOR("pldo-reg5", "vcc12", RK806_ID_PLDO5, rk806_ops_pldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_PLDO5_ON_VSEL,
|
||||
+ RK806_POWER_EN5, rk806_ldo_voltage_ranges, 1,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+
|
||||
+ RK806_REGULATOR("pldo-reg6", "vcca", RK806_ID_PLDO6, rk806_ops_pldo,
|
||||
+ RK806_LDO_SEL_CNT, RK806_PLDO6_ON_VSEL,
|
||||
+ RK806_POWER_EN4, rk806_ldo_voltage_ranges, 0,
|
||||
+ 0xEA, 0x38, rk806_ramp_delay_table_ldo),
|
||||
+};
|
||||
+
|
||||
+
|
||||
static const struct regulator_desc rk808_reg[] = {
|
||||
{
|
||||
.name = "DCDC_REG1",
|
||||
@@ -1313,6 +1693,10 @@ static int rk808_regulator_probe(struct
|
||||
regulators = rk805_reg;
|
||||
nregulators = RK805_NUM_REGULATORS;
|
||||
break;
|
||||
+ case RK806_ID:
|
||||
+ regulators = rk806_reg;
|
||||
+ nregulators = ARRAY_SIZE(rk806_reg);
|
||||
+ break;
|
||||
case RK808_ID:
|
||||
regulators = rk808_reg;
|
||||
nregulators = RK808_NUM_REGULATORS;
|
||||
@@ -1365,5 +1749,6 @@ MODULE_AUTHOR("Tony xie <tony.xie@rock-c
|
||||
MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
|
||||
MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
|
||||
MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");
|
||||
+MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:rk808-regulator");
|
||||
@ -1,35 +0,0 @@
|
||||
From d5edc0e36bb1657d2c46b7521010d4f0894a5c74 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Thu, 6 Apr 2023 22:41:54 +0300
|
||||
Subject: [PATCH] regulator: fan53555: Remove unused *_SLEW_SHIFT definitions
|
||||
|
||||
Commit b61ac767db4d ("regulator: fan53555: Convert to use
|
||||
regulator_set_ramp_delay_regmap") removed the slew_shift member from
|
||||
struct fan53555_device_info, hence the {CTL,TCS}_SLEW_SHIFT definitions
|
||||
remained unused. Drop them.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230406194158.963352-5-cristian.ciocaltea@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/fan53555.c | 2 --
|
||||
1 file changed, 2 deletions(-)
|
||||
|
||||
--- a/drivers/regulator/fan53555.c
|
||||
+++ b/drivers/regulator/fan53555.c
|
||||
@@ -49,7 +49,6 @@
|
||||
/* Control bit definitions */
|
||||
#define CTL_OUTPUT_DISCHG (1 << 7)
|
||||
#define CTL_SLEW_MASK (0x7 << 4)
|
||||
-#define CTL_SLEW_SHIFT 4
|
||||
#define CTL_RESET (1 << 2)
|
||||
#define CTL_MODE_VSEL0_MODE BIT(0)
|
||||
#define CTL_MODE_VSEL1_MODE BIT(1)
|
||||
@@ -60,7 +59,6 @@
|
||||
#define TCS_VSEL0_MODE (1 << 7)
|
||||
#define TCS_VSEL1_MODE (1 << 6)
|
||||
|
||||
-#define TCS_SLEW_SHIFT 3
|
||||
#define TCS_SLEW_MASK GENMASK(4, 3)
|
||||
|
||||
enum fan53555_vendor {
|
||||
@ -1,53 +0,0 @@
|
||||
From d25016618c0845b2a0f9ae64d084a66efd39b03c Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Thu, 6 Apr 2023 22:41:55 +0300
|
||||
Subject: [PATCH] regulator: fan53555: Make use of the bit macros
|
||||
|
||||
For consistency and improved clarity, use BIT() and GENMASK() macros for
|
||||
defining the bitfields inside the registers. No functional changes
|
||||
intended.
|
||||
|
||||
While here, also fix DIE_{ID,REV} inconsistent indentation.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230406194158.963352-6-cristian.ciocaltea@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/fan53555.c | 18 +++++++++---------
|
||||
1 file changed, 9 insertions(+), 9 deletions(-)
|
||||
|
||||
--- a/drivers/regulator/fan53555.c
|
||||
+++ b/drivers/regulator/fan53555.c
|
||||
@@ -41,23 +41,23 @@
|
||||
#define FAN53555_MONITOR 0x05
|
||||
|
||||
/* VSEL bit definitions */
|
||||
-#define VSEL_BUCK_EN (1 << 7)
|
||||
-#define VSEL_MODE (1 << 6)
|
||||
+#define VSEL_BUCK_EN BIT(7)
|
||||
+#define VSEL_MODE BIT(6)
|
||||
/* Chip ID and Verison */
|
||||
-#define DIE_ID 0x0F /* ID1 */
|
||||
-#define DIE_REV 0x0F /* ID2 */
|
||||
+#define DIE_ID 0x0F /* ID1 */
|
||||
+#define DIE_REV 0x0F /* ID2 */
|
||||
/* Control bit definitions */
|
||||
-#define CTL_OUTPUT_DISCHG (1 << 7)
|
||||
-#define CTL_SLEW_MASK (0x7 << 4)
|
||||
-#define CTL_RESET (1 << 2)
|
||||
+#define CTL_OUTPUT_DISCHG BIT(7)
|
||||
+#define CTL_SLEW_MASK GENMASK(6, 4)
|
||||
+#define CTL_RESET BIT(2)
|
||||
#define CTL_MODE_VSEL0_MODE BIT(0)
|
||||
#define CTL_MODE_VSEL1_MODE BIT(1)
|
||||
|
||||
#define FAN53555_NVOLTAGES 64 /* Numbers of voltages */
|
||||
#define FAN53526_NVOLTAGES 128
|
||||
|
||||
-#define TCS_VSEL0_MODE (1 << 7)
|
||||
-#define TCS_VSEL1_MODE (1 << 6)
|
||||
+#define TCS_VSEL0_MODE BIT(7)
|
||||
+#define TCS_VSEL1_MODE BIT(6)
|
||||
|
||||
#define TCS_SLEW_MASK GENMASK(4, 3)
|
||||
|
||||
@ -1,39 +0,0 @@
|
||||
From 6bb18339c6b54e0241344280fe4d14909db9356c Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Thu, 6 Apr 2023 22:41:56 +0300
|
||||
Subject: [PATCH] regulator: fan53555: Improve vsel_mask computation
|
||||
|
||||
In preparation for introducing support for additional regulators which
|
||||
do not use the maximum number of voltage selectors available for a given
|
||||
mask, improve the mask computation formula by using fls().
|
||||
|
||||
Note fls() requires the bitops header, hence include it explicitly and
|
||||
drop bits.h which is already pulled by bitops.h.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230406194158.963352-7-cristian.ciocaltea@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/fan53555.c | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/regulator/fan53555.c
|
||||
+++ b/drivers/regulator/fan53555.c
|
||||
@@ -8,7 +8,7 @@
|
||||
// Copyright (c) 2012 Marvell Technology Ltd.
|
||||
// Yunfan Zhang <yfzhang@marvell.com>
|
||||
|
||||
-#include <linux/bits.h>
|
||||
+#include <linux/bitops.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/module.h>
|
||||
@@ -486,7 +486,7 @@ static int fan53555_regulator_register(s
|
||||
rdesc->min_uV = di->vsel_min;
|
||||
rdesc->uV_step = di->vsel_step;
|
||||
rdesc->vsel_reg = di->vol_reg;
|
||||
- rdesc->vsel_mask = di->vsel_count - 1;
|
||||
+ rdesc->vsel_mask = BIT(fls(di->vsel_count - 1)) - 1;
|
||||
rdesc->ramp_reg = di->slew_reg;
|
||||
rdesc->ramp_mask = di->slew_mask;
|
||||
rdesc->ramp_delay_table = di->ramp_delay_table;
|
||||
@ -1,106 +0,0 @@
|
||||
From 2c82f5b8ae6d0b5bbac1526021d9c3120d183555 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Thu, 6 Apr 2023 22:41:57 +0300
|
||||
Subject: [PATCH] regulator: fan53555: Use dev_err_probe
|
||||
|
||||
Use dev_err_probe() instead of dev_err() in the probe function, which
|
||||
ensures the error code is always printed and, additionally, simplifies
|
||||
the code a bit.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230406194158.963352-8-cristian.ciocaltea@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/fan53555.c | 47 ++++++++++++++++--------------------
|
||||
1 file changed, 21 insertions(+), 26 deletions(-)
|
||||
|
||||
--- a/drivers/regulator/fan53555.c
|
||||
+++ b/drivers/regulator/fan53555.c
|
||||
@@ -568,10 +568,9 @@ static int fan53555_regulator_probe(stru
|
||||
if (!pdata)
|
||||
pdata = fan53555_parse_dt(&client->dev, np, &di->desc);
|
||||
|
||||
- if (!pdata || !pdata->regulator) {
|
||||
- dev_err(&client->dev, "Platform data not found!\n");
|
||||
- return -ENODEV;
|
||||
- }
|
||||
+ if (!pdata || !pdata->regulator)
|
||||
+ return dev_err_probe(&client->dev, -ENODEV,
|
||||
+ "Platform data not found!\n");
|
||||
|
||||
di->regulator = pdata->regulator;
|
||||
if (client->dev.of_node) {
|
||||
@@ -580,10 +579,9 @@ static int fan53555_regulator_probe(stru
|
||||
} else {
|
||||
/* if no ramp constraint set, get the pdata ramp_delay */
|
||||
if (!di->regulator->constraints.ramp_delay) {
|
||||
- if (pdata->slew_rate >= ARRAY_SIZE(slew_rates)) {
|
||||
- dev_err(&client->dev, "Invalid slew_rate\n");
|
||||
- return -EINVAL;
|
||||
- }
|
||||
+ if (pdata->slew_rate >= ARRAY_SIZE(slew_rates))
|
||||
+ return dev_err_probe(&client->dev, -EINVAL,
|
||||
+ "Invalid slew_rate\n");
|
||||
|
||||
di->regulator->constraints.ramp_delay
|
||||
= slew_rates[pdata->slew_rate];
|
||||
@@ -593,34 +591,31 @@ static int fan53555_regulator_probe(stru
|
||||
}
|
||||
|
||||
regmap = devm_regmap_init_i2c(client, &fan53555_regmap_config);
|
||||
- if (IS_ERR(regmap)) {
|
||||
- dev_err(&client->dev, "Failed to allocate regmap!\n");
|
||||
- return PTR_ERR(regmap);
|
||||
- }
|
||||
+ if (IS_ERR(regmap))
|
||||
+ return dev_err_probe(&client->dev, PTR_ERR(regmap),
|
||||
+ "Failed to allocate regmap!\n");
|
||||
+
|
||||
di->dev = &client->dev;
|
||||
i2c_set_clientdata(client, di);
|
||||
/* Get chip ID */
|
||||
ret = regmap_read(regmap, FAN53555_ID1, &val);
|
||||
- if (ret < 0) {
|
||||
- dev_err(&client->dev, "Failed to get chip ID!\n");
|
||||
- return ret;
|
||||
- }
|
||||
+ if (ret < 0)
|
||||
+ return dev_err_probe(&client->dev, ret, "Failed to get chip ID!\n");
|
||||
+
|
||||
di->chip_id = val & DIE_ID;
|
||||
/* Get chip revision */
|
||||
ret = regmap_read(regmap, FAN53555_ID2, &val);
|
||||
- if (ret < 0) {
|
||||
- dev_err(&client->dev, "Failed to get chip Rev!\n");
|
||||
- return ret;
|
||||
- }
|
||||
+ if (ret < 0)
|
||||
+ return dev_err_probe(&client->dev, ret, "Failed to get chip Rev!\n");
|
||||
+
|
||||
di->chip_rev = val & DIE_REV;
|
||||
dev_info(&client->dev, "FAN53555 Option[%d] Rev[%d] Detected!\n",
|
||||
di->chip_id, di->chip_rev);
|
||||
/* Device init */
|
||||
ret = fan53555_device_setup(di, pdata);
|
||||
- if (ret < 0) {
|
||||
- dev_err(&client->dev, "Failed to setup device!\n");
|
||||
- return ret;
|
||||
- }
|
||||
+ if (ret < 0)
|
||||
+ return dev_err_probe(&client->dev, ret, "Failed to setup device!\n");
|
||||
+
|
||||
/* Register regulator */
|
||||
config.dev = di->dev;
|
||||
config.init_data = di->regulator;
|
||||
@@ -630,9 +625,9 @@ static int fan53555_regulator_probe(stru
|
||||
|
||||
ret = fan53555_regulator_register(di, &config);
|
||||
if (ret < 0)
|
||||
- dev_err(&client->dev, "Failed to register regulator!\n");
|
||||
- return ret;
|
||||
+ dev_err_probe(&client->dev, ret, "Failed to register regulator!\n");
|
||||
|
||||
+ return ret;
|
||||
}
|
||||
|
||||
static const struct i2c_device_id fan53555_id[] = {
|
||||
@ -1,263 +0,0 @@
|
||||
From a27e71a66ee0f887fefcc31b85a804b0905fa865 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Thu, 6 Apr 2023 22:41:58 +0300
|
||||
Subject: [PATCH] regulator: fan53555: Add support for RK860X
|
||||
|
||||
Extend the existing fan53555 driver to support the Rockchip RK860X
|
||||
regulators.
|
||||
|
||||
RK8600/RK8601 are pretty similar to the FAN53555 regulators.
|
||||
|
||||
RK8602/RK8603 are a bit different, having a wider output voltage
|
||||
selection range, from 0.5 V to 1.5 V in 6.25 mV steps. They also use
|
||||
additional VSEL0/VSEL1 registers for the voltage selector, but the
|
||||
enable and mode bits are still located in the original FAN53555 specific
|
||||
VSEL0/VSEL1 registers.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230406194158.963352-9-cristian.ciocaltea@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
drivers/regulator/fan53555.c | 121 ++++++++++++++++++++++++++++++++++-
|
||||
1 file changed, 118 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/regulator/fan53555.c
|
||||
+++ b/drivers/regulator/fan53555.c
|
||||
@@ -26,6 +26,9 @@
|
||||
#define FAN53555_VSEL0 0x00
|
||||
#define FAN53555_VSEL1 0x01
|
||||
|
||||
+#define RK8602_VSEL0 0x06
|
||||
+#define RK8602_VSEL1 0x07
|
||||
+
|
||||
#define TCS4525_VSEL0 0x11
|
||||
#define TCS4525_VSEL1 0x10
|
||||
#define TCS4525_TIME 0x13
|
||||
@@ -55,6 +58,7 @@
|
||||
|
||||
#define FAN53555_NVOLTAGES 64 /* Numbers of voltages */
|
||||
#define FAN53526_NVOLTAGES 128
|
||||
+#define RK8602_NVOLTAGES 160
|
||||
|
||||
#define TCS_VSEL0_MODE BIT(7)
|
||||
#define TCS_VSEL1_MODE BIT(6)
|
||||
@@ -64,6 +68,8 @@
|
||||
enum fan53555_vendor {
|
||||
FAN53526_VENDOR_FAIRCHILD = 0,
|
||||
FAN53555_VENDOR_FAIRCHILD,
|
||||
+ FAN53555_VENDOR_ROCKCHIP, /* RK8600, RK8601 */
|
||||
+ RK8602_VENDOR_ROCKCHIP, /* RK8602, RK8603 */
|
||||
FAN53555_VENDOR_SILERGY,
|
||||
FAN53526_VENDOR_TCS,
|
||||
};
|
||||
@@ -88,6 +94,14 @@ enum {
|
||||
};
|
||||
|
||||
enum {
|
||||
+ RK8600_CHIP_ID_08 = 8, /* RK8600, RK8601 */
|
||||
+};
|
||||
+
|
||||
+enum {
|
||||
+ RK8602_CHIP_ID_10 = 10, /* RK8602, RK8603 */
|
||||
+};
|
||||
+
|
||||
+enum {
|
||||
TCS4525_CHIP_ID_12 = 12,
|
||||
};
|
||||
|
||||
@@ -117,6 +131,8 @@ struct fan53555_device_info {
|
||||
/* Voltage setting register */
|
||||
unsigned int vol_reg;
|
||||
unsigned int sleep_reg;
|
||||
+ unsigned int en_reg;
|
||||
+ unsigned int sleep_en_reg;
|
||||
/* Voltage range and step(linear) */
|
||||
unsigned int vsel_min;
|
||||
unsigned int vsel_step;
|
||||
@@ -159,7 +175,7 @@ static int fan53555_set_suspend_enable(s
|
||||
{
|
||||
struct fan53555_device_info *di = rdev_get_drvdata(rdev);
|
||||
|
||||
- return regmap_update_bits(rdev->regmap, di->sleep_reg,
|
||||
+ return regmap_update_bits(rdev->regmap, di->sleep_en_reg,
|
||||
VSEL_BUCK_EN, VSEL_BUCK_EN);
|
||||
}
|
||||
|
||||
@@ -167,7 +183,7 @@ static int fan53555_set_suspend_disable(
|
||||
{
|
||||
struct fan53555_device_info *di = rdev_get_drvdata(rdev);
|
||||
|
||||
- return regmap_update_bits(rdev->regmap, di->sleep_reg,
|
||||
+ return regmap_update_bits(rdev->regmap, di->sleep_en_reg,
|
||||
VSEL_BUCK_EN, 0);
|
||||
}
|
||||
|
||||
@@ -317,6 +333,50 @@ static int fan53555_voltages_setup_fairc
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int fan53555_voltages_setup_rockchip(struct fan53555_device_info *di)
|
||||
+{
|
||||
+ /* Init voltage range and step */
|
||||
+ switch (di->chip_id) {
|
||||
+ case RK8600_CHIP_ID_08:
|
||||
+ di->vsel_min = 712500;
|
||||
+ di->vsel_step = 12500;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(di->dev,
|
||||
+ "Chip ID %d not supported!\n", di->chip_id);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ di->slew_reg = FAN53555_CONTROL;
|
||||
+ di->slew_mask = CTL_SLEW_MASK;
|
||||
+ di->ramp_delay_table = slew_rates;
|
||||
+ di->n_ramp_values = ARRAY_SIZE(slew_rates);
|
||||
+ di->vsel_count = FAN53555_NVOLTAGES;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static int rk8602_voltages_setup_rockchip(struct fan53555_device_info *di)
|
||||
+{
|
||||
+ /* Init voltage range and step */
|
||||
+ switch (di->chip_id) {
|
||||
+ case RK8602_CHIP_ID_10:
|
||||
+ di->vsel_min = 500000;
|
||||
+ di->vsel_step = 6250;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(di->dev,
|
||||
+ "Chip ID %d not supported!\n", di->chip_id);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+ di->slew_reg = FAN53555_CONTROL;
|
||||
+ di->slew_mask = CTL_SLEW_MASK;
|
||||
+ di->ramp_delay_table = slew_rates;
|
||||
+ di->n_ramp_values = ARRAY_SIZE(slew_rates);
|
||||
+ di->vsel_count = RK8602_NVOLTAGES;
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di)
|
||||
{
|
||||
/* Init voltage range and step */
|
||||
@@ -377,6 +437,7 @@ static int fan53555_device_setup(struct
|
||||
switch (di->vendor) {
|
||||
case FAN53526_VENDOR_FAIRCHILD:
|
||||
case FAN53555_VENDOR_FAIRCHILD:
|
||||
+ case FAN53555_VENDOR_ROCKCHIP:
|
||||
case FAN53555_VENDOR_SILERGY:
|
||||
switch (pdata->sleep_vsel_id) {
|
||||
case FAN53555_VSEL_ID_0:
|
||||
@@ -391,6 +452,27 @@ static int fan53555_device_setup(struct
|
||||
dev_err(di->dev, "Invalid VSEL ID!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
+ di->sleep_en_reg = di->sleep_reg;
|
||||
+ di->en_reg = di->vol_reg;
|
||||
+ break;
|
||||
+ case RK8602_VENDOR_ROCKCHIP:
|
||||
+ switch (pdata->sleep_vsel_id) {
|
||||
+ case FAN53555_VSEL_ID_0:
|
||||
+ di->sleep_reg = RK8602_VSEL0;
|
||||
+ di->vol_reg = RK8602_VSEL1;
|
||||
+ di->sleep_en_reg = FAN53555_VSEL0;
|
||||
+ di->en_reg = FAN53555_VSEL1;
|
||||
+ break;
|
||||
+ case FAN53555_VSEL_ID_1:
|
||||
+ di->sleep_reg = RK8602_VSEL1;
|
||||
+ di->vol_reg = RK8602_VSEL0;
|
||||
+ di->sleep_en_reg = FAN53555_VSEL1;
|
||||
+ di->en_reg = FAN53555_VSEL0;
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(di->dev, "Invalid VSEL ID!\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
break;
|
||||
case FAN53526_VENDOR_TCS:
|
||||
switch (pdata->sleep_vsel_id) {
|
||||
@@ -406,6 +488,8 @@ static int fan53555_device_setup(struct
|
||||
dev_err(di->dev, "Invalid VSEL ID!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
+ di->sleep_en_reg = di->sleep_reg;
|
||||
+ di->en_reg = di->vol_reg;
|
||||
break;
|
||||
default:
|
||||
dev_err(di->dev, "vendor %d not supported!\n", di->vendor);
|
||||
@@ -427,10 +511,23 @@ static int fan53555_device_setup(struct
|
||||
}
|
||||
break;
|
||||
case FAN53555_VENDOR_FAIRCHILD:
|
||||
+ case FAN53555_VENDOR_ROCKCHIP:
|
||||
case FAN53555_VENDOR_SILERGY:
|
||||
di->mode_reg = di->vol_reg;
|
||||
di->mode_mask = VSEL_MODE;
|
||||
break;
|
||||
+ case RK8602_VENDOR_ROCKCHIP:
|
||||
+ di->mode_mask = VSEL_MODE;
|
||||
+
|
||||
+ switch (pdata->sleep_vsel_id) {
|
||||
+ case FAN53555_VSEL_ID_0:
|
||||
+ di->mode_reg = FAN53555_VSEL1;
|
||||
+ break;
|
||||
+ case FAN53555_VSEL_ID_1:
|
||||
+ di->mode_reg = FAN53555_VSEL0;
|
||||
+ break;
|
||||
+ }
|
||||
+ break;
|
||||
case FAN53526_VENDOR_TCS:
|
||||
di->mode_reg = TCS4525_COMMAND;
|
||||
|
||||
@@ -456,6 +553,12 @@ static int fan53555_device_setup(struct
|
||||
case FAN53555_VENDOR_FAIRCHILD:
|
||||
ret = fan53555_voltages_setup_fairchild(di);
|
||||
break;
|
||||
+ case FAN53555_VENDOR_ROCKCHIP:
|
||||
+ ret = fan53555_voltages_setup_rockchip(di);
|
||||
+ break;
|
||||
+ case RK8602_VENDOR_ROCKCHIP:
|
||||
+ ret = rk8602_voltages_setup_rockchip(di);
|
||||
+ break;
|
||||
case FAN53555_VENDOR_SILERGY:
|
||||
ret = fan53555_voltages_setup_silergy(di);
|
||||
break;
|
||||
@@ -481,7 +584,7 @@ static int fan53555_regulator_register(s
|
||||
rdesc->ops = &fan53555_regulator_ops;
|
||||
rdesc->type = REGULATOR_VOLTAGE;
|
||||
rdesc->n_voltages = di->vsel_count;
|
||||
- rdesc->enable_reg = di->vol_reg;
|
||||
+ rdesc->enable_reg = di->en_reg;
|
||||
rdesc->enable_mask = VSEL_BUCK_EN;
|
||||
rdesc->min_uV = di->vsel_min;
|
||||
rdesc->uV_step = di->vsel_step;
|
||||
@@ -532,6 +635,12 @@ static const struct of_device_id __maybe
|
||||
.compatible = "fcs,fan53555",
|
||||
.data = (void *)FAN53555_VENDOR_FAIRCHILD
|
||||
}, {
|
||||
+ .compatible = "rockchip,rk8600",
|
||||
+ .data = (void *)FAN53555_VENDOR_ROCKCHIP
|
||||
+ }, {
|
||||
+ .compatible = "rockchip,rk8602",
|
||||
+ .data = (void *)RK8602_VENDOR_ROCKCHIP
|
||||
+ }, {
|
||||
.compatible = "silergy,syr827",
|
||||
.data = (void *)FAN53555_VENDOR_SILERGY,
|
||||
}, {
|
||||
@@ -638,6 +747,12 @@ static const struct i2c_device_id fan535
|
||||
.name = "fan53555",
|
||||
.driver_data = FAN53555_VENDOR_FAIRCHILD
|
||||
}, {
|
||||
+ .name = "rk8600",
|
||||
+ .driver_data = FAN53555_VENDOR_ROCKCHIP
|
||||
+ }, {
|
||||
+ .name = "rk8602",
|
||||
+ .driver_data = RK8602_VENDOR_ROCKCHIP
|
||||
+ }, {
|
||||
.name = "syr827",
|
||||
.driver_data = FAN53555_VENDOR_SILERGY
|
||||
}, {
|
||||
@ -1,44 +0,0 @@
|
||||
From f1d2427cb458fd8ecb709c27f43088d6e250a7aa Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Wed, 8 Mar 2023 12:22:47 +0100
|
||||
Subject: [PATCH] thermal/drivers/rockchip: Simplify getting match data
|
||||
|
||||
It's possible to directly get the match data in a generic
|
||||
way nowadays.
|
||||
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230308112253.15659-2-sebastian.reichel@collabora.com
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 7 +------
|
||||
1 file changed, 1 insertion(+), 6 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -1353,16 +1353,11 @@ static int rockchip_thermal_probe(struct
|
||||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct rockchip_thermal_data *thermal;
|
||||
- const struct of_device_id *match;
|
||||
struct resource *res;
|
||||
int irq;
|
||||
int i;
|
||||
int error;
|
||||
|
||||
- match = of_match_node(of_rockchip_thermal_match, np);
|
||||
- if (!match)
|
||||
- return -ENXIO;
|
||||
-
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return -EINVAL;
|
||||
@@ -1374,7 +1369,7 @@ static int rockchip_thermal_probe(struct
|
||||
|
||||
thermal->pdev = pdev;
|
||||
|
||||
- thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
|
||||
+ thermal->chip = device_get_match_data(&pdev->dev);
|
||||
if (!thermal->chip)
|
||||
return -EINVAL;
|
||||
|
||||
@ -1,106 +0,0 @@
|
||||
From 2f6916f12c0e46ecd4c2b793a014132140730560 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Wed, 8 Mar 2023 12:22:48 +0100
|
||||
Subject: [PATCH] thermal/drivers/rockchip: Simplify clock logic
|
||||
|
||||
By using devm_clk_get_enabled() the clock acquisition and
|
||||
enabling can be done in one step with automatic error
|
||||
handling.
|
||||
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230308112253.15659-3-sebastian.reichel@collabora.com
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 33 +++++-------------------------
|
||||
1 file changed, 5 insertions(+), 28 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -1385,14 +1385,14 @@ static int rockchip_thermal_probe(struct
|
||||
return error;
|
||||
}
|
||||
|
||||
- thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
|
||||
+ thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc");
|
||||
if (IS_ERR(thermal->clk)) {
|
||||
error = PTR_ERR(thermal->clk);
|
||||
dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
|
||||
return error;
|
||||
}
|
||||
|
||||
- thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
|
||||
+ thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
|
||||
if (IS_ERR(thermal->pclk)) {
|
||||
error = PTR_ERR(thermal->pclk);
|
||||
dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
|
||||
@@ -1400,26 +1400,13 @@ static int rockchip_thermal_probe(struct
|
||||
return error;
|
||||
}
|
||||
|
||||
- error = clk_prepare_enable(thermal->clk);
|
||||
- if (error) {
|
||||
- dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
|
||||
- error);
|
||||
- return error;
|
||||
- }
|
||||
-
|
||||
- error = clk_prepare_enable(thermal->pclk);
|
||||
- if (error) {
|
||||
- dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
|
||||
- goto err_disable_clk;
|
||||
- }
|
||||
-
|
||||
rockchip_thermal_reset_controller(thermal->reset);
|
||||
|
||||
error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
|
||||
if (error) {
|
||||
dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
|
||||
error);
|
||||
- goto err_disable_pclk;
|
||||
+ return error;
|
||||
}
|
||||
|
||||
thermal->chip->initialize(thermal->grf, thermal->regs,
|
||||
@@ -1433,7 +1420,7 @@ static int rockchip_thermal_probe(struct
|
||||
dev_err(&pdev->dev,
|
||||
"failed to register sensor[%d] : error = %d\n",
|
||||
i, error);
|
||||
- goto err_disable_pclk;
|
||||
+ return error;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1444,7 +1431,7 @@ static int rockchip_thermal_probe(struct
|
||||
if (error) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to request tsadc irq: %d\n", error);
|
||||
- goto err_disable_pclk;
|
||||
+ return error;
|
||||
}
|
||||
|
||||
thermal->chip->control(thermal->regs, true);
|
||||
@@ -1462,13 +1449,6 @@ static int rockchip_thermal_probe(struct
|
||||
platform_set_drvdata(pdev, thermal);
|
||||
|
||||
return 0;
|
||||
-
|
||||
-err_disable_pclk:
|
||||
- clk_disable_unprepare(thermal->pclk);
|
||||
-err_disable_clk:
|
||||
- clk_disable_unprepare(thermal->clk);
|
||||
-
|
||||
- return error;
|
||||
}
|
||||
|
||||
static int rockchip_thermal_remove(struct platform_device *pdev)
|
||||
@@ -1485,9 +1465,6 @@ static int rockchip_thermal_remove(struc
|
||||
|
||||
thermal->chip->control(thermal->regs, false);
|
||||
|
||||
- clk_disable_unprepare(thermal->pclk);
|
||||
- clk_disable_unprepare(thermal->clk);
|
||||
-
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -1,96 +0,0 @@
|
||||
From cb71c5f904c5b7e84d770c87bebc5df0bec200a4 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Wed, 8 Mar 2023 12:22:49 +0100
|
||||
Subject: [PATCH] thermal/drivers/rockchip: Use dev_err_probe
|
||||
|
||||
Use dev_err_probe to simplify error printing in the driver's probe
|
||||
routine.
|
||||
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230308112253.15659-4-sebastian.reichel@collabora.com
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 50 +++++++++++-------------------
|
||||
1 file changed, 18 insertions(+), 32 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -1379,35 +1379,26 @@ static int rockchip_thermal_probe(struct
|
||||
return PTR_ERR(thermal->regs);
|
||||
|
||||
thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
|
||||
- if (IS_ERR(thermal->reset)) {
|
||||
- error = PTR_ERR(thermal->reset);
|
||||
- dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
|
||||
- return error;
|
||||
- }
|
||||
+ if (IS_ERR(thermal->reset))
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset),
|
||||
+ "failed to get tsadc reset.\n");
|
||||
|
||||
thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc");
|
||||
- if (IS_ERR(thermal->clk)) {
|
||||
- error = PTR_ERR(thermal->clk);
|
||||
- dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
|
||||
- return error;
|
||||
- }
|
||||
+ if (IS_ERR(thermal->clk))
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk),
|
||||
+ "failed to get tsadc clock.\n");
|
||||
|
||||
thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
|
||||
- if (IS_ERR(thermal->pclk)) {
|
||||
- error = PTR_ERR(thermal->pclk);
|
||||
- dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
|
||||
- error);
|
||||
- return error;
|
||||
- }
|
||||
+ if (IS_ERR(thermal->pclk))
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk),
|
||||
+ "failed to get apb_pclk clock.\n");
|
||||
|
||||
rockchip_thermal_reset_controller(thermal->reset);
|
||||
|
||||
error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
|
||||
- if (error) {
|
||||
- dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
|
||||
- error);
|
||||
- return error;
|
||||
- }
|
||||
+ if (error)
|
||||
+ return dev_err_probe(&pdev->dev, error,
|
||||
+ "failed to parse device tree data\n");
|
||||
|
||||
thermal->chip->initialize(thermal->grf, thermal->regs,
|
||||
thermal->tshut_polarity);
|
||||
@@ -1416,23 +1407,18 @@ static int rockchip_thermal_probe(struct
|
||||
error = rockchip_thermal_register_sensor(pdev, thermal,
|
||||
&thermal->sensors[i],
|
||||
thermal->chip->chn_id[i]);
|
||||
- if (error) {
|
||||
- dev_err(&pdev->dev,
|
||||
- "failed to register sensor[%d] : error = %d\n",
|
||||
- i, error);
|
||||
- return error;
|
||||
- }
|
||||
+ if (error)
|
||||
+ return dev_err_probe(&pdev->dev, error,
|
||||
+ "failed to register sensor[%d].\n", i);
|
||||
}
|
||||
|
||||
error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
|
||||
&rockchip_thermal_alarm_irq_thread,
|
||||
IRQF_ONESHOT,
|
||||
"rockchip_thermal", thermal);
|
||||
- if (error) {
|
||||
- dev_err(&pdev->dev,
|
||||
- "failed to request tsadc irq: %d\n", error);
|
||||
- return error;
|
||||
- }
|
||||
+ if (error)
|
||||
+ return dev_err_probe(&pdev->dev, error,
|
||||
+ "failed to request tsadc irq.\n");
|
||||
|
||||
thermal->chip->control(thermal->regs, true);
|
||||
|
||||
@ -1,157 +0,0 @@
|
||||
From f7cef1b743e84bdc7b1f2e5711615aaddf101ca8 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Wed, 8 Mar 2023 12:22:50 +0100
|
||||
Subject: [PATCH] thermal/drivers/rockchip: Simplify channel id logic
|
||||
|
||||
Replace the channel ID lookup table by a simple offset, since
|
||||
the channel IDs are consecutive.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Link: https://lore.kernel.org/r/20230308112253.15659-5-sebastian.reichel@collabora.com
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 48 +++++++++++++-----------------
|
||||
1 file changed, 21 insertions(+), 27 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -40,15 +40,6 @@ enum tshut_polarity {
|
||||
};
|
||||
|
||||
/*
|
||||
- * The system has two Temperature Sensors.
|
||||
- * sensor0 is for CPU, and sensor1 is for GPU.
|
||||
- */
|
||||
-enum sensor_id {
|
||||
- SENSOR_CPU = 0,
|
||||
- SENSOR_GPU,
|
||||
-};
|
||||
-
|
||||
-/*
|
||||
* The conversion table has the adc value and temperature.
|
||||
* ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
|
||||
* ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
|
||||
@@ -82,7 +73,7 @@ struct chip_tsadc_table {
|
||||
|
||||
/**
|
||||
* struct rockchip_tsadc_chip - hold the private data of tsadc chip
|
||||
- * @chn_id: array of sensor ids of chip corresponding to the channel
|
||||
+ * @chn_offset: the channel offset of the first channel
|
||||
* @chn_num: the channel number of tsadc chip
|
||||
* @tshut_temp: the hardware-controlled shutdown temperature value
|
||||
* @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
|
||||
@@ -98,7 +89,7 @@ struct chip_tsadc_table {
|
||||
*/
|
||||
struct rockchip_tsadc_chip {
|
||||
/* The sensor id of chip correspond to the ADC channel */
|
||||
- int chn_id[SOC_MAX_SENSORS];
|
||||
+ int chn_offset;
|
||||
int chn_num;
|
||||
|
||||
/* The hardware-controlled tshut property */
|
||||
@@ -925,8 +916,8 @@ static void rk_tsadcv2_tshut_mode(int ch
|
||||
}
|
||||
|
||||
static const struct rockchip_tsadc_chip px30_tsadc_data = {
|
||||
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
||||
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
||||
+ /* cpu, gpu */
|
||||
+ .chn_offset = 0,
|
||||
.chn_num = 2, /* 2 channels for tsadc */
|
||||
|
||||
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
|
||||
@@ -949,7 +940,8 @@ static const struct rockchip_tsadc_chip
|
||||
};
|
||||
|
||||
static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
|
||||
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
||||
+ /* cpu */
|
||||
+ .chn_offset = 0,
|
||||
.chn_num = 1, /* one channel for tsadc */
|
||||
|
||||
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
||||
@@ -973,7 +965,8 @@ static const struct rockchip_tsadc_chip
|
||||
};
|
||||
|
||||
static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
|
||||
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
||||
+ /* cpu */
|
||||
+ .chn_offset = 0,
|
||||
.chn_num = 1, /* one channel for tsadc */
|
||||
|
||||
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
||||
@@ -997,8 +990,8 @@ static const struct rockchip_tsadc_chip
|
||||
};
|
||||
|
||||
static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
|
||||
- .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
|
||||
- .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
|
||||
+ /* cpu, gpu */
|
||||
+ .chn_offset = 1,
|
||||
.chn_num = 2, /* two channels for tsadc */
|
||||
|
||||
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
||||
@@ -1022,7 +1015,8 @@ static const struct rockchip_tsadc_chip
|
||||
};
|
||||
|
||||
static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
|
||||
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
||||
+ /* cpu */
|
||||
+ .chn_offset = 0,
|
||||
.chn_num = 1, /* one channels for tsadc */
|
||||
|
||||
.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
|
||||
@@ -1045,8 +1039,8 @@ static const struct rockchip_tsadc_chip
|
||||
};
|
||||
|
||||
static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
|
||||
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
||||
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
||||
+ /* cpu, gpu */
|
||||
+ .chn_offset = 0,
|
||||
.chn_num = 2, /* two channels for tsadc */
|
||||
|
||||
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
||||
@@ -1070,8 +1064,8 @@ static const struct rockchip_tsadc_chip
|
||||
};
|
||||
|
||||
static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
|
||||
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
||||
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
||||
+ /* cpu, gpu */
|
||||
+ .chn_offset = 0,
|
||||
.chn_num = 2, /* two channels for tsadc */
|
||||
|
||||
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
||||
@@ -1095,8 +1089,8 @@ static const struct rockchip_tsadc_chip
|
||||
};
|
||||
|
||||
static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
|
||||
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
||||
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
||||
+ /* cpu, gpu */
|
||||
+ .chn_offset = 0,
|
||||
.chn_num = 2, /* two channels for tsadc */
|
||||
|
||||
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
||||
@@ -1120,8 +1114,8 @@ static const struct rockchip_tsadc_chip
|
||||
};
|
||||
|
||||
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
|
||||
- .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
|
||||
- .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
|
||||
+ /* cpu, gpu */
|
||||
+ .chn_offset = 0,
|
||||
.chn_num = 2, /* two channels for tsadc */
|
||||
|
||||
.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
||||
@@ -1406,7 +1400,7 @@ static int rockchip_thermal_probe(struct
|
||||
for (i = 0; i < thermal->chip->chn_num; i++) {
|
||||
error = rockchip_thermal_register_sensor(pdev, thermal,
|
||||
&thermal->sensors[i],
|
||||
- thermal->chip->chn_id[i]);
|
||||
+ thermal->chip->chn_offset + i);
|
||||
if (error)
|
||||
return dev_err_probe(&pdev->dev, error,
|
||||
"failed to register sensor[%d].\n", i);
|
||||
@ -1,53 +0,0 @@
|
||||
From 267f596585abc78efbdda51a80dd36c65c0f6ad0 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Wed, 8 Mar 2023 12:22:51 +0100
|
||||
Subject: [PATCH] thermal/drivers/rockchip: Support dynamic sized sensor array
|
||||
|
||||
Dynamically allocate the sensors array based on the amount
|
||||
of platform sensors in preparation for rk3588 support, which
|
||||
needs 7 sensors.
|
||||
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230308112253.15659-6-sebastian.reichel@collabora.com
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 13 ++++++-------
|
||||
1 file changed, 6 insertions(+), 7 deletions(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -52,12 +52,6 @@ enum adc_sort_mode {
|
||||
#include "thermal_hwmon.h"
|
||||
|
||||
/**
|
||||
- * The max sensors is two in rockchip SoCs.
|
||||
- * Two sensors: CPU and GPU sensor.
|
||||
- */
|
||||
-#define SOC_MAX_SENSORS 2
|
||||
-
|
||||
-/**
|
||||
* struct chip_tsadc_table - hold information about chip-specific differences
|
||||
* @id: conversion table
|
||||
* @length: size of conversion table
|
||||
@@ -147,7 +141,7 @@ struct rockchip_thermal_data {
|
||||
struct platform_device *pdev;
|
||||
struct reset_control *reset;
|
||||
|
||||
- struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
|
||||
+ struct rockchip_thermal_sensor *sensors;
|
||||
|
||||
struct clk *clk;
|
||||
struct clk *pclk;
|
||||
@@ -1367,6 +1361,11 @@ static int rockchip_thermal_probe(struct
|
||||
if (!thermal->chip)
|
||||
return -EINVAL;
|
||||
|
||||
+ thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num,
|
||||
+ sizeof(*thermal->sensors), GFP_KERNEL);
|
||||
+ if (!thermal->sensors)
|
||||
+ return -ENOMEM;
|
||||
+
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
thermal->regs = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(thermal->regs))
|
||||
@ -1,319 +0,0 @@
|
||||
From 45d7b3867a5cabb97fc31f16122cda8540c3a30c Mon Sep 17 00:00:00 2001
|
||||
From: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
Date: Wed, 8 Mar 2023 12:22:52 +0100
|
||||
Subject: [PATCH] thermal/drivers/rockchip: Support RK3588 SoC in the thermal
|
||||
driver
|
||||
|
||||
The RK3588 SoC has seven temperature sensor ADC channels:
|
||||
|
||||
- Chip Center
|
||||
- CPU Cluster 1 (Dual A76 "Big" Cores)
|
||||
- CPU Cluster 2 (Dual A76 "Big" Cores)
|
||||
- CPU Cluster 0 (Quad A55 "Little" Cores)
|
||||
- Power Domain Center
|
||||
- Graphics Processing Unit
|
||||
- Neural Processing Unit
|
||||
|
||||
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
|
||||
[rebase, squash fixes]
|
||||
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/20230308112253.15659-7-sebastian.reichel@collabora.com
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 177 +++++++++++++++++++++++++++++
|
||||
1 file changed, 177 insertions(+)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -165,29 +165,49 @@ struct rockchip_thermal_data {
|
||||
#define TSADCV2_AUTO_CON 0x04
|
||||
#define TSADCV2_INT_EN 0x08
|
||||
#define TSADCV2_INT_PD 0x0c
|
||||
+#define TSADCV3_AUTO_SRC_CON 0x0c
|
||||
+#define TSADCV3_HT_INT_EN 0x14
|
||||
+#define TSADCV3_HSHUT_GPIO_INT_EN 0x18
|
||||
+#define TSADCV3_HSHUT_CRU_INT_EN 0x1c
|
||||
+#define TSADCV3_INT_PD 0x24
|
||||
+#define TSADCV3_HSHUT_PD 0x28
|
||||
#define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
|
||||
#define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
|
||||
#define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
|
||||
+#define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
|
||||
+#define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
|
||||
+#define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
|
||||
#define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
|
||||
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
|
||||
+#define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
|
||||
+#define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
|
||||
#define TSADCV2_AUTO_PERIOD 0x68
|
||||
#define TSADCV2_AUTO_PERIOD_HT 0x6c
|
||||
+#define TSADCV3_AUTO_PERIOD 0x154
|
||||
+#define TSADCV3_AUTO_PERIOD_HT 0x158
|
||||
|
||||
#define TSADCV2_AUTO_EN BIT(0)
|
||||
+#define TSADCV2_AUTO_EN_MASK BIT(16)
|
||||
#define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
|
||||
+#define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
|
||||
+#define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn)
|
||||
#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
|
||||
+#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
|
||||
|
||||
#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
|
||||
|
||||
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
|
||||
+#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
|
||||
#define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
|
||||
#define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
|
||||
|
||||
#define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
|
||||
#define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
|
||||
+#define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
|
||||
|
||||
#define TSADCV2_DATA_MASK 0xfff
|
||||
#define TSADCV3_DATA_MASK 0x3ff
|
||||
+#define TSADCV4_DATA_MASK 0x1ff
|
||||
|
||||
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
|
||||
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
|
||||
@@ -198,6 +218,8 @@ struct rockchip_thermal_data {
|
||||
|
||||
#define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
|
||||
#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
|
||||
+#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
|
||||
+#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
|
||||
|
||||
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
|
||||
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
|
||||
@@ -214,6 +236,12 @@ struct rockchip_thermal_data {
|
||||
#define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
|
||||
#define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
|
||||
|
||||
+#define RK3588_GRF0_TSADC_CON 0x0100
|
||||
+
|
||||
+#define RK3588_GRF0_TSADC_TRM (0xff0077 << 0)
|
||||
+#define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10)
|
||||
+#define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12)
|
||||
+
|
||||
#define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
|
||||
#define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
|
||||
#define GRF_TSADC_VCM_EN_L (0x10001 << 7)
|
||||
@@ -508,6 +536,15 @@ static const struct tsadc_table rk3568_c
|
||||
{TSADCV2_DATA_MASK, 125000},
|
||||
};
|
||||
|
||||
+static const struct tsadc_table rk3588_code_table[] = {
|
||||
+ {0, -40000},
|
||||
+ {215, -40000},
|
||||
+ {285, 25000},
|
||||
+ {350, 85000},
|
||||
+ {395, 125000},
|
||||
+ {TSADCV4_DATA_MASK, 125000},
|
||||
+};
|
||||
+
|
||||
static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
|
||||
int temp)
|
||||
{
|
||||
@@ -778,6 +815,25 @@ static void rk_tsadcv7_initialize(struct
|
||||
}
|
||||
}
|
||||
|
||||
+static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
|
||||
+ enum tshut_polarity tshut_polarity)
|
||||
+{
|
||||
+ writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
|
||||
+ writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
|
||||
+ regs + TSADCV3_AUTO_PERIOD_HT);
|
||||
+ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
|
||||
+ regs + TSADCV3_HIGHT_INT_DEBOUNCE);
|
||||
+ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
|
||||
+ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
|
||||
+ if (tshut_polarity == TSHUT_HIGH_ACTIVE)
|
||||
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
|
||||
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
|
||||
+ regs + TSADCV2_AUTO_CON);
|
||||
+ else
|
||||
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
|
||||
+ regs + TSADCV2_AUTO_CON);
|
||||
+}
|
||||
+
|
||||
static void rk_tsadcv2_irq_ack(void __iomem *regs)
|
||||
{
|
||||
u32 val;
|
||||
@@ -794,6 +850,17 @@ static void rk_tsadcv3_irq_ack(void __io
|
||||
writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
|
||||
}
|
||||
|
||||
+static void rk_tsadcv4_irq_ack(void __iomem *regs)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ val = readl_relaxed(regs + TSADCV3_INT_PD);
|
||||
+ writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
|
||||
+ val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
|
||||
+ writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
|
||||
+ regs + TSADCV3_HSHUT_PD);
|
||||
+}
|
||||
+
|
||||
static void rk_tsadcv2_control(void __iomem *regs, bool enable)
|
||||
{
|
||||
u32 val;
|
||||
@@ -829,6 +896,18 @@ static void rk_tsadcv3_control(void __io
|
||||
writel_relaxed(val, regs + TSADCV2_AUTO_CON);
|
||||
}
|
||||
|
||||
+static void rk_tsadcv4_control(void __iomem *regs, bool enable)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ if (enable)
|
||||
+ val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
|
||||
+ else
|
||||
+ val = TSADCV2_AUTO_EN_MASK;
|
||||
+
|
||||
+ writel_relaxed(val, regs + TSADCV2_AUTO_CON);
|
||||
+}
|
||||
+
|
||||
static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
|
||||
int chn, void __iomem *regs, int *temp)
|
||||
{
|
||||
@@ -839,6 +918,16 @@ static int rk_tsadcv2_get_temp(const str
|
||||
return rk_tsadcv2_code_to_temp(table, val, temp);
|
||||
}
|
||||
|
||||
+static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
|
||||
+ int chn, void __iomem *regs, int *temp)
|
||||
+{
|
||||
+ u32 val;
|
||||
+
|
||||
+ val = readl_relaxed(regs + TSADCV3_DATA(chn));
|
||||
+
|
||||
+ return rk_tsadcv2_code_to_temp(table, val, temp);
|
||||
+}
|
||||
+
|
||||
static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
|
||||
int chn, void __iomem *regs, int temp)
|
||||
{
|
||||
@@ -873,6 +962,33 @@ static int rk_tsadcv2_alarm_temp(const s
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
|
||||
+ int chn, void __iomem *regs, int temp)
|
||||
+{
|
||||
+ u32 alarm_value;
|
||||
+
|
||||
+ /*
|
||||
+ * In some cases, some sensors didn't need the trip points, the
|
||||
+ * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
|
||||
+ * in the end, ignore this case and disable the high temperature
|
||||
+ * interrupt.
|
||||
+ */
|
||||
+ if (temp == INT_MAX) {
|
||||
+ writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
|
||||
+ regs + TSADCV3_HT_INT_EN);
|
||||
+ return 0;
|
||||
+ }
|
||||
+ /* Make sure the value is valid */
|
||||
+ alarm_value = rk_tsadcv2_temp_to_code(table, temp);
|
||||
+ if (alarm_value == table->data_mask)
|
||||
+ return -ERANGE;
|
||||
+ writel_relaxed(alarm_value & table->data_mask,
|
||||
+ regs + TSADCV3_COMP_INT(chn));
|
||||
+ writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
|
||||
+ regs + TSADCV3_HT_INT_EN);
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
|
||||
int chn, void __iomem *regs, int temp)
|
||||
{
|
||||
@@ -892,6 +1008,25 @@ static int rk_tsadcv2_tshut_temp(const s
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
|
||||
+ int chn, void __iomem *regs, int temp)
|
||||
+{
|
||||
+ u32 tshut_value;
|
||||
+
|
||||
+ /* Make sure the value is valid */
|
||||
+ tshut_value = rk_tsadcv2_temp_to_code(table, temp);
|
||||
+ if (tshut_value == table->data_mask)
|
||||
+ return -ERANGE;
|
||||
+
|
||||
+ writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
|
||||
+
|
||||
+ /* TSHUT will be valid */
|
||||
+ writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
|
||||
+ regs + TSADCV3_AUTO_SRC_CON);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
|
||||
enum tshut_mode mode)
|
||||
{
|
||||
@@ -909,6 +1044,22 @@ static void rk_tsadcv2_tshut_mode(int ch
|
||||
writel_relaxed(val, regs + TSADCV2_INT_EN);
|
||||
}
|
||||
|
||||
+static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs,
|
||||
+ enum tshut_mode mode)
|
||||
+{
|
||||
+ u32 val_gpio, val_cru;
|
||||
+
|
||||
+ if (mode == TSHUT_MODE_GPIO) {
|
||||
+ val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
|
||||
+ val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
|
||||
+ } else {
|
||||
+ val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
|
||||
+ val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
|
||||
+ }
|
||||
+ writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
|
||||
+ writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
|
||||
+}
|
||||
+
|
||||
static const struct rockchip_tsadc_chip px30_tsadc_data = {
|
||||
/* cpu, gpu */
|
||||
.chn_offset = 0,
|
||||
@@ -1132,6 +1283,28 @@ static const struct rockchip_tsadc_chip
|
||||
},
|
||||
};
|
||||
|
||||
+static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
|
||||
+ /* top, big_core0, big_core1, little_core, center, gpu, npu */
|
||||
+ .chn_offset = 0,
|
||||
+ .chn_num = 7, /* seven channels for tsadc */
|
||||
+ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
|
||||
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
|
||||
+ .tshut_temp = 95000,
|
||||
+ .initialize = rk_tsadcv8_initialize,
|
||||
+ .irq_ack = rk_tsadcv4_irq_ack,
|
||||
+ .control = rk_tsadcv4_control,
|
||||
+ .get_temp = rk_tsadcv4_get_temp,
|
||||
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
|
||||
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
|
||||
+ .set_tshut_mode = rk_tsadcv3_tshut_mode,
|
||||
+ .table = {
|
||||
+ .id = rk3588_code_table,
|
||||
+ .length = ARRAY_SIZE(rk3588_code_table),
|
||||
+ .data_mask = TSADCV4_DATA_MASK,
|
||||
+ .mode = ADC_INCREMENT,
|
||||
+ },
|
||||
+};
|
||||
+
|
||||
static const struct of_device_id of_rockchip_thermal_match[] = {
|
||||
{ .compatible = "rockchip,px30-tsadc",
|
||||
.data = (void *)&px30_tsadc_data,
|
||||
@@ -1168,6 +1341,10 @@ static const struct of_device_id of_rock
|
||||
.compatible = "rockchip,rk3568-tsadc",
|
||||
.data = (void *)&rk3568_tsadc_data,
|
||||
},
|
||||
+ {
|
||||
+ .compatible = "rockchip,rk3588-tsadc",
|
||||
+ .data = (void *)&rk3588_tsadc_data,
|
||||
+ },
|
||||
{ /* end */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
|
||||
@ -1,28 +0,0 @@
|
||||
From fee5caec88b3d1948453c55474cf16b81026a1b2 Mon Sep 17 00:00:00 2001
|
||||
From: Ye Xingchen <ye.xingchen@zte.com.cn>
|
||||
Date: Fri, 24 Mar 2023 11:08:55 +0800
|
||||
Subject: [PATCH] thermal/drivers/rockchip: use
|
||||
devm_reset_control_array_get_exclusive()
|
||||
|
||||
Switch devm_reset_control_array_get() to
|
||||
devm_reset_control_array_get_exclusive().
|
||||
|
||||
Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn>
|
||||
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
|
||||
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
||||
Link: https://lore.kernel.org/r/202303241108553006227@zte.com.cn
|
||||
---
|
||||
drivers/thermal/rockchip_thermal.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
--- a/drivers/thermal/rockchip_thermal.c
|
||||
+++ b/drivers/thermal/rockchip_thermal.c
|
||||
@@ -1548,7 +1548,7 @@ static int rockchip_thermal_probe(struct
|
||||
if (IS_ERR(thermal->regs))
|
||||
return PTR_ERR(thermal->regs);
|
||||
|
||||
- thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
|
||||
+ thermal->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
|
||||
if (IS_ERR(thermal->reset))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset),
|
||||
"failed to get tsadc reset.\n");
|
||||
@ -1,232 +0,0 @@
|
||||
From a03c4427725301328ccbe414d0a19ad39e90d008 Mon Sep 17 00:00:00 2001
|
||||
From: Lucas Tanure <lucas.tanure@collabora.com>
|
||||
Date: Tue, 14 Mar 2023 13:55:55 +0000
|
||||
Subject: [PATCH] phy: rockchip: Add naneng combo phy support for RK3588
|
||||
|
||||
Add support for RK3588 combo phy
|
||||
|
||||
This is based on prior work from XiaoDong Huang and
|
||||
Peter Geis fixing this issue specifically for Rockchip 356x.
|
||||
|
||||
Co-developed-by: Andrew Powers-Holmes <aholmes@omnom.net>
|
||||
Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
|
||||
Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230314135555.44162-4-lucas.tanure@collabora.com
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
.../rockchip/phy-rockchip-naneng-combphy.c | 184 ++++++++++++++++++
|
||||
1 file changed, 184 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
|
||||
@@ -63,6 +63,9 @@
|
||||
#define PHYREG18 0x44
|
||||
#define PHYREG18_PLL_LOOP 0x32
|
||||
|
||||
+#define PHYREG27 0x6C
|
||||
+#define PHYREG27_RX_TRIM_RK3588 0x4C
|
||||
+
|
||||
#define PHYREG32 0x7C
|
||||
#define PHYREG32_SSC_MASK GENMASK(7, 4)
|
||||
#define PHYREG32_SSC_DIR_SHIFT 4
|
||||
@@ -114,7 +117,10 @@ struct rockchip_combphy_grfcfg {
|
||||
struct combphy_reg con2_for_sata;
|
||||
struct combphy_reg con3_for_sata;
|
||||
struct combphy_reg pipe_con0_for_sata;
|
||||
+ struct combphy_reg pipe_con1_for_sata;
|
||||
struct combphy_reg pipe_xpcs_phy_ready;
|
||||
+ struct combphy_reg pipe_pcie1l0_sel;
|
||||
+ struct combphy_reg pipe_pcie1l1_sel;
|
||||
};
|
||||
|
||||
struct rockchip_combphy_cfg {
|
||||
@@ -559,11 +565,189 @@ static const struct rockchip_combphy_cfg
|
||||
.combphy_cfg = rk3568_combphy_cfg,
|
||||
};
|
||||
|
||||
+static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
|
||||
+{
|
||||
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
|
||||
+ unsigned long rate;
|
||||
+ u32 val;
|
||||
+
|
||||
+ switch (priv->type) {
|
||||
+ case PHY_TYPE_PCIE:
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
|
||||
+ break;
|
||||
+ case PHY_TYPE_USB3:
|
||||
+ /* Set SSC downward spread spectrum */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
|
||||
+ PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
|
||||
+ PHYREG32);
|
||||
+
|
||||
+ /* Enable adaptive CTLE for USB3.0 Rx. */
|
||||
+ val = readl(priv->mmio + PHYREG15);
|
||||
+ val |= PHYREG15_CTLE_EN;
|
||||
+ writel(val, priv->mmio + PHYREG15);
|
||||
+
|
||||
+ /* Set PLL KVCO fine tuning signals. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
+ PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
|
||||
+ PHYREG33);
|
||||
+
|
||||
+ /* Enable controlling random jitter. */
|
||||
+ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
+
|
||||
+ /* Set PLL input clock divider 1/2. */
|
||||
+ rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
|
||||
+ PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
|
||||
+ PHYREG6);
|
||||
+
|
||||
+ writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
|
||||
+ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
|
||||
+ break;
|
||||
+ case PHY_TYPE_SATA:
|
||||
+ /* Enable adaptive CTLE for SATA Rx. */
|
||||
+ val = readl(priv->mmio + PHYREG15);
|
||||
+ val |= PHYREG15_CTLE_EN;
|
||||
+ writel(val, priv->mmio + PHYREG15);
|
||||
+ /*
|
||||
+ * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
|
||||
+ * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
|
||||
+ */
|
||||
+ val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
|
||||
+ val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
|
||||
+ writel(val, priv->mmio + PHYREG7);
|
||||
+
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
|
||||
+ rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
|
||||
+ break;
|
||||
+ case PHY_TYPE_SGMII:
|
||||
+ case PHY_TYPE_QSGMII:
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "incompatible PHY type\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ rate = clk_get_rate(priv->refclk);
|
||||
+
|
||||
+ switch (rate) {
|
||||
+ case REF_CLOCK_24MHz:
|
||||
+ if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
|
||||
+ /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
|
||||
+ val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
|
||||
+ val, PHYREG15);
|
||||
+
|
||||
+ writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
|
||||
+ }
|
||||
+ break;
|
||||
+
|
||||
+ case REF_CLOCK_25MHz:
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
|
||||
+ break;
|
||||
+ case REF_CLOCK_100MHz:
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
|
||||
+ if (priv->type == PHY_TYPE_PCIE) {
|
||||
+ /* PLL KVCO fine tuning. */
|
||||
+ val = 4 << PHYREG33_PLL_KVCO_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
|
||||
+ val, PHYREG33);
|
||||
+
|
||||
+ /* Enable controlling random jitter. */
|
||||
+ writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
|
||||
+
|
||||
+ /* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
|
||||
+ writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27);
|
||||
+
|
||||
+ /* Set up su_trim: */
|
||||
+ writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
|
||||
+ } else if (priv->type == PHY_TYPE_SATA) {
|
||||
+ /* downward spread spectrum +500ppm */
|
||||
+ val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
|
||||
+ val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
|
||||
+ }
|
||||
+ break;
|
||||
+ default:
|
||||
+ dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ if (priv->ext_refclk) {
|
||||
+ rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
|
||||
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
|
||||
+ val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
|
||||
+ val |= PHYREG13_CKRCV_AMP0;
|
||||
+ rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
|
||||
+
|
||||
+ val = readl(priv->mmio + PHYREG14);
|
||||
+ val |= PHYREG14_CKRCV_AMP1;
|
||||
+ writel(val, priv->mmio + PHYREG14);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (priv->enable_ssc) {
|
||||
+ val = readl(priv->mmio + PHYREG8);
|
||||
+ val |= PHYREG8_SSC_EN;
|
||||
+ writel(val, priv->mmio + PHYREG8);
|
||||
+ }
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
|
||||
+ /* pipe-phy-grf */
|
||||
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
|
||||
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
|
||||
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
|
||||
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
|
||||
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
|
||||
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
|
||||
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
|
||||
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
|
||||
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
|
||||
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
|
||||
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
|
||||
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
|
||||
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
|
||||
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
|
||||
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
|
||||
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
|
||||
+ .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
|
||||
+ .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
|
||||
+ .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
|
||||
+ .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
|
||||
+ /* pipe-grf */
|
||||
+ .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
|
||||
+ .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
|
||||
+ .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
|
||||
+ .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
|
||||
+ .grfcfg = &rk3588_combphy_grfcfgs,
|
||||
+ .combphy_cfg = rk3588_combphy_cfg,
|
||||
+};
|
||||
+
|
||||
static const struct of_device_id rockchip_combphy_of_match[] = {
|
||||
{
|
||||
.compatible = "rockchip,rk3568-naneng-combphy",
|
||||
.data = &rk3568_combphy_cfgs,
|
||||
},
|
||||
+ {
|
||||
+ .compatible = "rockchip,rk3588-naneng-combphy",
|
||||
+ .data = &rk3588_combphy_cfgs,
|
||||
+ },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
|
||||
@ -1,351 +0,0 @@
|
||||
From 52b99b871eb79637342660b46c900642483d4412 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 22 May 2023 19:03:19 +0200
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3588 support
|
||||
|
||||
Add basic support for the USB2 PHY found in the Rockchip RK3588.
|
||||
|
||||
Co-developed-by: William Wu <william.wu@rock-chips.com>
|
||||
Signed-off-by: William Wu <william.wu@rock-chips.com>
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Message-ID: <20230522170324.61349-3-sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 226 ++++++++++++++++--
|
||||
1 file changed, 211 insertions(+), 15 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -116,6 +116,12 @@ struct rockchip_chg_det_reg {
|
||||
* @bvalid_det_en: vbus valid rise detection enable register.
|
||||
* @bvalid_det_st: vbus valid rise detection status register.
|
||||
* @bvalid_det_clr: vbus valid rise detection clear register.
|
||||
+ * @disfall_en: host disconnect fall edge detection enable.
|
||||
+ * @disfall_st: host disconnect fall edge detection state.
|
||||
+ * @disfall_clr: host disconnect fall edge detection clear.
|
||||
+ * @disrise_en: host disconnect rise edge detection enable.
|
||||
+ * @disrise_st: host disconnect rise edge detection state.
|
||||
+ * @disrise_clr: host disconnect rise edge detection clear.
|
||||
* @id_det_en: id detection enable register.
|
||||
* @id_det_st: id detection state register.
|
||||
* @id_det_clr: id detection clear register.
|
||||
@@ -133,6 +139,12 @@ struct rockchip_usb2phy_port_cfg {
|
||||
struct usb2phy_reg bvalid_det_en;
|
||||
struct usb2phy_reg bvalid_det_st;
|
||||
struct usb2phy_reg bvalid_det_clr;
|
||||
+ struct usb2phy_reg disfall_en;
|
||||
+ struct usb2phy_reg disfall_st;
|
||||
+ struct usb2phy_reg disfall_clr;
|
||||
+ struct usb2phy_reg disrise_en;
|
||||
+ struct usb2phy_reg disrise_st;
|
||||
+ struct usb2phy_reg disrise_clr;
|
||||
struct usb2phy_reg id_det_en;
|
||||
struct usb2phy_reg id_det_st;
|
||||
struct usb2phy_reg id_det_clr;
|
||||
@@ -168,6 +180,7 @@ struct rockchip_usb2phy_cfg {
|
||||
* @port_id: flag for otg port or host port.
|
||||
* @suspended: phy suspended flag.
|
||||
* @vbus_attached: otg device vbus status.
|
||||
+ * @host_disconnect: usb host disconnect status.
|
||||
* @bvalid_irq: IRQ number assigned for vbus valid rise detection.
|
||||
* @id_irq: IRQ number assigned for ID pin detection.
|
||||
* @ls_irq: IRQ number assigned for linestate detection.
|
||||
@@ -187,6 +200,7 @@ struct rockchip_usb2phy_port {
|
||||
unsigned int port_id;
|
||||
bool suspended;
|
||||
bool vbus_attached;
|
||||
+ bool host_disconnect;
|
||||
int bvalid_irq;
|
||||
int id_irq;
|
||||
int ls_irq;
|
||||
@@ -405,6 +419,27 @@ static int rockchip_usb2phy_extcon_regis
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static int rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy *rphy,
|
||||
+ struct rockchip_usb2phy_port *rport,
|
||||
+ bool en)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = property_enable(rphy->grf, &rport->port_cfg->disfall_en, en);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ ret = property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ return property_enable(rphy->grf, &rport->port_cfg->disrise_en, en);
|
||||
+}
|
||||
+
|
||||
static int rockchip_usb2phy_init(struct phy *phy)
|
||||
{
|
||||
struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
|
||||
@@ -449,6 +484,15 @@ static int rockchip_usb2phy_init(struct
|
||||
dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
|
||||
}
|
||||
} else if (rport->port_id == USB2PHY_PORT_HOST) {
|
||||
+ if (rport->port_cfg->disfall_en.offset) {
|
||||
+ rport->host_disconnect = true;
|
||||
+ ret = rockchip_usb2phy_enable_host_disc_irq(rphy, rport, true);
|
||||
+ if (ret) {
|
||||
+ dev_err(rphy->dev, "failed to enable disconnect irq\n");
|
||||
+ goto out;
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
/* clear linestate and enable linestate detect irq */
|
||||
ret = property_enable(rphy->grf,
|
||||
&rport->port_cfg->ls_det_clr, true);
|
||||
@@ -810,9 +854,7 @@ static void rockchip_usb2phy_sm_work(str
|
||||
struct rockchip_usb2phy_port *rport =
|
||||
container_of(work, struct rockchip_usb2phy_port, sm_work.work);
|
||||
struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
|
||||
- unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
|
||||
- rport->port_cfg->utmi_hstdet.bitstart + 1;
|
||||
- unsigned int ul, uhd, state;
|
||||
+ unsigned int sh, ul, uhd, state;
|
||||
unsigned int ul_mask, uhd_mask;
|
||||
int ret;
|
||||
|
||||
@@ -822,18 +864,26 @@ static void rockchip_usb2phy_sm_work(str
|
||||
if (ret < 0)
|
||||
goto next_schedule;
|
||||
|
||||
- ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
|
||||
- if (ret < 0)
|
||||
- goto next_schedule;
|
||||
-
|
||||
- uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
|
||||
- rport->port_cfg->utmi_hstdet.bitstart);
|
||||
ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
|
||||
rport->port_cfg->utmi_ls.bitstart);
|
||||
|
||||
- /* stitch on utmi_ls and utmi_hstdet as phy state */
|
||||
- state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
|
||||
- (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
|
||||
+ if (rport->port_cfg->utmi_hstdet.offset) {
|
||||
+ ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
|
||||
+ if (ret < 0)
|
||||
+ goto next_schedule;
|
||||
+
|
||||
+ uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
|
||||
+ rport->port_cfg->utmi_hstdet.bitstart);
|
||||
+
|
||||
+ sh = rport->port_cfg->utmi_hstdet.bitend -
|
||||
+ rport->port_cfg->utmi_hstdet.bitstart + 1;
|
||||
+ /* stitch on utmi_ls and utmi_hstdet as phy state */
|
||||
+ state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
|
||||
+ (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
|
||||
+ } else {
|
||||
+ state = ((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << 1 |
|
||||
+ rport->host_disconnect;
|
||||
+ }
|
||||
|
||||
switch (state) {
|
||||
case PHY_STATE_HS_ONLINE:
|
||||
@@ -966,6 +1016,31 @@ static irqreturn_t rockchip_usb2phy_otg_
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static irqreturn_t rockchip_usb2phy_host_disc_irq(int irq, void *data)
|
||||
+{
|
||||
+ struct rockchip_usb2phy_port *rport = data;
|
||||
+ struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
|
||||
+
|
||||
+ if (!property_enabled(rphy->grf, &rport->port_cfg->disfall_st) &&
|
||||
+ !property_enabled(rphy->grf, &rport->port_cfg->disrise_st))
|
||||
+ return IRQ_NONE;
|
||||
+
|
||||
+ mutex_lock(&rport->mutex);
|
||||
+
|
||||
+ /* clear disconnect fall or rise detect irq pending status */
|
||||
+ if (property_enabled(rphy->grf, &rport->port_cfg->disfall_st)) {
|
||||
+ property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
|
||||
+ rport->host_disconnect = false;
|
||||
+ } else if (property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) {
|
||||
+ property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
|
||||
+ rport->host_disconnect = true;
|
||||
+ }
|
||||
+
|
||||
+ mutex_unlock(&rport->mutex);
|
||||
+
|
||||
+ return IRQ_HANDLED;
|
||||
+}
|
||||
+
|
||||
static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
|
||||
{
|
||||
struct rockchip_usb2phy *rphy = data;
|
||||
@@ -978,6 +1053,10 @@ static irqreturn_t rockchip_usb2phy_irq(
|
||||
if (!rport->phy)
|
||||
continue;
|
||||
|
||||
+ if (rport->port_id == USB2PHY_PORT_HOST &&
|
||||
+ rport->port_cfg->disfall_en.offset)
|
||||
+ ret |= rockchip_usb2phy_host_disc_irq(irq, rport);
|
||||
+
|
||||
switch (rport->port_id) {
|
||||
case USB2PHY_PORT_OTG:
|
||||
if (rport->mode != USB_DR_MODE_HOST &&
|
||||
@@ -1233,7 +1312,7 @@ static int rockchip_usb2phy_probe(struct
|
||||
}
|
||||
|
||||
/* support address_cells=2 */
|
||||
- if (reg == 0) {
|
||||
+ if (of_property_count_u32_elems(np, "reg") > 2 && reg == 0) {
|
||||
if (of_property_read_u32_index(np, "reg", 1, ®)) {
|
||||
dev_err(dev, "the reg property is not assigned in %pOFn node\n",
|
||||
np);
|
||||
@@ -1254,14 +1333,14 @@ static int rockchip_usb2phy_probe(struct
|
||||
|
||||
/* find out a proper config which can be matched with dt. */
|
||||
index = 0;
|
||||
- while (phy_cfgs[index].reg) {
|
||||
+ do {
|
||||
if (phy_cfgs[index].reg == reg) {
|
||||
rphy->phy_cfg = &phy_cfgs[index];
|
||||
break;
|
||||
}
|
||||
|
||||
++index;
|
||||
- }
|
||||
+ } while (phy_cfgs[index].reg);
|
||||
|
||||
if (!rphy->phy_cfg) {
|
||||
dev_err(dev, "no phy-config can be matched with %pOFn node\n",
|
||||
@@ -1664,6 +1743,122 @@ static const struct rockchip_usb2phy_cfg
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
+static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
|
||||
+ {
|
||||
+ .reg = 0x0000,
|
||||
+ .num_ports = 1,
|
||||
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x000c, 11, 11, 0, 1 },
|
||||
+ .bvalid_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .bvalid_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
+ .disfall_en = { 0x0080, 6, 6, 0, 1 },
|
||||
+ .disfall_st = { 0x0084, 6, 6, 0, 1 },
|
||||
+ .disfall_clr = { 0x0088, 6, 6, 0, 1 },
|
||||
+ .disrise_en = { 0x0080, 5, 5, 0, 1 },
|
||||
+ .disrise_st = { 0x0084, 5, 5, 0, 1 },
|
||||
+ .disrise_clr = { 0x0088, 5, 5, 0, 1 },
|
||||
+ .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
|
||||
+ .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
|
||||
+ }
|
||||
+ },
|
||||
+ .chg_det = {
|
||||
+ .cp_det = { 0x00c0, 0, 0, 0, 1 },
|
||||
+ .dcp_det = { 0x00c0, 0, 0, 0, 1 },
|
||||
+ .dp_det = { 0x00c0, 1, 1, 1, 0 },
|
||||
+ .idm_sink_en = { 0x0008, 5, 5, 1, 0 },
|
||||
+ .idp_sink_en = { 0x0008, 5, 5, 0, 1 },
|
||||
+ .idp_src_en = { 0x0008, 14, 14, 0, 1 },
|
||||
+ .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 },
|
||||
+ .vdm_src_en = { 0x0008, 7, 6, 0, 3 },
|
||||
+ .vdp_src_en = { 0x0008, 7, 6, 0, 3 },
|
||||
+ },
|
||||
+ },
|
||||
+ {
|
||||
+ .reg = 0x4000,
|
||||
+ .num_ports = 1,
|
||||
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_OTG] = {
|
||||
+ .phy_sus = { 0x000c, 11, 11, 0, 1 },
|
||||
+ .bvalid_det_en = { 0x0080, 1, 1, 0, 1 },
|
||||
+ .bvalid_det_st = { 0x0084, 1, 1, 0, 1 },
|
||||
+ .bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
|
||||
+ .ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
+ .disfall_en = { 0x0080, 6, 6, 0, 1 },
|
||||
+ .disfall_st = { 0x0084, 6, 6, 0, 1 },
|
||||
+ .disfall_clr = { 0x0088, 6, 6, 0, 1 },
|
||||
+ .disrise_en = { 0x0080, 5, 5, 0, 1 },
|
||||
+ .disrise_st = { 0x0084, 5, 5, 0, 1 },
|
||||
+ .disrise_clr = { 0x0088, 5, 5, 0, 1 },
|
||||
+ .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
|
||||
+ .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
|
||||
+ }
|
||||
+ },
|
||||
+ .chg_det = {
|
||||
+ .cp_det = { 0x00c0, 0, 0, 0, 1 },
|
||||
+ .dcp_det = { 0x00c0, 0, 0, 0, 1 },
|
||||
+ .dp_det = { 0x00c0, 1, 1, 1, 0 },
|
||||
+ .idm_sink_en = { 0x0008, 5, 5, 1, 0 },
|
||||
+ .idp_sink_en = { 0x0008, 5, 5, 0, 1 },
|
||||
+ .idp_src_en = { 0x0008, 14, 14, 0, 1 },
|
||||
+ .rdm_pdwn_en = { 0x0008, 14, 14, 0, 1 },
|
||||
+ .vdm_src_en = { 0x0008, 7, 6, 0, 3 },
|
||||
+ .vdp_src_en = { 0x0008, 7, 6, 0, 3 },
|
||||
+ },
|
||||
+ },
|
||||
+ {
|
||||
+ .reg = 0x8000,
|
||||
+ .num_ports = 1,
|
||||
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ .phy_sus = { 0x0008, 2, 2, 0, 1 },
|
||||
+ .ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
+ .disfall_en = { 0x0080, 6, 6, 0, 1 },
|
||||
+ .disfall_st = { 0x0084, 6, 6, 0, 1 },
|
||||
+ .disfall_clr = { 0x0088, 6, 6, 0, 1 },
|
||||
+ .disrise_en = { 0x0080, 5, 5, 0, 1 },
|
||||
+ .disrise_st = { 0x0084, 5, 5, 0, 1 },
|
||||
+ .disrise_clr = { 0x0088, 5, 5, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
|
||||
+ }
|
||||
+ },
|
||||
+ },
|
||||
+ {
|
||||
+ .reg = 0xc000,
|
||||
+ .num_ports = 1,
|
||||
+ .clkout_ctl = { 0x0000, 0, 0, 1, 0 },
|
||||
+ .port_cfgs = {
|
||||
+ [USB2PHY_PORT_HOST] = {
|
||||
+ .phy_sus = { 0x0008, 2, 2, 0, 1 },
|
||||
+ .ls_det_en = { 0x0080, 0, 0, 0, 1 },
|
||||
+ .ls_det_st = { 0x0084, 0, 0, 0, 1 },
|
||||
+ .ls_det_clr = { 0x0088, 0, 0, 0, 1 },
|
||||
+ .disfall_en = { 0x0080, 6, 6, 0, 1 },
|
||||
+ .disfall_st = { 0x0084, 6, 6, 0, 1 },
|
||||
+ .disfall_clr = { 0x0088, 6, 6, 0, 1 },
|
||||
+ .disrise_en = { 0x0080, 5, 5, 0, 1 },
|
||||
+ .disrise_st = { 0x0084, 5, 5, 0, 1 },
|
||||
+ .disrise_clr = { 0x0088, 5, 5, 0, 1 },
|
||||
+ .utmi_ls = { 0x00c0, 10, 9, 0, 1 },
|
||||
+ }
|
||||
+ },
|
||||
+ },
|
||||
+ { /* sentinel */ }
|
||||
+};
|
||||
+
|
||||
static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0x100,
|
||||
@@ -1714,6 +1909,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
|
||||
+ { .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
|
||||
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
|
||||
{}
|
||||
};
|
||||
@ -1,97 +0,0 @@
|
||||
From 44d88aa9ae81c79ccc47ba4ef85aeda968bc4a50 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 22 May 2023 19:03:20 +0200
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add reset support
|
||||
|
||||
Add reset handling support, which is needed for proper
|
||||
operation with RK3588.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Message-ID: <20230522170324.61349-4-sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 38 +++++++++++++++++++
|
||||
1 file changed, 38 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -24,6 +24,7 @@
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/power_supply.h>
|
||||
#include <linux/regmap.h>
|
||||
+#include <linux/reset.h>
|
||||
#include <linux/mfd/syscon.h>
|
||||
#include <linux/usb/of.h>
|
||||
#include <linux/usb/otg.h>
|
||||
@@ -223,6 +224,7 @@ struct rockchip_usb2phy_port {
|
||||
* @clk: clock struct of phy input clk.
|
||||
* @clk480m: clock struct of phy output clk.
|
||||
* @clk480m_hw: clock struct of phy output clk management.
|
||||
+ * @phy_reset: phy reset control.
|
||||
* @chg_state: states involved in USB charger detection.
|
||||
* @chg_type: USB charger types.
|
||||
* @dcd_retries: The retry count used to track Data contact
|
||||
@@ -239,6 +241,7 @@ struct rockchip_usb2phy {
|
||||
struct clk *clk;
|
||||
struct clk *clk480m;
|
||||
struct clk_hw clk480m_hw;
|
||||
+ struct reset_control *phy_reset;
|
||||
enum usb_chg_state chg_state;
|
||||
enum power_supply_type chg_type;
|
||||
u8 dcd_retries;
|
||||
@@ -280,6 +283,25 @@ static inline bool property_enabled(stru
|
||||
return tmp != reg->disable;
|
||||
}
|
||||
|
||||
+static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ ret = reset_control_assert(rphy->phy_reset);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ udelay(10);
|
||||
+
|
||||
+ ret = reset_control_deassert(rphy->phy_reset);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ usleep_range(100, 200);
|
||||
+
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
|
||||
{
|
||||
struct rockchip_usb2phy *rphy =
|
||||
@@ -534,6 +556,18 @@ static int rockchip_usb2phy_power_on(str
|
||||
return ret;
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * For rk3588, it needs to reset phy when exit from
|
||||
+ * suspend mode with common_on_n 1'b1(aka REFCLK_LOGIC,
|
||||
+ * Bias, and PLL blocks are powered down) for lower
|
||||
+ * power consumption. If you don't want to reset phy,
|
||||
+ * please keep the common_on_n 1'b0 to set these blocks
|
||||
+ * remain powered.
|
||||
+ */
|
||||
+ ret = rockchip_usb2phy_reset(rphy);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
/* waiting for the utmi_clk to become stable */
|
||||
usleep_range(1500, 2000);
|
||||
|
||||
@@ -1348,6 +1382,10 @@ static int rockchip_usb2phy_probe(struct
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
+ rphy->phy_reset = devm_reset_control_get_optional(dev, "phy");
|
||||
+ if (IS_ERR(rphy->phy_reset))
|
||||
+ return PTR_ERR(rphy->phy_reset);
|
||||
+
|
||||
rphy->clk = of_clk_get_by_name(np, "phyclk");
|
||||
if (!IS_ERR(rphy->clk)) {
|
||||
clk_prepare_enable(rphy->clk);
|
||||
@ -1,148 +0,0 @@
|
||||
From 7d508a92e4588a59b909e235667d515051dd5955 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 22 May 2023 19:03:21 +0200
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning support
|
||||
|
||||
On RK3588 some registers need to be tweaked to support waking up from
|
||||
suspend when a USB device is plugged into a port from a suspended PHY.
|
||||
Without this change USB devices only work when they are plugged at
|
||||
boot time.
|
||||
|
||||
Apart from that it optimizes settings to avoid devices toggling
|
||||
between fullspeed and highspeed mode.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Message-ID: <20230522170324.61349-5-sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 63 +++++++++++++++++++
|
||||
1 file changed, 63 insertions(+)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -33,6 +33,8 @@
|
||||
#define SCHEDULE_DELAY (60 * HZ)
|
||||
#define OTG_SCHEDULE_DELAY (2 * HZ)
|
||||
|
||||
+struct rockchip_usb2phy;
|
||||
+
|
||||
enum rockchip_usb2phy_port_id {
|
||||
USB2PHY_PORT_OTG,
|
||||
USB2PHY_PORT_HOST,
|
||||
@@ -163,6 +165,7 @@ struct rockchip_usb2phy_port_cfg {
|
||||
* struct rockchip_usb2phy_cfg - usb-phy configuration.
|
||||
* @reg: the address offset of grf for usb-phy config.
|
||||
* @num_ports: specify how many ports that the phy has.
|
||||
+ * @phy_tuning: phy default parameters tuning.
|
||||
* @clkout_ctl: keep on/turn off output clk of phy.
|
||||
* @port_cfgs: usb-phy port configurations.
|
||||
* @chg_det: charger detection registers.
|
||||
@@ -170,6 +173,7 @@ struct rockchip_usb2phy_port_cfg {
|
||||
struct rockchip_usb2phy_cfg {
|
||||
unsigned int reg;
|
||||
unsigned int num_ports;
|
||||
+ int (*phy_tuning)(struct rockchip_usb2phy *rphy);
|
||||
struct usb2phy_reg clkout_ctl;
|
||||
const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
|
||||
const struct rockchip_chg_det_reg chg_det;
|
||||
@@ -1400,6 +1404,12 @@ static int rockchip_usb2phy_probe(struct
|
||||
goto disable_clks;
|
||||
}
|
||||
|
||||
+ if (rphy->phy_cfg->phy_tuning) {
|
||||
+ ret = rphy->phy_cfg->phy_tuning(rphy);
|
||||
+ if (ret)
|
||||
+ goto disable_clks;
|
||||
+ }
|
||||
+
|
||||
index = 0;
|
||||
for_each_available_child_of_node(np, child_np) {
|
||||
struct rockchip_usb2phy_port *rport = &rphy->ports[index];
|
||||
@@ -1468,6 +1478,55 @@ disable_clks:
|
||||
return ret;
|
||||
}
|
||||
|
||||
+static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
|
||||
+{
|
||||
+ int ret;
|
||||
+ bool usb3otg = false;
|
||||
+ /*
|
||||
+ * utmi_termselect = 1'b1 (en FS terminations)
|
||||
+ * utmi_xcvrselect = 2'b01 (FS transceiver)
|
||||
+ */
|
||||
+ int suspend_cfg = 0x14;
|
||||
+
|
||||
+ if (rphy->phy_cfg->reg == 0x0000 || rphy->phy_cfg->reg == 0x4000) {
|
||||
+ /* USB2 config for USB3_0 and USB3_1 */
|
||||
+ suspend_cfg |= 0x01; /* utmi_opmode = 2'b01 (no-driving) */
|
||||
+ usb3otg = true;
|
||||
+ } else if (rphy->phy_cfg->reg == 0x8000 || rphy->phy_cfg->reg == 0xc000) {
|
||||
+ /* USB2 config for USB2_0 and USB2_1 */
|
||||
+ suspend_cfg |= 0x00; /* utmi_opmode = 2'b00 (normal) */
|
||||
+ } else {
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
+ /* Deassert SIDDQ to power on analog block */
|
||||
+ ret = regmap_write(rphy->grf, 0x0008, GENMASK(29, 29) | 0x0000);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* Do reset after exit IDDQ mode */
|
||||
+ ret = rockchip_usb2phy_reset(rphy);
|
||||
+ if (ret)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* suspend configuration */
|
||||
+ ret |= regmap_write(rphy->grf, 0x000c, GENMASK(20, 16) | suspend_cfg);
|
||||
+
|
||||
+ /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
|
||||
+ ret |= regmap_write(rphy->grf, 0x0004, GENMASK(27, 24) | 0x0900);
|
||||
+
|
||||
+ /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
|
||||
+ ret |= regmap_write(rphy->grf, 0x0008, GENMASK(20, 19) | 0x0010);
|
||||
+
|
||||
+ if (!usb3otg)
|
||||
+ return ret;
|
||||
+
|
||||
+ /* Pullup iddig pin for USB3_0 OTG mode */
|
||||
+ ret |= regmap_write(rphy->grf, 0x0010, GENMASK(17, 16) | 0x0003);
|
||||
+
|
||||
+ return ret;
|
||||
+}
|
||||
+
|
||||
static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0x760,
|
||||
@@ -1785,6 +1844,7 @@ static const struct rockchip_usb2phy_cfg
|
||||
{
|
||||
.reg = 0x0000,
|
||||
.num_ports = 1,
|
||||
+ .phy_tuning = rk3588_usb2phy_tuning,
|
||||
.clkout_ctl = { 0x0000, 0, 0, 1, 0 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
@@ -1821,6 +1881,7 @@ static const struct rockchip_usb2phy_cfg
|
||||
{
|
||||
.reg = 0x4000,
|
||||
.num_ports = 1,
|
||||
+ .phy_tuning = rk3588_usb2phy_tuning,
|
||||
.clkout_ctl = { 0x0000, 0, 0, 1, 0 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_OTG] = {
|
||||
@@ -1857,6 +1918,7 @@ static const struct rockchip_usb2phy_cfg
|
||||
{
|
||||
.reg = 0x8000,
|
||||
.num_ports = 1,
|
||||
+ .phy_tuning = rk3588_usb2phy_tuning,
|
||||
.clkout_ctl = { 0x0000, 0, 0, 1, 0 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
@@ -1877,6 +1939,7 @@ static const struct rockchip_usb2phy_cfg
|
||||
{
|
||||
.reg = 0xc000,
|
||||
.num_ports = 1,
|
||||
+ .phy_tuning = rk3588_usb2phy_tuning,
|
||||
.clkout_ctl = { 0x0000, 0, 0, 1, 0 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
@ -1,61 +0,0 @@
|
||||
From f4ca578b9803601074ab0d9e366b5fcda504e5a6 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 22 May 2023 19:03:22 +0200
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: simplify phy clock handling
|
||||
|
||||
Simplify phyclk handling by using devm_clk_get_optional_enabled to
|
||||
acquire and enable the optional clock. This also fixes a resource
|
||||
leak in driver remove path and adds proper error handling.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Message-ID: <20230522170324.61349-6-sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 19 ++++++-------------
|
||||
1 file changed, 6 insertions(+), 13 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1390,24 +1390,22 @@ static int rockchip_usb2phy_probe(struct
|
||||
if (IS_ERR(rphy->phy_reset))
|
||||
return PTR_ERR(rphy->phy_reset);
|
||||
|
||||
- rphy->clk = of_clk_get_by_name(np, "phyclk");
|
||||
- if (!IS_ERR(rphy->clk)) {
|
||||
- clk_prepare_enable(rphy->clk);
|
||||
- } else {
|
||||
- dev_info(&pdev->dev, "no phyclk specified\n");
|
||||
- rphy->clk = NULL;
|
||||
+ rphy->clk = devm_clk_get_optional_enabled(dev, "phyclk");
|
||||
+ if (IS_ERR(rphy->clk)) {
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(rphy->clk),
|
||||
+ "failed to get phyclk\n");
|
||||
}
|
||||
|
||||
ret = rockchip_usb2phy_clk480m_register(rphy);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register 480m output clock\n");
|
||||
- goto disable_clks;
|
||||
+ return ret;
|
||||
}
|
||||
|
||||
if (rphy->phy_cfg->phy_tuning) {
|
||||
ret = rphy->phy_cfg->phy_tuning(rphy);
|
||||
if (ret)
|
||||
- goto disable_clks;
|
||||
+ return ret;
|
||||
}
|
||||
|
||||
index = 0;
|
||||
@@ -1470,11 +1468,6 @@ next_child:
|
||||
|
||||
put_child:
|
||||
of_node_put(child_np);
|
||||
-disable_clks:
|
||||
- if (rphy->clk) {
|
||||
- clk_disable_unprepare(rphy->clk);
|
||||
- clk_put(rphy->clk);
|
||||
- }
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -1,55 +0,0 @@
|
||||
From 2e5ead8478e8e4a7b3d63a2001c2f0022b2f5e1b Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 22 May 2023 19:03:23 +0200
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: simplify getting match data
|
||||
|
||||
Simplify the code by directly getting the match data via
|
||||
device_get_match_data() instead of open coding its functionality.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Message-ID: <20230522170324.61349-7-sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 12 ++++--------
|
||||
1 file changed, 4 insertions(+), 8 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1305,7 +1305,6 @@ static int rockchip_usb2phy_probe(struct
|
||||
struct phy_provider *provider;
|
||||
struct rockchip_usb2phy *rphy;
|
||||
const struct rockchip_usb2phy_cfg *phy_cfgs;
|
||||
- const struct of_device_id *match;
|
||||
unsigned int reg;
|
||||
int index, ret;
|
||||
|
||||
@@ -1313,12 +1312,6 @@ static int rockchip_usb2phy_probe(struct
|
||||
if (!rphy)
|
||||
return -ENOMEM;
|
||||
|
||||
- match = of_match_device(dev->driver->of_match_table, dev);
|
||||
- if (!match || !match->data) {
|
||||
- dev_err(dev, "phy configs are not assigned!\n");
|
||||
- return -EINVAL;
|
||||
- }
|
||||
-
|
||||
if (!dev->parent || !dev->parent->of_node) {
|
||||
rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
|
||||
if (IS_ERR(rphy->grf)) {
|
||||
@@ -1359,12 +1352,15 @@ static int rockchip_usb2phy_probe(struct
|
||||
}
|
||||
|
||||
rphy->dev = dev;
|
||||
- phy_cfgs = match->data;
|
||||
+ phy_cfgs = device_get_match_data(dev);
|
||||
rphy->chg_state = USB_CHG_STATE_UNDEFINED;
|
||||
rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
|
||||
rphy->irq = platform_get_irq_optional(pdev, 0);
|
||||
platform_set_drvdata(pdev, rphy);
|
||||
|
||||
+ if (!phy_cfgs)
|
||||
+ return dev_err_probe(dev, -EINVAL, "phy configs are not assigned!\n");
|
||||
+
|
||||
ret = rockchip_usb2phy_extcon_register(rphy);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -1,28 +0,0 @@
|
||||
From e7254a4a7c444fa194440fa8dc73c7728e927162 Mon Sep 17 00:00:00 2001
|
||||
From: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Date: Mon, 22 May 2023 19:03:24 +0200
|
||||
Subject: [PATCH] phy: phy-rockchip-inno-usb2: improve error message
|
||||
|
||||
Printing the OF node is not useful, since we get the same information
|
||||
from the device context. Instead print the reg address, that could
|
||||
not be found.
|
||||
|
||||
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
|
||||
Message-ID: <20230522170324.61349-8-sebastian.reichel@collabora.com>
|
||||
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
||||
---
|
||||
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 3 +--
|
||||
1 file changed, 1 insertion(+), 2 deletions(-)
|
||||
|
||||
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
|
||||
@@ -1377,8 +1377,7 @@ static int rockchip_usb2phy_probe(struct
|
||||
} while (phy_cfgs[index].reg);
|
||||
|
||||
if (!rphy->phy_cfg) {
|
||||
- dev_err(dev, "no phy-config can be matched with %pOFn node\n",
|
||||
- np);
|
||||
+ dev_err(dev, "could not find phy config for reg=0x%08x\n", reg);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
@ -1,55 +0,0 @@
|
||||
From d980004e349049a3fcbffc6096d14896f6a122ed Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Date: Tue, 25 Oct 2022 14:41:30 +0200
|
||||
Subject: [PATCH] ASoC: rockchip: i2s_tdm: Make the grf property optional
|
||||
|
||||
Only IO Multiplex and two TRCM modes need access to the GRF, so
|
||||
making it a hard requirement is not a wise idea, as it complicates
|
||||
support for newer SoCs which do not do these things.
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20221025124132.399729-3-frattaroli.nicolas@gmail.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
sound/soc/rockchip/rockchip_i2s_tdm.c | 16 ++++++++++++----
|
||||
1 file changed, 12 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/sound/soc/rockchip/rockchip_i2s_tdm.c
|
||||
+++ b/sound/soc/rockchip/rockchip_i2s_tdm.c
|
||||
@@ -756,6 +756,12 @@ static int rockchip_i2s_io_multiplex(str
|
||||
if (!i2s_tdm->io_multiplex)
|
||||
return 0;
|
||||
|
||||
+ if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
|
||||
+ dev_err(i2s_tdm->dev,
|
||||
+ "io multiplex not supported for this device\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
|
||||
struct snd_pcm_str *playback_str =
|
||||
&substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
|
||||
@@ -1222,6 +1228,12 @@ static int common_soc_init(struct device
|
||||
if (trcm == TRCM_TXRX)
|
||||
return 0;
|
||||
|
||||
+ if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
|
||||
+ dev_err(i2s_tdm->dev,
|
||||
+ "no grf present but non-txrx TRCM specified\n");
|
||||
+ return -EINVAL;
|
||||
+ }
|
||||
+
|
||||
for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
|
||||
if (addr != configs[i].addr)
|
||||
continue;
|
||||
@@ -1568,10 +1580,6 @@ static int rockchip_i2s_tdm_probe(struct
|
||||
return ret;
|
||||
|
||||
i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
|
||||
- if (IS_ERR(i2s_tdm->grf))
|
||||
- return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->grf),
|
||||
- "Error in rockchip,grf\n");
|
||||
-
|
||||
i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
|
||||
"tx-m");
|
||||
if (IS_ERR(i2s_tdm->tx_reset)) {
|
||||
@ -1,33 +0,0 @@
|
||||
From c619bd4268ff9895760dab303b4eb15ed3d0f7e9 Mon Sep 17 00:00:00 2001
|
||||
From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Date: Tue, 25 Oct 2022 14:41:32 +0200
|
||||
Subject: [PATCH] ASoC: rockchip: i2s_tdm: Add support for RK3588
|
||||
|
||||
This adds support for the RK3588 SoC to the I2S/TDM driver.
|
||||
|
||||
Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20221025124132.399729-5-frattaroli.nicolas@gmail.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
sound/soc/rockchip/rockchip_i2s_tdm.c | 3 ++-
|
||||
1 file changed, 2 insertions(+), 1 deletion(-)
|
||||
|
||||
--- a/sound/soc/rockchip/rockchip_i2s_tdm.c
|
||||
+++ b/sound/soc/rockchip/rockchip_i2s_tdm.c
|
||||
@@ -1318,6 +1318,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
|
||||
{ .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
|
||||
{ .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
|
||||
+ { .compatible = "rockchip,rk3588-i2s-tdm" },
|
||||
{ .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
|
||||
{},
|
||||
};
|
||||
@@ -1556,7 +1557,7 @@ static int rockchip_i2s_tdm_probe(struct
|
||||
i2s_tdm->dev = &pdev->dev;
|
||||
|
||||
of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
|
||||
- if (!of_id || !of_id->data)
|
||||
+ if (!of_id)
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_init(&i2s_tdm->lock);
|
||||
@ -1,25 +0,0 @@
|
||||
From 0e6c37610934e9b91f6f5f2599de5e2f1ab59e72 Mon Sep 17 00:00:00 2001
|
||||
From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Date: Wed, 15 Mar 2023 13:48:03 +0200
|
||||
Subject: [PATCH] ASoC: rockchip: i2s: Add compatible for RK3588
|
||||
|
||||
The Rockchip I2S driver supports the RK3588/RK3588S SoCs, hence add the
|
||||
corresponding compatible string.
|
||||
|
||||
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230315114806.3819515-9-cristian.ciocaltea@collabora.com
|
||||
Signed-off-by: Mark Brown <broonie@kernel.org>
|
||||
---
|
||||
sound/soc/rockchip/rockchip_i2s.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
--- a/sound/soc/rockchip/rockchip_i2s.c
|
||||
+++ b/sound/soc/rockchip/rockchip_i2s.c
|
||||
@@ -659,6 +659,7 @@ static const struct of_device_id rockchi
|
||||
{ .compatible = "rockchip,rk3366-i2s", },
|
||||
{ .compatible = "rockchip,rk3368-i2s", },
|
||||
{ .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
|
||||
+ { .compatible = "rockchip,rk3588-i2s", },
|
||||
{ .compatible = "rockchip,rv1126-i2s", },
|
||||
{},
|
||||
};
|
||||
@ -1,147 +0,0 @@
|
||||
From fb1c13d595857ccff49cbb69ddcdc08594a832e7 Mon Sep 17 00:00:00 2001
|
||||
From: Simon Xue <xxm@rock-chips.com>
|
||||
Date: Sun, 4 Jun 2023 00:23:33 +0530
|
||||
Subject: [PATCH] iio: adc: rockchip_saradc: Add callback functions
|
||||
|
||||
Add start, read and power_down callback functions,
|
||||
which will help in adding new rockchip device support
|
||||
cleanly.
|
||||
|
||||
Signed-off-by: Simon Xue <xxm@rock-chips.com>
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230603185340.13838-2-shreeya.patel@collabora.com
|
||||
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
||||
---
|
||||
drivers/iio/adc/rockchip_saradc.c | 64 +++++++++++++++++++++++++++++++--------
|
||||
1 file changed, 52 insertions(+), 12 deletions(-)
|
||||
|
||||
--- a/drivers/iio/adc/rockchip_saradc.c
|
||||
+++ b/drivers/iio/adc/rockchip_saradc.c
|
||||
@@ -37,10 +37,15 @@
|
||||
#define SARADC_TIMEOUT msecs_to_jiffies(100)
|
||||
#define SARADC_MAX_CHANNELS 8
|
||||
|
||||
+struct rockchip_saradc;
|
||||
+
|
||||
struct rockchip_saradc_data {
|
||||
const struct iio_chan_spec *channels;
|
||||
int num_channels;
|
||||
unsigned long clk_rate;
|
||||
+ void (*start)(struct rockchip_saradc *info, int chn);
|
||||
+ int (*read)(struct rockchip_saradc *info);
|
||||
+ void (*power_down)(struct rockchip_saradc *info);
|
||||
};
|
||||
|
||||
struct rockchip_saradc {
|
||||
@@ -57,27 +62,50 @@ struct rockchip_saradc {
|
||||
struct notifier_block nb;
|
||||
};
|
||||
|
||||
-static void rockchip_saradc_power_down(struct rockchip_saradc *info)
|
||||
+static void rockchip_saradc_reset_controller(struct reset_control *reset);
|
||||
+
|
||||
+static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
|
||||
+{
|
||||
+ /* 8 clock periods as delay between power up and start cmd */
|
||||
+ writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
|
||||
+ /* Select the channel to be used and trigger conversion */
|
||||
+ writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
|
||||
+ SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
|
||||
+}
|
||||
+
|
||||
+static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
|
||||
+{
|
||||
+ info->data->start(info, chn);
|
||||
+}
|
||||
+
|
||||
+static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
|
||||
+{
|
||||
+ return readl_relaxed(info->regs + SARADC_DATA);
|
||||
+}
|
||||
+
|
||||
+static int rockchip_saradc_read(struct rockchip_saradc *info)
|
||||
+{
|
||||
+ return info->data->read(info);
|
||||
+}
|
||||
+
|
||||
+static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
|
||||
{
|
||||
- /* Clear irq & power down adc */
|
||||
writel_relaxed(0, info->regs + SARADC_CTRL);
|
||||
}
|
||||
|
||||
+static void rockchip_saradc_power_down(struct rockchip_saradc *info)
|
||||
+{
|
||||
+ if (info->data->power_down)
|
||||
+ info->data->power_down(info);
|
||||
+}
|
||||
+
|
||||
static int rockchip_saradc_conversion(struct rockchip_saradc *info,
|
||||
struct iio_chan_spec const *chan)
|
||||
{
|
||||
reinit_completion(&info->completion);
|
||||
|
||||
- /* 8 clock periods as delay between power up and start cmd */
|
||||
- writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
|
||||
-
|
||||
info->last_chan = chan;
|
||||
-
|
||||
- /* Select the channel to be used and trigger conversion */
|
||||
- writel(SARADC_CTRL_POWER_CTRL
|
||||
- | (chan->channel & SARADC_CTRL_CHN_MASK)
|
||||
- | SARADC_CTRL_IRQ_ENABLE,
|
||||
- info->regs + SARADC_CTRL);
|
||||
+ rockchip_saradc_start(info, chan->channel);
|
||||
|
||||
if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
|
||||
return -ETIMEDOUT;
|
||||
@@ -120,7 +148,7 @@ static irqreturn_t rockchip_saradc_isr(i
|
||||
struct rockchip_saradc *info = dev_id;
|
||||
|
||||
/* Read value */
|
||||
- info->last_val = readl_relaxed(info->regs + SARADC_DATA);
|
||||
+ info->last_val = rockchip_saradc_read(info);
|
||||
info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
|
||||
|
||||
rockchip_saradc_power_down(info);
|
||||
@@ -160,6 +188,9 @@ static const struct rockchip_saradc_data
|
||||
.channels = rockchip_saradc_iio_channels,
|
||||
.num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
|
||||
.clk_rate = 1000000,
|
||||
+ .start = rockchip_saradc_start_v1,
|
||||
+ .read = rockchip_saradc_read_v1,
|
||||
+ .power_down = rockchip_saradc_power_down_v1,
|
||||
};
|
||||
|
||||
static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
|
||||
@@ -171,6 +202,9 @@ static const struct rockchip_saradc_data
|
||||
.channels = rockchip_rk3066_tsadc_iio_channels,
|
||||
.num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
|
||||
.clk_rate = 50000,
|
||||
+ .start = rockchip_saradc_start_v1,
|
||||
+ .read = rockchip_saradc_read_v1,
|
||||
+ .power_down = rockchip_saradc_power_down_v1,
|
||||
};
|
||||
|
||||
static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
|
||||
@@ -186,6 +220,9 @@ static const struct rockchip_saradc_data
|
||||
.channels = rockchip_rk3399_saradc_iio_channels,
|
||||
.num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
|
||||
.clk_rate = 1000000,
|
||||
+ .start = rockchip_saradc_start_v1,
|
||||
+ .read = rockchip_saradc_read_v1,
|
||||
+ .power_down = rockchip_saradc_power_down_v1,
|
||||
};
|
||||
|
||||
static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
|
||||
@@ -203,6 +240,9 @@ static const struct rockchip_saradc_data
|
||||
.channels = rockchip_rk3568_saradc_iio_channels,
|
||||
.num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
|
||||
.clk_rate = 1000000,
|
||||
+ .start = rockchip_saradc_start_v1,
|
||||
+ .read = rockchip_saradc_read_v1,
|
||||
+ .power_down = rockchip_saradc_power_down_v1,
|
||||
};
|
||||
|
||||
static const struct of_device_id rockchip_saradc_match[] = {
|
||||
@ -1,132 +0,0 @@
|
||||
From 757953f8ec6916084e0c22218d1d0482e9fc6682 Mon Sep 17 00:00:00 2001
|
||||
From: Simon Xue <xxm@rock-chips.com>
|
||||
Date: Sun, 4 Jun 2023 00:23:34 +0530
|
||||
Subject: [PATCH] iio: adc: rockchip_saradc: Add support for RK3588
|
||||
|
||||
Add new start and read functions to support rk3588 device.
|
||||
Also, add a device compatible string for the same.
|
||||
|
||||
Signed-off-by: Simon Xue <xxm@rock-chips.com>
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230603185340.13838-3-shreeya.patel@collabora.com
|
||||
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
||||
---
|
||||
drivers/iio/adc/rockchip_saradc.c | 70 +++++++++++++++++++++++++++++++++++++++
|
||||
1 file changed, 70 insertions(+)
|
||||
|
||||
--- a/drivers/iio/adc/rockchip_saradc.c
|
||||
+++ b/drivers/iio/adc/rockchip_saradc.c
|
||||
@@ -4,6 +4,7 @@
|
||||
* Copyright (C) 2014 ROCKCHIP, Inc.
|
||||
*/
|
||||
|
||||
+#include <linux/bitfield.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
@@ -37,6 +38,22 @@
|
||||
#define SARADC_TIMEOUT msecs_to_jiffies(100)
|
||||
#define SARADC_MAX_CHANNELS 8
|
||||
|
||||
+/* v2 registers */
|
||||
+#define SARADC2_CONV_CON 0x000
|
||||
+#define SARADC_T_PD_SOC 0x004
|
||||
+#define SARADC_T_DAS_SOC 0x00c
|
||||
+#define SARADC2_END_INT_EN 0x104
|
||||
+#define SARADC2_ST_CON 0x108
|
||||
+#define SARADC2_STATUS 0x10c
|
||||
+#define SARADC2_END_INT_ST 0x110
|
||||
+#define SARADC2_DATA_BASE 0x120
|
||||
+
|
||||
+#define SARADC2_EN_END_INT BIT(0)
|
||||
+#define SARADC2_START BIT(4)
|
||||
+#define SARADC2_SINGLE_MODE BIT(5)
|
||||
+
|
||||
+#define SARADC2_CONV_CHANNELS GENMASK(15, 0)
|
||||
+
|
||||
struct rockchip_saradc;
|
||||
|
||||
struct rockchip_saradc_data {
|
||||
@@ -73,6 +90,25 @@ static void rockchip_saradc_start_v1(str
|
||||
SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
|
||||
}
|
||||
|
||||
+static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
|
||||
+{
|
||||
+ int val;
|
||||
+
|
||||
+ if (info->reset)
|
||||
+ rockchip_saradc_reset_controller(info->reset);
|
||||
+
|
||||
+ writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
|
||||
+ writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
|
||||
+ val = FIELD_PREP(SARADC2_EN_END_INT, 1);
|
||||
+ val |= val << 16;
|
||||
+ writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
|
||||
+ val = FIELD_PREP(SARADC2_START, 1) |
|
||||
+ FIELD_PREP(SARADC2_SINGLE_MODE, 1) |
|
||||
+ FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
|
||||
+ val |= val << 16;
|
||||
+ writel(val, info->regs + SARADC2_CONV_CON);
|
||||
+}
|
||||
+
|
||||
static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
|
||||
{
|
||||
info->data->start(info, chn);
|
||||
@@ -83,6 +119,18 @@ static int rockchip_saradc_read_v1(struc
|
||||
return readl_relaxed(info->regs + SARADC_DATA);
|
||||
}
|
||||
|
||||
+static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
|
||||
+{
|
||||
+ int offset;
|
||||
+
|
||||
+ /* Clear irq */
|
||||
+ writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
|
||||
+
|
||||
+ offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
|
||||
+
|
||||
+ return readl_relaxed(info->regs + offset);
|
||||
+}
|
||||
+
|
||||
static int rockchip_saradc_read(struct rockchip_saradc *info)
|
||||
{
|
||||
return info->data->read(info);
|
||||
@@ -245,6 +293,25 @@ static const struct rockchip_saradc_data
|
||||
.power_down = rockchip_saradc_power_down_v1,
|
||||
};
|
||||
|
||||
+static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
|
||||
+ SARADC_CHANNEL(0, "adc0", 12),
|
||||
+ SARADC_CHANNEL(1, "adc1", 12),
|
||||
+ SARADC_CHANNEL(2, "adc2", 12),
|
||||
+ SARADC_CHANNEL(3, "adc3", 12),
|
||||
+ SARADC_CHANNEL(4, "adc4", 12),
|
||||
+ SARADC_CHANNEL(5, "adc5", 12),
|
||||
+ SARADC_CHANNEL(6, "adc6", 12),
|
||||
+ SARADC_CHANNEL(7, "adc7", 12),
|
||||
+};
|
||||
+
|
||||
+static const struct rockchip_saradc_data rk3588_saradc_data = {
|
||||
+ .channels = rockchip_rk3588_saradc_iio_channels,
|
||||
+ .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
|
||||
+ .clk_rate = 1000000,
|
||||
+ .start = rockchip_saradc_start_v2,
|
||||
+ .read = rockchip_saradc_read_v2,
|
||||
+};
|
||||
+
|
||||
static const struct of_device_id rockchip_saradc_match[] = {
|
||||
{
|
||||
.compatible = "rockchip,saradc",
|
||||
@@ -258,6 +325,9 @@ static const struct of_device_id rockchi
|
||||
}, {
|
||||
.compatible = "rockchip,rk3568-saradc",
|
||||
.data = &rk3568_saradc_data,
|
||||
+ }, {
|
||||
+ .compatible = "rockchip,rk3588-saradc",
|
||||
+ .data = &rk3588_saradc_data,
|
||||
},
|
||||
{},
|
||||
};
|
||||
@ -1,96 +0,0 @@
|
||||
From 97ad10bb2901738b87b02a8fbf02215f1f198bdb Mon Sep 17 00:00:00 2001
|
||||
From: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Date: Sun, 4 Jun 2023 00:23:35 +0530
|
||||
Subject: [PATCH] iio: adc: rockchip_saradc: Make use of devm_clk_get_enabled
|
||||
|
||||
Use devm_clk_get_enabled() to avoid manually disabling the
|
||||
clock.
|
||||
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230603185340.13838-4-shreeya.patel@collabora.com
|
||||
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
||||
---
|
||||
drivers/iio/adc/rockchip_saradc.c | 56 ++++++---------------------------------
|
||||
1 file changed, 8 insertions(+), 48 deletions(-)
|
||||
|
||||
--- a/drivers/iio/adc/rockchip_saradc.c
|
||||
+++ b/drivers/iio/adc/rockchip_saradc.c
|
||||
@@ -343,20 +343,6 @@ static void rockchip_saradc_reset_contro
|
||||
reset_control_deassert(reset);
|
||||
}
|
||||
|
||||
-static void rockchip_saradc_clk_disable(void *data)
|
||||
-{
|
||||
- struct rockchip_saradc *info = data;
|
||||
-
|
||||
- clk_disable_unprepare(info->clk);
|
||||
-}
|
||||
-
|
||||
-static void rockchip_saradc_pclk_disable(void *data)
|
||||
-{
|
||||
- struct rockchip_saradc *info = data;
|
||||
-
|
||||
- clk_disable_unprepare(info->pclk);
|
||||
-}
|
||||
-
|
||||
static void rockchip_saradc_regulator_disable(void *data)
|
||||
{
|
||||
struct rockchip_saradc *info = data;
|
||||
@@ -490,16 +476,6 @@ static int rockchip_saradc_probe(struct
|
||||
return ret;
|
||||
}
|
||||
|
||||
- info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
|
||||
- if (IS_ERR(info->pclk))
|
||||
- return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
|
||||
- "failed to get pclk\n");
|
||||
-
|
||||
- info->clk = devm_clk_get(&pdev->dev, "saradc");
|
||||
- if (IS_ERR(info->clk))
|
||||
- return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
|
||||
- "failed to get adc clock\n");
|
||||
-
|
||||
info->vref = devm_regulator_get(&pdev->dev, "vref");
|
||||
if (IS_ERR(info->vref))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
|
||||
@@ -537,31 +513,15 @@ static int rockchip_saradc_probe(struct
|
||||
|
||||
info->uv_vref = ret;
|
||||
|
||||
- ret = clk_prepare_enable(info->pclk);
|
||||
- if (ret < 0) {
|
||||
- dev_err(&pdev->dev, "failed to enable pclk\n");
|
||||
- return ret;
|
||||
- }
|
||||
- ret = devm_add_action_or_reset(&pdev->dev,
|
||||
- rockchip_saradc_pclk_disable, info);
|
||||
- if (ret) {
|
||||
- dev_err(&pdev->dev, "failed to register devm action, %d\n",
|
||||
- ret);
|
||||
- return ret;
|
||||
- }
|
||||
+ info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
|
||||
+ if (IS_ERR(info->pclk))
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
|
||||
+ "failed to get pclk\n");
|
||||
|
||||
- ret = clk_prepare_enable(info->clk);
|
||||
- if (ret < 0) {
|
||||
- dev_err(&pdev->dev, "failed to enable converter clock\n");
|
||||
- return ret;
|
||||
- }
|
||||
- ret = devm_add_action_or_reset(&pdev->dev,
|
||||
- rockchip_saradc_clk_disable, info);
|
||||
- if (ret) {
|
||||
- dev_err(&pdev->dev, "failed to register devm action, %d\n",
|
||||
- ret);
|
||||
- return ret;
|
||||
- }
|
||||
+ info->clk = devm_clk_get_enabled(&pdev->dev, "saradc");
|
||||
+ if (IS_ERR(info->clk))
|
||||
+ return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
|
||||
+ "failed to get adc clock\n");
|
||||
|
||||
platform_set_drvdata(pdev, indio_dev);
|
||||
|
||||
@ -1,47 +0,0 @@
|
||||
From 47902344c8c35c1c08147df08879ef75a3ff86c1 Mon Sep 17 00:00:00 2001
|
||||
From: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Date: Sun, 4 Jun 2023 00:23:36 +0530
|
||||
Subject: [PATCH] iio: adc: rockchip_saradc: Use of_device_get_match_data
|
||||
|
||||
Use of_device_get_match_data() to simplify the code.
|
||||
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
|
||||
Link: https://lore.kernel.org/r/20230603185340.13838-5-shreeya.patel@collabora.com
|
||||
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
||||
---
|
||||
drivers/iio/adc/rockchip_saradc.c | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
--- a/drivers/iio/adc/rockchip_saradc.c
|
||||
+++ b/drivers/iio/adc/rockchip_saradc.c
|
||||
@@ -412,10 +412,10 @@ static void rockchip_saradc_regulator_un
|
||||
|
||||
static int rockchip_saradc_probe(struct platform_device *pdev)
|
||||
{
|
||||
+ const struct rockchip_saradc_data *match_data;
|
||||
struct rockchip_saradc *info = NULL;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct iio_dev *indio_dev = NULL;
|
||||
- const struct of_device_id *match;
|
||||
int ret;
|
||||
int irq;
|
||||
|
||||
@@ -429,13 +429,13 @@ static int rockchip_saradc_probe(struct
|
||||
}
|
||||
info = iio_priv(indio_dev);
|
||||
|
||||
- match = of_match_device(rockchip_saradc_match, &pdev->dev);
|
||||
- if (!match) {
|
||||
+ match_data = of_device_get_match_data(&pdev->dev);
|
||||
+ if (!match_data) {
|
||||
dev_err(&pdev->dev, "failed to match device\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
- info->data = match->data;
|
||||
+ info->data = match_data;
|
||||
|
||||
/* Sanity check for possible later IP variants with more channels */
|
||||
if (info->data->num_channels > SARADC_MAX_CHANNELS) {
|
||||
@ -1,38 +0,0 @@
|
||||
From 10bec68f51ee1564fc2b6dcc25ccec22a01b22f9 Mon Sep 17 00:00:00 2001
|
||||
From: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Date: Sun, 4 Jun 2023 00:23:37 +0530
|
||||
Subject: [PATCH] iio: adc: rockchip_saradc: Match alignment with open parenthesis
|
||||
|
||||
Match alignment with open parenthesis for improving the code
|
||||
readability.
|
||||
|
||||
Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
|
||||
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
|
||||
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
Link: https://lore.kernel.org/r/20230603185340.13838-6-shreeya.patel@collabora.com
|
||||
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
|
||||
---
|
||||
drivers/iio/adc/rockchip_saradc.c | 5 ++---
|
||||
1 file changed, 2 insertions(+), 3 deletions(-)
|
||||
|
||||
--- a/drivers/iio/adc/rockchip_saradc.c
|
||||
+++ b/drivers/iio/adc/rockchip_saradc.c
|
||||
@@ -148,7 +148,7 @@ static void rockchip_saradc_power_down(s
|
||||
}
|
||||
|
||||
static int rockchip_saradc_conversion(struct rockchip_saradc *info,
|
||||
- struct iio_chan_spec const *chan)
|
||||
+ struct iio_chan_spec const *chan)
|
||||
{
|
||||
reinit_completion(&info->completion);
|
||||
|
||||
@@ -391,8 +391,7 @@ out:
|
||||
}
|
||||
|
||||
static int rockchip_saradc_volt_notify(struct notifier_block *nb,
|
||||
- unsigned long event,
|
||||
- void *data)
|
||||
+ unsigned long event, void *data)
|
||||
{
|
||||
struct rockchip_saradc *info =
|
||||
container_of(nb, struct rockchip_saradc, nb);
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user